| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | samsung-pinctrl.txt | 6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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| D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
9 GPIO base, IO control registers
11 - #gpio-cells:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
24 Interrupt ID
26 - interrupt-controller:
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| D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
23 - reg:
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| /kernel/linux/linux-5.10/drivers/hwmon/ |
| D | npcm750-pwm-fan.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
7 #include <linux/hwmon-sysfs.h>
8 #include <linux/interrupt.h>
19 #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L)) argument
21 #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00) argument
22 #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04) argument
23 #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08) argument
24 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \ argument
25 (NPCM7XX_PWM_REG_BASE(base, n) + 0x0C + (12 * (ch)))
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-mbigen.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/interrupt.h>
19 /* Interrupt numbers per mbigen node supported */
22 /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
45 * of interrupt
50 * offset of interrupt type register
51 * This register is used to configure interrupt
57 * struct mbigen_device - holds the information of mbigen device.
60 * @base: mapped address of this mbigen chip.
64 void __iomem *base; member
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| D | irq-gic-v2m.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
5 * implement ARM Generic Interrupt Controller: GICv2m.
16 #include <linux/dma-iommu.h>
26 #include <linux/irqchip/arm-gic.h>
49 /* APM X-Gene with GICv2m MSI_IIDR register value */
66 void __iomem *base; /* GICv2m virt address */ member
102 if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) in gicv2m_get_msi_addr()
103 return v2m->res.start | ((hwirq - 32) << 3); in gicv2m_get_msi_addr()
105 return v2m->res.start + V2M_MSI_SETSPI_NS; in gicv2m_get_msi_addr()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
| D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cci.txt | 5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
35 of cells, containing base and size.
36 Definition: A standard property. Specifies base physical
40 - ranges:
43 as a tuple of cells, containing child address,
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| /kernel/linux/linux-5.10/arch/mips/pci/ |
| D | pci-rt3883.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
15 #include <linux/interrupt.h>
21 #include <asm/mach-ralink/rt3883.h>
22 #include <asm/mach-ralink/ralink_regs.h>
59 void __iomem *base; member
76 hose = (struct pci_controller *) bus->sysdata; in pci_bus_to_rt3883_controller()
83 return ioread32(rpc->base + reg); in rt3883_pci_r32()
89 iowrite32(val, rpc->base + reg); in rt3883_pci_w32()
146 irq = irq_find_mapping(rpc->irq_domain, bit); in rt3883_pci_irq_handler()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/dove/ |
| D | pmu.txt | 4 - compatible: value should be "marvell,dove-pmu".
5 May also include "simple-bus" if there are child devices, in which
7 - reg: two base addresses and sizes of the PM controller and PMU.
8 - interrupts: single interrupt number for the PMU interrupt
9 - interrupt-controller: must be specified as the PMU itself is an
10 interrupt controller.
11 - #interrupt-cells: must be 1.
12 - #reset-cells: must be 1.
13 - domains: sub-node containing domain descriptions
16 - ranges: defines the address mapping for child devices, as per the
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
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| /kernel/linux/linux-5.10/drivers/mfd/ |
| D | mfd-core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mfd/mfd-core.c
40 if (!cell->enable) { in mfd_cell_enable()
41 dev_dbg(&pdev->dev, "No .enable() call-back registered\n"); in mfd_cell_enable()
45 return cell->enable(pdev); in mfd_cell_enable()
53 if (!cell->disable) { in mfd_cell_disable()
54 dev_dbg(&pdev->dev, "No .disable() call-back registered\n"); in mfd_cell_disable()
58 return cell->disable(pdev); in mfd_cell_disable()
66 const struct mfd_cell_acpi_match *match = cell->acpi_match; in mfd_acpi_add_device()
67 struct acpi_device *parent, *child; in mfd_acpi_add_device() local
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| D | twl-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * twl_core.c - driver for TWL4030/TWL5030/TWL60X0/TPS659x0 PM
6 * Copyright (C) 2005-2006 Texas Instruments, Inc.
8 * Modifications to defer interrupt handling to a kernel thread:
37 #include <linux/mfd/twl4030-audio.h>
39 #include "twl-core.h"
42 * The TWL4030 "Triton 2" is one of a family of a multi-function "Power
45 * often at around 3 Mbit/sec, including for interrupt handling.
50 * FIXME this driver currently requires use of the first interrupt line
58 /* Base Address defns for twl4030_map[] */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-host.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
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| D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
26 2) Child nodes
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | octeon-usb.txt | 7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
31 2) Child node
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | omap-mailbox.txt | 5 using a queued mailbox interrupt mechanism. The IP block is external to the
8 interrupt configuration registers.
11 interrupt lines. An output interrupt line is routed to an interrupt controller
13 specific processor's interrupt controller. The interrupt line connections are
15 (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
16 programmable through a set of interrupt configuration registers, and have a rx
17 and tx interrupt source per h/w fifo. Communication between different processors
18 is achieved through the appropriate programming of the rx and tx interrupt
19 sources on the appropriate interrupt lines.
21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
96 * (direction, retime-type, retime-clk, retime-delay)
98 * +----------------+
99 *[31:28]| reserved-3 |
100 * +----------------+-------------
102 * +----------------+ v
104 * +----------------+ ^
106 * +----------------+-------------
107 *[24] | reserved-2 |
108 * +----------------+-------------
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-ixp4xx.c | 1 // SPDX-License-Identifier: GPL-2.0
6 // based on previous work and know-how from:
18 #include <linux/irqchip/irq-ixp4xx.h>
20 #include <asm/mach-types.h>
32 * The hardware uses 3 bits to indicate interrupt "style".
46 * struct ixp4xx_gpio - IXP4 GPIO state container
50 * @base: remapped I/O-memory base
51 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
58 void __iomem *base; member
67 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | amlogic,meson-mx-sdio.txt | 13 - compatible : must be one of
14 - "amlogic,meson8-sdio"
15 - "amlogic,meson8b-sdio"
16 along with the generic "amlogic,meson-mx-sdio"
17 - reg : mmc controller base registers
18 - interrupts : mmc controller interrupt
19 - #address-cells : must be 1
20 - size-cells : must be 0
21 - clocks : phandle to clock providers
22 - clock-names : must contain "core" and "clkin"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/dsa/ |
| D | marvell.txt | 2 ---------------------------------------
11 placed as a child node of an mdio device.
17 which is at a different MDIO base address in different switch families.
18 - "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
22 - "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
24 - "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
28 - compatible : Should be one of "marvell,mv88e6085",
31 - reg : Address on the MII bus for the switch.
35 - reset-gpios : Should be a gpio specifier for a reset line
36 - interrupts : Interrupt from the switch
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| /kernel/linux/linux-5.10/drivers/usb/cdns3/ |
| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 NXP
6 * Copyright (C) 2018-2019 Cadence.
20 * struct cdns3_role_driver - host/gadget role driver
50 * struct cdns3 - Representation of Cadence USB3 DRD controller.
52 * @xhci_regs: pointer to base of xhci registers
54 * @dev_regs: pointer to base of dev registers
56 * @otg_v0_regs: pointer to base of v0 otg registers
57 * @otg_v1_regs: pointer to base of v1 otg registers
58 * @otg_regs: pointer to base of otg registers
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec6.txt | 4 -SEC 6 Node
5 -Job Ring Node
6 -Full Example
13 Node defines the base address of the SEC 6 block.
20 - compatible
23 Definition: Must include "fsl,sec-v6.0".
25 - fsl,sec-era
31 - #address-cells
35 for representing physical addresses in child nodes.
37 - #size-cells
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
7 Ethernet controllers connected to TI GPMC are represented as child nodes of
10 All timing relevant properties as well as generic GPMC child properties are
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
[all …]
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