| /kernel/linux/linux-5.10/include/linux/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/clk.h
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
17 struct clk;
22 * DOC: clk notifier callback types
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
32 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
45 * @clk: struct clk * to associate the notifier with
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
20 Select this option when the clock API in <linux/clk.h> is implemented
23 'struct clk'.
34 clk, useful across many platforms, as well as an
35 implementation of the clock API in include/linux/clk.h.
36 Architectures utilizing the common struct clk should select
48 source "drivers/clk/versatile/Kconfig"
76 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
86 multi-function device has one fixed-rate oscillator, clocked
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | spear-cpufreq.c | 2 * drivers/cpufreq/spear-cpufreq.c
16 #include <linux/clk.h>
28 struct clk *clk; member
34 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq) in spear1340_cpu_get_possible_parent()
36 struct clk *sys_pclk; in spear1340_cpu_get_possible_parent()
39 * In SPEAr1340, cpu clk's parent sys clk can take input from in spear1340_cpu_get_possible_parent()
50 * As sys clk can have multiple source with their own range in spear1340_cpu_get_possible_parent()
60 return ERR_PTR(-EINVAL); in spear1340_cpu_get_possible_parent()
72 * access a source clock (clk) which might not be ancestor of cpu at present.
73 * Hence in SPEAr1340 we would operate on source clock directly before switching
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| D | tegra124-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
21 struct clk *cpu_clk;
22 struct clk *pllp_clk;
23 struct clk *pllx_clk;
24 struct clk *dfll_clk;
30 struct clk *orig_parent; in tegra124_cpu_switch_to_dfll()
33 ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk)); in tegra124_cpu_switch_to_dfll()
37 orig_parent = clk_get_parent(priv->cpu_clk); in tegra124_cpu_switch_to_dfll()
38 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-super.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
13 #include "clk.h"
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
38 u8 source, shift; in clk_super_get_parent() local
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
50 source = (val >> shift) & super_state_to_src_mask(mux); in clk_super_get_parent()
54 * PLLX/2 is the input source to CCLKLP. in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
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| D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clk/tegra.h>
15 #include "clk.h"
37 struct clk *parents[8];
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
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| D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
12 #include <linux/clk.h>
26 #include "clk.h"
48 * clock source as the current parent, we must first change to a backup
49 * timing that has a different clock source.
67 struct clk *parent;
74 struct clk *prev_parent;
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
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| D | clk-audio-sync.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
10 #include "clk.h"
17 return sync->rate; in clk_sync_source_recalc_rate()
25 if (rate > sync->max_rate) in clk_sync_source_round_rate()
26 return -EINVAL; in clk_sync_source_round_rate()
36 sync->rate = rate; in clk_sync_source_set_rate()
46 struct clk *tegra_clk_register_sync_source(const char *name, in tegra_clk_register_sync_source()
51 struct clk *clk; in tegra_clk_register_sync_source() local
55 pr_err("%s: could not allocate sync source clk\n", __func__); in tegra_clk_register_sync_source()
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-nps.c | 7 * COPYING in the main directory of this source tree, or the
10 * Redistribution and use in source and binary forms, with or
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
36 #include <linux/clk.h>
51 struct clk **clk) in nps_get_timer_clk() argument
55 *clk = of_clk_get(node, 0); in nps_get_timer_clk()
56 ret = PTR_ERR_OR_ZERO(*clk); in nps_get_timer_clk()
58 pr_err("timer missing clk\n"); in nps_get_timer_clk()
62 ret = clk_prepare_enable(*clk); in nps_get_timer_clk()
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| D | timer-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is diabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
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| D | timer-cadence-ttc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
10 #include <linux/clk.h>
22 * This driver configures the 2 16/32-bit count-up timers as follows:
25 * T2: Timer 2, clockevent source for hrtimers
29 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
33 * obtained from device tree. The pre-scaler of 32 is used.
49 #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
54 * Setup the timers to use pre-scaling, using a fixed value for now that will
59 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
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| /kernel/linux/linux-5.10/drivers/net/can/mscan/ |
| D | mpc5xxx_can.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
19 #include <linux/clk.h>
36 { .compatible = "fsl,mpc5200-cdm", },
53 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
74 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
80 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
84 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
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| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
37 uint32_t source : 8; /* source index + 1 (0 == none) */ member
46 /* For fixed-factor ones */
66 .source = 1 + R9A06G032_##_src, .name = _n, \
70 .source = 1 + R9A06G032_##_src, .name = _n, \
77 .source = 1 + R9A06G032_##_src, .name = _n, \
81 .source = 1 + R9A06G032_##_src, .name = _n, \
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-s3c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
18 #include <linux/clk.h>
104 * struct sdhci_s3c - S3C SDHCI instance
114 * @no_divider: No or non-standard internal clock divider.
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
132 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
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| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | pwm-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.txt | 4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
14 "nvidia,tegra20-i2c-dvc".
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
16 master and slave mode of I2C communication. The i2c-tegra driver only
18 only compatible with "nvidia,tegra20-i2c".
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | davinci_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2006-2013 Texas Instruments.
21 #include <linux/clk.h>
24 #define MODULE_NAME "DAVINCI-WDT: "
60 * @base - base io address of WD device
61 * @clk - source clock of WDT
62 * @wdd - hold watchdog device as is in WDT core
66 struct clk *clk; member
77 wdt_freq = clk_get_rate(davinci_wdt->clk); in davinci_wdt_start()
79 /* disable, internal clock source */ in davinci_wdt_start()
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-regmap-mux-div.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
14 * struct mux_div_clk - combined mux/divider clock
18 * @src_width: number of bits in source select
19 * @src_shift: lowest bit of source select field
23 * @clkr: handle between common and hardware-specific interfaces
37 struct clk *pclk;
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| /kernel/linux/linux-5.10/drivers/acpi/ |
| D | acpi_apd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
15 #include <linux/platform_data/clk-fch.h>
23 * struct apd_device_desc - a descriptor for apd device
24 * @fixed_clk_rate: fixed rate input clock source for acpi device;
25 * 0 means no fixed rate input clock source
26 * @properties: build-in properties of the device such as UART
38 struct clk *clk; member
48 const struct apd_device_desc *dev_desc = pdata->dev_desc; in acpi_apd_setup()
49 struct clk *clk; in acpi_apd_setup() local
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| /kernel/liteos_a/testsuites/unittest/libc/time/clock/full/ |
| D | clock_test_009.cpp | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without modification,
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
45 clockid_t clk = CLOCK_MONOTONIC_RAW; in ClockTest() local
51 ret = clock_getres(clk, &res); in ClockTest()
57 ret = clock_gettime(clk, &oldtp); in ClockTest()
65 ret = clock_settime(clk, &tp); in ClockTest()
66 ICUNIT_ASSERT_EQUAL(ret, -1, ret); in ClockTest()
72 ret = clock_gettime(clk, &tp); in ClockTest()
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| D | clock_test_007.cpp | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without modification,
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
45 clockid_t clk = CLOCK_MONOTONIC_COARSE; in ClockTest() local
50 ret = clock_getres(clk, &res); in ClockTest()
56 ret = clock_gettime(clk, &oldtp); in ClockTest()
64 ret = clock_settime(clk, &tp); in ClockTest()
65 ICUNIT_ASSERT_EQUAL(ret, -1, ret); in ClockTest()
71 ret = clock_gettime(clk, &tp); in ClockTest()
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| D | clock_test_008.cpp | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without modification,
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
45 clockid_t clk = CLOCK_MONOTONIC; in ClockTest() local
51 ret = clock_getres(clk, &res); in ClockTest()
57 ret = clock_gettime(clk, &oldtp); in ClockTest()
65 ret = clock_settime(clk, &tp); in ClockTest()
66 ICUNIT_ASSERT_EQUAL(ret, -1, ret); in ClockTest()
72 ret = clock_gettime(clk, &tp); in ClockTest()
|
| D | clock_test_006.cpp | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without modification,
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
45 clockid_t clk = CLOCK_REALTIME_COARSE; in ClockTest() local
51 ret = clock_getres(clk, &res); in ClockTest()
57 ret = clock_gettime(clk, &oldtp); in ClockTest()
65 ret = clock_settime(clk, &tp); in ClockTest()
66 ICUNIT_ASSERT_EQUAL(ret, -1, ret); in ClockTest()
72 ret = clock_gettime(clk, &tp); in ClockTest()
|
| D | clock_test_001.cpp | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without modification,
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
45 clockid_t clk = CLOCK_REALTIME; in ClockTest() local
51 ret = clock_getres(clk, &res); in ClockTest()
57 ret = clock_gettime(clk, &oldtp); in ClockTest()
68 ret = clock_settime(clk, &tp); in ClockTest()
75 ret = clock_gettime(clk, &tp); in ClockTest()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv50.c | 32 read_div(struct nv50_clk *clk) in read_div() argument
34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
52 read_pll_src(struct nv50_clk *clk, u32 base) in read_pll_src() argument
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll_src()
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