| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-cadence-sierra.txt | 2 -----------------------
5 - compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
6 Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
7 - resets: Must contain an entry for each in reset-names.
9 - reset-names: Must include "sierra_reset" and "sierra_apb".
13 - reg: register range for the PHY.
14 - #address-cells: Must be 1
15 - #size-cells: Must be 0
18 - clocks: Must contain an entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
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| D | nvidia,tegra124-xusb-padctl.txt | 4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
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| D | phy-cadence-torrent.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | ti,cal.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
15 processing capability to connect CSI2 image-sensor modules to the
21 Documentation/devicetree/bindings/media/video-interfaces.txt.
27 - ti,dra72-cal
29 - ti,dra72-pre-es2-cal
31 - ti,dra76-cal
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| D | samsung-mipi-csis.txt | 1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
2 -------------------------------------------------------------
6 - compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110),
7 "samsung,exynos4210-csis" for Exynos4210 (S5PC210),
8 "samsung,exynos4212-csis" for Exynos4212/Exynos4412,
9 "samsung,exynos5250-csis" for Exynos5250;
10 - reg : offset and length of the register set for the device;
11 - interrupts : should contain MIPI CSIS interrupt; the format of the
13 - bus-width : maximum number of data lanes supported (SoC specific);
14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
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| D | imx7-mipi-csi2.txt | 5 --------------
7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
8 compatible with previous version of Samsung D-phy.
12 - compatible : "fsl,imx7-mipi-csi2";
13 - reg : base address and length of the register set for the device;
14 - interrupts : should contain MIPI CSIS interrupt;
15 - clocks : list of clock specifiers, see
16 Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17 - clock-names : must contain "pclk", "wrap" and "phy" entries, matching
18 entries in the clock property;
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| D | renesas,csi2.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car MIPI CSI-2 receiver
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the
15 Renesas R-Car and RZ/G2 family of devices. It is used in conjunction with the
16 R-Car VIN module, which provides the video capture capabilities.
21 - enum:
22 - renesas,r8a774a1-csi2 # RZ/G2M
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| D | qcom,camss.txt | 5 - compatible:
9 - "qcom,msm8916-camss"
10 - "qcom,msm8996-camss"
11 - reg:
13 Value type: <prop-encoded-array>
14 Definition: Register ranges as listed in the reg-names property.
15 - reg-names:
19 - "csiphy0"
20 - "csiphy0_clk_mux"
21 - "csiphy1"
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| D | samsung-s5k5baf.txt | 2 --------------------------------------------------------------------
6 - compatible : "samsung,s5k5baf";
7 - reg : I2C slave address of the sensor;
8 - vdda-supply : analog power supply 2.8V (2.6V to 3.0V);
9 - vddreg-supply : regulator input power supply 1.8V (1.7V to 1.9V)
11 - vddio-supply : I/O power supply 1.8V (1.65V to 1.95V)
13 - stbyn-gpios : GPIO connected to STDBYN pin;
14 - rstn-gpios : GPIO connected to RSTN pin;
15 - clocks : list of phandle and clock specifier pairs
16 according to common clock bindings for the
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| D | video-interfaces.txt | 4 ---------------
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
55 and data-shift properties can be used to assign physical data lines to each
59 --------------------------------
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,csi2rxss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@xilinx.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/ |
| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
10 source, the clock input is named "refclk".
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
[all …]
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| D | ov2680.txt | 1 * Omnivision OV2680 MIPI CSI-2 sensor
4 - compatible: should be "ovti,ov2680".
5 - clocks: reference to the xvclk input clock.
6 - clock-names: should be "xvclk".
7 - DOVDD-supply: Digital I/O voltage supply.
8 - DVDD-supply: Digital core voltage supply.
9 - AVDD-supply: Analog voltage supply.
12 - reset-gpios: reference to the GPIO connected to the powerdown/reset pin,
18 Documentation/devicetree/bindings/media/video-interfaces.txt.
20 Endpoint node required properties for CSI-2 connection are:
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| D | ov5640.txt | 1 * Omnivision OV5640 MIPI CSI-2 / parallel sensor
4 - compatible: should be "ovti,ov5640"
5 - clocks: reference to the xclk input clock.
6 - clock-names: should be "xclk".
7 - DOVDD-supply: Digital I/O voltage supply, 1.8 volts
8 - AVDD-supply: Analog voltage supply, 2.8 volts
9 - DVDD-supply: Digital core voltage supply, 1.5 volts
12 - reset-gpios: reference to the GPIO connected to the reset pin, if any.
14 - powerdown-gpios: reference to the GPIO connected to the powerdown pin,
16 - rotation: as defined in
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/ |
| D | r8a774c0-ek874-mipi-2.1.dts | 1 // SPDX-License-Identifier: GPL-2.0
4 * connected with aistarvision-mipi-v2-adapter board
9 /dts-v1/;
10 #include "r8a774c0-ek874.dts"
12 #include "aistarvision-mipi-adapter-2.1.dtsi"
15 …model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-ada…
16 compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
37 clock-lanes = <0>;
38 data-lanes = <1 2>;
39 remote-endpoint = <&ov5645_ep>;
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| /kernel/linux/linux-5.10/drivers/staging/media/rkisp1/Documentation/devicetree/bindings/media/ |
| D | rockchip-isp1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
18 const: rockchip,rk3399-cif-isp
29 power-domains:
36 phy-names:
41 - description: ISP clock
42 - description: ISP AXI clock clock
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | dp.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright (C) 2013-2019 NVIDIA Corporation
17 caps->enhanced_framing = false; in drm_dp_link_caps_reset()
18 caps->tps3_supported = false; in drm_dp_link_caps_reset()
19 caps->fast_training = false; in drm_dp_link_caps_reset()
20 caps->channel_coding = false; in drm_dp_link_caps_reset()
21 caps->alternate_scrambler_reset = false; in drm_dp_link_caps_reset()
27 dest->enhanced_framing = src->enhanced_framing; in drm_dp_link_caps_copy()
28 dest->tps3_supported = src->tps3_supported; in drm_dp_link_caps_copy()
29 dest->fast_training = src->fast_training; in drm_dp_link_caps_copy()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ti/ |
| D | ti,omap5-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
[all …]
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| D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
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| D | rockchip-pcie-ep.txt | 4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
23 #include "pcie-rockchip.h"
27 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
29 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
33 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
36 "axi-base"); in rockchip_pcie_parse_dt()
37 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); in rockchip_pcie_parse_dt()
38 if (IS_ERR(rockchip->reg_base)) in rockchip_pcie_parse_dt()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
21 For DSIv2, we need an additional clock:
23 For DSI6G v2.0 onwards, we need also need the clock:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ufs/ |
| D | ufshcd-pltfrm.txt | 3 UFSHC nodes are defined to describe on-chip UFS host controllers.
7 - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0"
10 SoC-specific compatible along with "qcom,ufshc" and
12 "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
13 "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
14 "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
15 "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
16 "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
17 - interrupts : <interrupt mapping for UFS host controller IRQ>
18 - reg : <registers mapping>
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/bridge/ |
| D | nwl-dsi.c | 1 // SPDX-License-Identifier: GPL-2.0+
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
106 * hardware bug: the i.MX8MQ needs this clock on during reset
111 /* dsi lanes */
112 u32 lanes; member
136 int ret = dsi->error; in nwl_dsi_clear_error()
138 dsi->error = 0; in nwl_dsi_clear_error()
146 if (dsi->error) in nwl_dsi_write()
149 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
[all …]
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