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Searched +full:dma +full:- +full:protection +full:- +full:control (Results 1 – 25 of 197) sorted by relevance

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/kernel/linux/linux-5.10/include/dt-bindings/dma/
Ddw-dmac.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
7 * Protection Control bits provide protection against illegal transactions.
8 * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
11 #define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */
12 #define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */
/kernel/linux/linux-5.10/Documentation/x86/
Dintel_txt.rst6 Technology (Intel(R) TXT), defines platform-level enhancements that
13 - Provides dynamic root of trust for measurement (DRTM)
14 - Data protection in case of improper shutdown
15 - Measurement and verification of launched environment
18 non-vPro systems. It is currently available on desktop systems
30 - LinuxTAG 2008:
31 http://www.linuxtag.org/2008/en/conf/events/vp-donnerstag.html
33 - TRUST2008:
34 http://www.trust-conference.eu/downloads/Keynote-Speakers/
35 3_David-Grawrock_The-Front-Door-of-Trusted-Computing.pdf
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/kernel/linux/linux-5.10/include/media/drv-intf/
Dsaa7146.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h> /* for delay-stuff */
7 #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
22 #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
23 #define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
67 dma_addr_t dma; member
107 u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
129 u32 revision; /* chip revision; needed for bug-workarounds*/
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/kernel/linux/linux-5.10/Documentation/admin-guide/sysctl/
Dvm.rst13 ------------------------------------------------------------------------------
27 - admin_reserve_kbytes
28 - compact_memory
29 - compaction_proactiveness
30 - compact_unevictable_allowed
31 - dirty_background_bytes
32 - dirty_background_ratio
33 - dirty_bytes
34 - dirty_expire_centisecs
35 - dirty_ratio
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/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
60 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
63 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
66 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
69 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
72 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
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Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
62 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
64 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
66 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
68 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
70 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
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Dm5206sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
48 #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
57 #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
60 #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
70 #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
73 #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
76 #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
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Dm525xsim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
36 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
57 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
60 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
63 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
66 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
69 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
71 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
81 #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
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Dm5272sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5272sim.h -- ColdFire 5272 System Integration Module support.
26 #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
67 #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
75 #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
78 #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
83 #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
85 #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
120 #define MCF_IRQ_DMA 85 /* DMA Controller */
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/kernel/linux/linux-5.10/drivers/net/ethernet/altera/
Daltera_tse.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
126 u32 control; /* PHY device operation control register */ member
130 u32 auto_negotiation_advertisement; /* Auto-negotiation
178 /* The host processor uses this register to control and configure the
182 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
186 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
190 /* 14-bit maximum frame length. The MAC receive logic */
196 /* 12-bit receive FIFO section-empty threshold */
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/kernel/linux/linux-5.10/include/linux/platform_data/
Ddma-dw.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Driver for the Synopsys DesignWare DMA Controller
6 * Copyright (C) 2010-2011 ST Microelectronics
22 * struct dw_dma_slave - Controller-specific information about a slave
24 * @dma_dev: required DMA master device
43 * struct dw_dma_platform_data - Controller configuration parameters
54 * @protctl: Protection control signals setting per channel.
/kernel/linux/linux-5.10/arch/s390/boot/
Dtext_dma.S1 /* SPDX-License-Identifier: GPL-2.0 */
12 .section .dma.text,"ax"
17 * affects a few functions that are not performance-relevant.
33 lhi %r5,-EIO
51 lhi %r2,-1
68 lghi %r5,-EOPNOTSUPP
94 larl %r4,.Lctlregs # Save control registers
96 lg %r2,0(%r4) # Disable lowcore protection
101 larl %r4,.Lfpctl # Floating point control register
123 larl %r4,.Lctlregs # Restore control registers
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/kernel/linux/linux-5.10/drivers/dma/dw/
Dof.c1 // SPDX-License-Identifier: GPL-2.0
3 * Platform driver for the Synopsys DesignWare DMA Controller
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
19 struct dw_dma *dw = ofdma->of_dma_data; in dw_dma_of_xlate()
21 .dma_dev = dw->dma.dev, in dw_dma_of_xlate()
25 if (dma_spec->args_count < 3 || dma_spec->args_count > 4) in dw_dma_of_xlate()
28 slave.src_id = dma_spec->args[0]; in dw_dma_of_xlate()
29 slave.dst_id = dma_spec->args[0]; in dw_dma_of_xlate()
30 slave.m_master = dma_spec->args[1]; in dw_dma_of_xlate()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: "dma-controller.yaml#"
18 const: snps,dma-spear1340
20 "#dma-cells":
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/kernel/linux/linux-5.10/drivers/crypto/ux500/cryp/
Dcryp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST-Ericsson SA 2010
4 * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
5 * Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
6 * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
7 * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
8 * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
82 * struct cryp_config -
96 * struct cryp_protection_config -
100 * Protection configuration structure for setting privilage access
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/kernel/linux/linux-5.10/Documentation/block/
Ddata-integrity.rst16 protocols (SBC Data Integrity Field, SCC protection proposal) as well
17 as SATA/T13 (External Path Protection) try to remedy this by adding
19 metadata (or protection information in SCSI terminology) includes a
22 for some protection schemes also that the I/O is written to the right
29 DIF and the other integrity extensions is that the protection format
42 the protection information to be transferred to and from their
45 The SCSI Data Integrity Field works by appending 8 bytes of protection
54 scatter-gather lists.
57 read. This means that Linux can DMA the data buffers to and from
60 Also, the 16-bit CRC checksum mandated by both the SCSI and SATA specs
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/kernel/linux/linux-5.10/drivers/net/ethernet/cortina/
Dgemini.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
46 /* TOE DMA Queue Size should be 2^n, n = 6...12
47 * TOE DMA Queues are the following queue types:
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
51 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
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/kernel/linux/linux-5.10/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/kernel/linux/linux-5.10/arch/arm/mm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
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/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtl8xxxu/
Drtl8xxxu_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
155 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
157 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
166 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */
172 control */
180 control */
187 control */
220 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
221 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */
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/kernel/linux/linux-5.10/drivers/scsi/mvsas/
Dmv_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
43 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
57 SPI_CTL = 0x10, /* EEPROM control */
78 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
126 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
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/kernel/linux/linux-5.10/include/linux/
Dremoteproc.h47 * struct resource_table - firmware resource table header
81 * struct fw_rsc_hdr - firmware resource entry header
95 * enum fw_resource_type - types of resource entries
99 * @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
126 #define FW_RSC_ADDR_ANY (-1)
129 * struct fw_rsc_carveout - physically contiguous memory request
133 * @flags: iommu protection flags
135 * @name: human-readable name of the requested memory region
159 * even if they do use an iommu. This is needed, e.g., if they control
167 * @flags is used to provide IOMMU protection flags, and @name should
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/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
113 /* Interrupt bit error summary. Don't include I_RU: we refill DMA at other
145 ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
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/kernel/linux/linux-5.10/drivers/acpi/acpica/
Dhwvalid.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: hwvalid - I/O request validation
6 * Copyright (C) 2000 - 2020, Intel Corp.
27 * later (meaning that the BIOS itelf is post-XP.)
33 * DMA: DMA controller
37 * RTC: Real-time clock
39 * DMA1: DMA 1 page registers
40 * DMA1L: DMA 1 Ch 0 low page
41 * DMA2: DMA 2 page registers
42 * DMA2L: DMA 2 low page refresh
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/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/
Ds626.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
56 * Organization (physical order) and size (in DWORDs) of logical DMA buffers
60 * ADC DMA buffer must hold 16 samples,
64 * DAC output DMA buffer holds a single
68 /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */
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