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/kernel/linux/linux-5.10/arch/arm/include/asm/
Ducontext.h26 /* Last for extensibility. Eight byte aligned because some
27 coprocessors require eight byte alignment. */
36 * these should be a multiple of eight bytes and aligned to eight
/kernel/linux/linux-5.10/Documentation/mips/
Dingenic-tcu.rst8 hardware block. It features up to eight channels, that can be used as
12 have eight channels.
35 - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
49 channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
/kernel/linux/linux-5.10/drivers/media/cec/usb/pulse8/
DKconfig3 tristate "Pulse Eight HDMI CEC"
10 This is a cec driver for the Pulse Eight HDMI CEC device.
/kernel/linux/linux-5.10/include/linux/platform_data/
Dmax3421-hcd.h14 * MAX3421E GPIO pins. The chip has eight GP inputs and eight GP outputs.
/kernel/linux/linux-5.10/Documentation/ABI/stable/
Dsysfs-driver-ib_srp10 * id_ext, a 16-digit hexadecimal number specifying the eight
14 * ioc_guid, a 16-digit hexadecimal number specifying the eight
125 Description: Eight-byte identifier extension portion of the 16-byte target
132 Description: Eight-byte I/O controller GUID portion of the 16-byte target
/kernel/linux/linux-5.10/arch/arm64/lib/
Dmemcmp.S60 * Directly compare eight bytes each time.
79 * from last eight bytes of the intended memory range.
180 * Divide the eight bytes into two parts. First,backwards the src2
181 * to an alignment boundary,load eight bytes and compare from
Dstrcmp.S148 * Divide the eight bytes into two parts. First,backwards the src2
149 * to an alignment boundary,load eight bytes from the SRC2 alignment
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsamsung,exynos4210-combiner.txt8 The interrupt combiner controller consists of multiple combiners. Up to eight
10 combined interrupt for its eight interrupt sources. The combined interrupt
Dloongson,htvec.yaml26 description: Eight parent interrupts that receive chained interrupts.
/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/
Dpixfmt-y41p.rst16 In this format each 12 bytes is eight pixels. In the twelve bytes are
17 two CbCr pairs and eight Y's. The first CbCr pair goes with the first
/kernel/linux/linux-5.10/Documentation/hwmon/
Dmax16065.rst57 simultaneously, and the MAX16066 manages up to eight supply voltages.
69 monitors up to eight supply voltages.
/kernel/linux/linux-5.10/Documentation/networking/
Darcnet-hardware.rst125 to other segments of the net. They usually have eight connectors. Active
640 The eight switches in group S2 are used to set the node ID.
649 of eight possible I/O Base addresses using the following table::
669 16K block can be located in any of eight positions.
848 The eight switches in group SW3 are used to set the node ID. Each node
934 from 0 to 15 would be possible, but only the following eight values will
1227 There is another array of eight DIP switches at the top of the
1377 The eight switches in SW2 are used to set the node ID. Each node attached
1420 of eight possible I/O Base addresses using the following table::
1440 located in any of eight positions. The address of the Boot Prom is
[all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/
Dunicode.rst17 both the eight-bit character sets and UTF-8 mode are changed to use
20 This changes the semantics of the eight-bit character tables subtly.
165 U+F8F8 KLINGON DIGIT EIGHT
/kernel/linux/linux-5.10/Documentation/admin-guide/media/
Dpulse8-cec.rst3 Pulse-Eight CEC Adapter driver
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Ddigicolor-wdt.txt4 "Agent Communication" block. This block includes the eight programmable system
/kernel/linux/linux-5.10/arch/arm/mach-footbridge/include/mach/
Disa-dma.h15 * On CATS hardware we have an additional eight ISA dma channels
/kernel/linux/linux-5.10/include/crypto/
Dtwofish.h14 * S-boxes composed with the MDS matrix; w contains the eight "whitening"
/kernel/linux/linux-5.10/drivers/rtc/
Drtc-tegra.c21 /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
59 * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
/kernel/linux/linux-5.10/Documentation/w1/masters/
Dds2482.rst25 one (DS2482-100) or eight (DS2482-800) 1-wire busses.
/kernel/linux/linux-5.10/arch/s390/mm/
Dmaccess.c52 * Therefore we have a read-modify-write sequence: the function reads eight
53 * bytes from destination at an eight byte boundary, modifies the bytes
/kernel/linux/linux-5.10/drivers/misc/sgi-xp/
Dxp.h50 * exceeds the absolute MAXIMUM number of channels possible (eight), then one
53 * The absolute maximum number of channels possible is limited to eight for
55 * require sixteen bytes per channel, and eight allows all of this
/kernel/linux/linux-5.10/include/linux/
Darm-smccc.h325 * This is a variadic macro taking one to eight source arguments, and
341 * This is a variadic macro taking one to eight source arguments, and
370 * This is a variadic macro taking one to eight source arguments, and
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/
Dnuvoton,npcm750-adc.yaml13 The NPCM ADC is a 10-bit converter for eight channel inputs.
/kernel/linux/linux-5.10/Documentation/driver-api/nfc/
Dnfc-pn544.rst26 HCI messages consist of an eight bit header and the message body. The
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-mediatek.txt19 - "pwm1-8": the eight per PWM clocks for mt2712

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