| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | simple-card.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
16 $ref: /schemas/types.yaml#/definitions/phandle-array
19 bitclock-master:
20 description: Indicates dai-link bit clock master
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| D | mikroe,mikroe-proto.txt | 1 Mikroe-PROTO audio board
4 - compatible: "mikroe,mikroe-proto"
5 - dai-format: Must be "i2s".
6 - i2s-controller: The phandle of the I2S controller.
7 - audio-codec: The phandle of the WM8731 audio codec.
9 - model: The user-visible name of this sound complex.
10 - bitclock-master: Indicates dai-link bit clock master; for details see simple-card.txt (1).
11 - frame-master: Indicates dai-link frame master; for details see simple-card.txt (1).
13 (1) : There must be the same master for both bit and frame clocks.
17 compatible = "mikroe,mikroe-proto";
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| D | marvell,mmp-sspa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/marvell,mmp-sspa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lubomir Rintel <lkundrak@v3.sk>
14 pattern: "^audio-controller(@.*)?$"
17 const: marvell,mmp-sspa
21 - description: RX block
22 - description: TX block
29 - description: Clock for the Audio block
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| D | fsl-asoc-card.txt | 23 "fsl,imx-audio-ac97"
25 "fsl,imx-audio-cs42888"
27 "fsl,imx-audio-cs427x"
30 "fsl,imx-audio-wm8962"
32 "fsl,imx-audio-sgtl5000"
33 (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
35 "fsl,imx-audio-wm8960"
37 "fsl,imx-audio-mqs"
39 "fsl,imx-audio-wm8524"
41 "fsl,imx-audio-tlv320aic32x4"
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| /kernel/linux/linux-5.10/Documentation/sound/soc/ |
| D | clocking.rst | 9 Master Clock
10 ------------
12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
13 or SYSCLK). This audio master clock can be derived from a number of sources
17 Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
19 power). Other master clocks are fixed at a set frequency (i.e. crystals).
23 ----------
28 The DAI also has a frame clock to signal the start of each audio frame. This
29 clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
32 Bit Clock can be generated as follows:-
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| D | dai.rst | 16 frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
17 frame is 21uS long and is divided into 13 time slots.
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
30 usually varies depending on the sample rate and the master system clock
35 I2S has several different operating modes:-
58 Common PCM operating modes:-
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
64 MSB is transmitted on rising edge of FRAME/SYNC.
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| /kernel/linux/linux-5.10/net/hsr/ |
| D | hsr_forward.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2011-2014 Autronica Fire and Security AS
5 * 2011-2014 Arvid Brodin, arvid.brodin@alten.se
7 * Frame router for HSR and PRP.
24 * --
25 * Or not - resetting the counter and bridging the frame would create a
29 * frame is received from a particular node, we know something is wrong.
45 if (!ether_addr_equal(eth_hdr->h_dest, in is_supervision_frame()
46 hsr->sup_multicast_addr)) in is_supervision_frame()
50 if (!(eth_hdr->h_proto == htons(ETH_P_PRP) || in is_supervision_frame()
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| D | hsr_device.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2011-2014 Autronica Fire and Security AS
5 * 2011-2014 Arvid Brodin, arvid.brodin@alten.se
23 return dev && (dev->flags & IFF_UP); in is_admin_up()
34 if (dev->operstate != transition) { in __hsr_set_operstate()
35 dev->operstate = transition; in __hsr_set_operstate()
43 static void hsr_set_operstate(struct hsr_port *master, bool has_carrier) in hsr_set_operstate() argument
45 if (!is_admin_up(master->dev)) { in hsr_set_operstate()
46 __hsr_set_operstate(master->dev, IF_OPER_DOWN); in hsr_set_operstate()
51 __hsr_set_operstate(master->dev, IF_OPER_UP); in hsr_set_operstate()
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| /kernel/linux/linux-5.10/include/linux/dma/ |
| D | xilinx_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 #include <linux/dma-mapping.h>
15 * struct xilinx_vdma_config - VDMA Configuration structure
16 * @frm_dly: Frame delay
17 * @gen_lock: Whether in gen-lock mode
18 * @master: Master that it syncs to
19 * @frm_cnt_en: Enable frame count enable
21 * @park_frm: Frame to park on
25 * @ext_fsync: External Frame Sync source
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| /kernel/linux/linux-5.10/sound/soc/ti/ |
| D | davinci-i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
31 #include "edma-pcm.h"
32 #include "davinci-i2s.h"
34 #define DRV_NAME "davinci-i2s"
39 * - This driver supports the "Audio Serial Port" (ASP),
42 * - But it labels it a "Multi-channel Buffered Serial Port"
44 * backward-compatible, possibly explaining that confusion.
46 * - OMAP chips have a controller called McBSP, which is
49 * - Newer DaVinci chips have a controller called McASP,
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| /kernel/linux/linux-5.10/drivers/media/v4l2-core/ |
| D | v4l2-ctrls.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #define pr_fmt(fmt) "v4l2-ctrls: " fmt
15 #include <media/v4l2-ctrls.h>
16 #include <media/v4l2-dev.h>
17 #include <media/v4l2-device.h>
18 #include <media/v4l2-event.h>
19 #include <media/v4l2-fwnode.h>
20 #include <media/v4l2-ioctl.h>
23 if (!WARN_ON(!(vdev)) && ((vdev)->dev_debug & V4L2_DEV_DEBUG_CTRL)) \
28 #define has_op(master, op) \ argument
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | pxa300-raumfeld-connector.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
6 #include "pxa300-raumfeld-tuneable-clock.dtsi"
10 compatible = "raumfeld,raumfeld-connector-pxa303", "marvell,pxa300";
13 compatible = "simple-audio-card";
14 simple-audio-card,name = "Raumfeld Connector";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 simple-audio-card,dai-link@0 {
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1012a-oxalis.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include "fsl-ls1012a.dtsi"
15 compatible = "ebs-systart,oxalis", "fsl,ls1012a";
17 sys_mclk: clock-mclk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <25000000>;
23 reg_1p8v: regulator-1p8v {
24 compatible = "regulator-fixed";
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| D | fsl-ls1012a-frdm.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
16 sys_mclk: clock-mclk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <25000000>;
22 reg_1p8v: regulator-1p8v {
23 compatible = "regulator-fixed";
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| D | fsl-ls1028a-kontron-sl28-var3-ads2.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0
10 /dts-v1/;
11 #include "fsl-ls1028a-kontron-sl28.dts"
14 model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
15 compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",
18 pwm-fan {
19 compatible = "pwm-fan";
20 cooling-min-state = <0>;
21 cooling-max-state = <3>;
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| D | fsl-ls1012a-qds.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "fsl-ls1012a.dtsi"
14 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
16 sys_mclk: clock-mclk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <24576000>;
22 reg_3p3v: regulator-3p3v {
23 compatible = "regulator-fixed";
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| /kernel/linux/linux-5.10/drivers/net/wireless/ti/wl12xx/ |
| D | conf.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
39 * in WLAN / BT master basic rate
41 * Range: 0 - 255 (ms)
50 * Range: 0 - 255 (ms)
57 * in WLAN / BT master EDR
59 * Range: 0 - 255 (ms)
68 * Range: 0 - 255 (ms)
75 * in WLAN PSM / BT master/slave BR
77 * Range: 0 - 255 (ms)
84 * in WLAN PSM / BT master/slave EDR
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| /kernel/linux/linux-5.10/drivers/misc/ |
| D | pti.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * pti.c - PTI driver for cJTAG data extration
27 #include <linux/intel-pti.h>
40 #define MODEM_BASE_ID 71 /* modem master ID address */
41 #define CONTROL_ID 72 /* control master ID address */
42 #define CONSOLE_ID 73 /* console master ID address */
43 #define OS_BASE_ID 74 /* base OS master ID address */
44 #define APP_BASE_ID 80 /* base App master ID address */
45 #define CONTROL_FRAME_LEN 32 /* PTI control frame maximum size */
83 * pti_write_to_aperture()- The private write function to PTI HW.
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| /kernel/linux/linux-5.10/drivers/atm/ |
| D | suni.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * drivers/atm/suni.h - S/UNI PHY driver
6 /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
17 #define SUNI_MRI 0x00 /* Master Reset and Identity / Load
19 #define SUNI_MC 0x01 /* Master Configuration */
20 #define SUNI_MIS 0x02 /* Master Interrupt Status */
22 #define SUNI_MCM 0x04 /* Master Clock Monitor */
23 #define SUNI_MCT 0x05 /* Master Control */
26 /* 0x08-0x0F reserved */
29 #define SUNI_RSOP_SBL 0x12 /* RSOP Section BIP-8 LSB */
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| /kernel/linux/linux-5.10/drivers/net/wan/ |
| D | sbni.c | 8 * Driver supports SBNI12-02,-04,-05,-10,-11 cards, single and
9 * double-channel, PCI and ISA modifications.
18 * - Fixed bug in probe
20 * - Driver was completely redesigned by Denis I.Timofeev,
21 * - now PCI/Dual, ISA/Dual (with single interrupt line) models are
22 * - supported
24 * - PCI cards support
26 * - Completely rebuilt all the packet storage system
27 * - to work in Ethernet-like style.
32 * - added pre-calculation for CRC, fixed bug with "len-2" frames,
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| D | dlci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DLCI Implementation of Frame Relay protocol for Linux, according to
21 * sent back to Linux for re-transmission
108 dev->stats.rx_errors++; in dlci_receive()
113 hdr = (struct frhdr *) skb->data; in dlci_receive()
116 skb->dev = dev; in dlci_receive()
118 if (hdr->control != FRAD_I_UI) in dlci_receive()
121 hdr->control); in dlci_receive()
122 dev->stats.rx_errors++; in dlci_receive()
125 switch (hdr->IP_NLPID) in dlci_receive()
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| /kernel/linux/linux-5.10/include/linux/soundwire/ |
| D | sdw.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
25 /* SDW Master Device Number, not supported yet */
29 /* frame shape defines */
71 * enum sdw_slave_status - Slave status
89 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
90 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
100 * enum sdw_command_response - Command response as defined by SDW spec
180 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
191 * enum sdw_dpn_type - Data port types
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/ |
| D | r8a77951-salvator-x.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
8 /dts-v1/;
10 #include "salvator-x.dtsi"
13 model = "Renesas Salvator-X board based on r8a77951";
14 compatible = "renesas,salvator-x", "renesas,r8a7795";
47 clock-names = "du.0", "du.1", "du.2", "du.3",
62 remote-endpoint = <&hdmi0_con>;
68 remote-endpoint = <&rsnd_endpoint1>;
75 remote-endpoint = <&rcar_dw_hdmi0_out>;
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| D | r8a77950-salvator-x.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x
8 /dts-v1/;
10 #include "salvator-x.dtsi"
13 model = "Renesas Salvator-X board based on r8a77950";
14 compatible = "renesas,salvator-x", "renesas,r8a7795";
47 clock-names = "du.0", "du.1", "du.2", "du.3",
62 remote-endpoint = <&hdmi0_con>;
68 remote-endpoint = <&rsnd_endpoint1>;
75 remote-endpoint = <&rcar_dw_hdmi0_out>;
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| /kernel/linux/linux-5.10/include/sound/ |
| D | soc-dai.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * linux/sound/soc-dai.h -- ALSA SoC Layer
5 * Copyright: 2005-2008 Wolfson Microelectronics. PLC.
43 * sending or receiving PCM data in a frame. This can be used to save power.
55 * - "normal" polarity means signal is available at rising edge of BCLK
56 * - "inverted" polarity means signal is available at falling edge of BCLK
58 * FSYNC "normal" polarity depends on the frame format:
59 * - I2S: frame consists of left then right channel data. Left channel starts
61 * - Left/Right Justified: frame consists of left then right channel data.
64 * - DSP A/B: Frame starts with rising FSYNC edge.
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