| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
| D | qcom,pdc-global.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/qcom,pdc-global.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PDC Global
10 - Sibi Sankar <sibis@codeaurora.org>
13 The bindings describes the reset-controller found on PDC-Global (Power Domain
19 - description: on SC7180 SoCs the following compatibles must be specified
21 - const: "qcom,sc7180-pdc-global"
22 - const: "qcom,sdm845-pdc-global"
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| D | intel,rcu-gw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Reset Controller on Intel Gateway SoCs
10 - Dilip Kota <eswara.kota@linux.intel.com>
15 - intel,rcu-lgm
16 - intel,rcu-xrx200
19 description: Reset controller registers.
22 intel,global-reset:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/fsl/ |
| D | guts.txt | 1 * Global Utilities Block
3 The global utilities block controls power management, I/O device
4 enabling, power-on-reset configuration monitoring, general-purpose
10 - compatible : Should define the compatible device type for
11 global-utilities.
13 "fsl,qoriq-device-config-1.0"
14 "fsl,qoriq-device-config-2.0"
15 "fsl,<chip>-device-config"
16 "fsl,<chip>-guts"
17 - reg : Offset and length of the register set for the device.
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | selftest_hangcheck.c | 62 h->gt = gt; in hang_init()
64 h->ctx = kernel_context(gt->i915); in hang_init()
65 if (IS_ERR(h->ctx)) in hang_init()
66 return PTR_ERR(h->ctx); in hang_init()
68 GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx)); in hang_init()
70 h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
71 if (IS_ERR(h->hws)) { in hang_init()
72 err = PTR_ERR(h->hws); in hang_init()
76 h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
77 if (IS_ERR(h->obj)) { in hang_init()
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| D | intel_reset_types.h | 1 /* SPDX-License-Identifier: MIT */
15 * flags: Control various stages of the GPU reset
17 * #I915_RESET_BACKOFF - When we start a global reset, we need to
19 * any global resources that may be clobber by the reset (such as
22 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
23 * acquire the struct_mutex to reset an engine, we need an explicit
24 * flag to prevent two concurrent reset attempts in the same engine.
28 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
31 * aborted (with -EIO reported to userspace) if set.
33 * #I915_WEDGED_ON_INIT - If we fail to initialize the GPU we can no
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| /kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/ |
| D | hw_atl_llh.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
19 /* set temperature sense reset */
37 /* global */
39 /* set global microprocessor semaphore */
43 /* get global microprocessor semaphore */
46 /* set global register reset disable */
49 /* set soft reset */
52 /* get soft reset */
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| /kernel/linux/linux-5.10/Documentation/ABI/stable/ |
| D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
6 Read/Write PMU global general storage register value,
8 Global general storage register that can be used
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
32 Read/Write PMU persistent global general storage register
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-stih407-usb.txt | 7 - compatible : should be "st,stih407-usb2-phy"
8 - st,syscfg : phandle of sysconfig bank plus integer array containing phyparam and phyctrl registe…
9 - resets : list of phandle and reset specifier pairs. There should be two entries, one
11 - reset-names : list of reset signal names. Should be "global" and "port"
12 See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
13 See: Documentation/devicetree/bindings/reset/reset.txt
18 compatible = "st,stih407-usb2-phy";
19 #phy-cells = <0>;
23 reset-names = "global", "port";
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
85 tristate "APQ8084 Global Clock Controller"
88 Support for the global clock controller on apq8084 devices.
121 tristate "IPQ4019 Global Clock Controller"
123 Support for the global clock controller on ipq4019 devices.
128 tristate "IPQ6018 Global Clock Controller"
130 Support for global clock controller on ipq6018 devices.
136 tristate "IPQ806x Global Clock Controller"
138 Support for the global clock controller on ipq806x devices.
151 tristate "IPQ8074 Global Clock Controller"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc-ipq8074.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-ipq8074.h
22 const: qcom,gcc-ipq8074
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| D | qcom,gcc-qcs404.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Bindingfor QCS404
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-qcs404.h
22 const: qcom,gcc-qcs404
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| D | qcom,gcc-msm8996.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-msm8996.h
22 const: qcom,gcc-msm8996
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| D | qcom,gcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-apq8084.h
19 - dt-bindings/reset/qcom,gcc-apq8084.h
20 - dt-bindings/clock/qcom,gcc-ipq4019.h
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| D | qcom,gcc-sc7180.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SC7180
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-sc7180.h
22 const: qcom,gcc-sc7180
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| D | qcom,gcc-sm8250.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8250
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-sm8250.h
22 const: qcom,gcc-sm8250
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| D | qcom,gcc-sm8150.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8150
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-sm8150.h
22 const: qcom,gcc-sm8150
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| D | qcom,gcc-apq8064.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-msm8960.h
19 - dt-bindings/reset/qcom,gcc-msm8960.h
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| D | qcom,gcc-msm8998.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for MSM8998
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
14 Qualcomm global clock control module which supports the clocks, resets and
18 - dt-bindings/clock/qcom,gcc-msm8998.h
22 const: qcom,gcc-msm8998
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| /kernel/linux/linux-5.10/drivers/phy/st/ |
| D | phy-stih407-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/reset.h>
44 reset_control_deassert(phy_dev->rstc); in stih407_usb2_pico_ctrl()
46 return regmap_update_bits(phy_dev->regmap, phy_dev->ctrl, in stih407_usb2_pico_ctrl()
58 ret = regmap_update_bits(phy_dev->regmap, in stih407_usb2_init_port()
59 phy_dev->param, in stih407_usb2_init_port()
65 return reset_control_deassert(phy_dev->rstport); in stih407_usb2_init_port()
73 * Only port reset is asserted, phy global reset is kept untouched in stih407_usb2_exit_port()
74 * as other ports may still be active. When all ports are in reset in stih407_usb2_exit_port()
77 * reset (like here) or global reset should be equivalent. in stih407_usb2_exit_port()
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| /kernel/linux/linux-5.10/arch/c6x/kernel/ |
| D | vectors.S | 1 ; SPDX-License-Identifier: GPL-2.0-only
9 ; At RESET the processor sets up the DRAM timing parameters and
18 .global \name
21 STW .D2T1 A0,*B15--[2]
44 .global RESET symbol
45 .hidden RESET
46 RESET: label
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| /kernel/linux/linux-5.10/arch/x86/include/uapi/asm/ |
| D | debugreg.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
7 debug registers. Registers 0-3 contain the addresses we wish to trap on */
27 #define DR_STEP (0x4000) /* single-step */
32 bits - each field corresponds to one of the four debug registers,
50 that the processor will reset the bit after a task switch and the other
51 is global meaning that we have to explicitly reset the bit. With linux,
56 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
58 #define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */
62 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
75 #define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | stih418.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
11 #address-cells = <1>;
12 #size-cells = <0>;
15 compatible = "arm,cortex-a9";
17 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
18 cpu-release-addr = <0x94100A4>;
22 compatible = "arm,cortex-a9";
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| /kernel/linux/linux-5.10/arch/xtensa/boot/boot-elf/ |
| D | bootstrap.S | 2 * arch/xtensa/boot/boot-elf/bootstrap.S
4 * Low-level exception handling
10 * Copyright (C) 2004 - 2013 by Tensilica Inc.
23 .global _ResetVector
24 .global reset symbol
29 .begin no-absolute-literals
59 rsil a0, XCHAL_DEBUGLEVEL-1
61 reset: label
77 .end no-absolute-literals
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| /kernel/linux/linux-5.10/sound/mips/ |
| D | hal2.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
18 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
19 #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
40 /* 9=Global DMA Control */
53 /* If IAR_TYPE_M=Global DMA Control: */
99 #define H2I_DMA_END 0x9108 /* global dma endian select */
107 #define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
120 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
136 #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
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| /kernel/linux/linux-5.10/drivers/usb/dwc2/ |
| D | core.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
48 #include <linux/dma-mapping.h>
61 * dwc2_backup_global_registers() - Backup global controller registers.
71 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_global_registers()
73 /* Backup global regs */ in dwc2_backup_global_registers()
74 gr = &hsotg->gr_backup; in dwc2_backup_global_registers()
76 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); in dwc2_backup_global_registers()
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