Searched full:input_reg (Results 1 – 25 of 35) sorted by relevance
12
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx8mm-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
|
| D | fsl,imx8mn-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
|
| D | fsl,imx8mp-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
|
| D | fsl,imx8mq-pinctrl.yaml | 35 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
48 "input_reg" indicates the offset of select input register.
|
| D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| D | fsl,imx6ul-pinctrl.txt | 10 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| D | fsl,imx6sll-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| D | fsl,imx7ulp-pinctrl.txt | 17 <mux_conf_reg input_reg mux_mode input_val> are specified
|
| D | fsl,imx7d-pinctrl.txt | 32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| D | fsl,imx-pinctrl.txt | 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| /kernel/linux/linux-5.10/drivers/pinctrl/freescale/ |
| D | pinctrl-imx.c | 215 * The input_reg[i] here is actually some IOMUXC general in imx_pmx_set_one_pin_mmio()
218 val = readl(ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
221 writel(val, ipctl->base + pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
222 } else if (pin_mmio->input_reg) { in imx_pmx_set_one_pin_mmio()
229 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
232 pin_mmio->input_reg); in imx_pmx_set_one_pin_mmio()
235 pin_mmio->input_reg, pin_mmio->input_val); in imx_pmx_set_one_pin_mmio()
505 * <mux_reg conf_reg input_reg mux_mode input_val>
507 * <mux_conf_reg input_reg mux_mode input_val>
545 pin_mmio->input_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
|
| D | pinctrl-imx.h | 25 * @input_reg: the select input register offset for this pin if any
32 u16 input_reg; member
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6ull-pinfunc-snvs.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
|
| D | imx6ull-pinfunc.h | 12 * <mux_reg conf_reg input_reg mux_mode input_val>
|
| D | imx7ulp-pinfunc.h | 12 * <mux_conf_reg input_reg mux_mode input_val>
|
| D | imx25-pinfunc.h | 13 * <mux_reg conf_reg input_reg mux_mode input_val>
|
| D | vf610-pinfunc.h | 11 * <mux_reg input_reg mux_mode input_val>
|
| D | imx51-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
|
| D | imx6ul-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
|
| /kernel/linux/linux-5.10/drivers/pinctrl/mvebu/ |
| D | pinctrl-armada-37xx.c | 1070 u32 mask, *irq_pol, input_reg, virq, type, level; in armada_3700_pinctrl_resume() local
1075 input_reg = INPUT_VAL; in armada_3700_pinctrl_resume()
1079 input_reg = INPUT_VAL + sizeof(u32); in armada_3700_pinctrl_resume()
1095 regmap_read(info->regmap, input_reg, &level); in armada_3700_pinctrl_resume()
|
| /kernel/linux/linux-5.10/drivers/input/touchscreen/ |
| D | iqs5xx.c | 961 bool input_reg = !iqs5xx->input; in fw_file_store() local
985 if (input_reg) { in fw_file_store()
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8mq-pinfunc.h | 12 * <mux_reg conf_reg input_reg mux_mode input_val>
|
| D | imx8mn-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
|
| D | imx8mm-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
|
| D | imx8mp-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
|
12