| /arkcompiler/runtime_core/compiler/docs/ |
| D | ir_builder.md | 10 form, without dead phi instructions, but it has various drawbacks, such as significant overhead, si…
18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
21 IR ConstInst instructions.
39 3. Fixing the type uncertainties of the instructions.
43 1. Iterate over all bytecode instructions and make basic block for all target instructions, i.e. in…
51 2. If basic block is a loop header, create SafePoint and OsrSaveState instructions.
52 3. Create phi instructions for the live registers.
55 - create auxiliary instructions (SaveState, NullCheck, etc) if needed
63 **Fixing the type uncertainties of the instructions**
66 1. Split constants: for all constants that are used in instructions with different types, split con…
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| D | vn_doc.md | 5 …umbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so the i…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
10 Reducing the number of instructions.
18 All instructions have field `vn_`.
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
21 Based on the collected information, we are looking for a equivalent instructions in the hash map.
23 1. If equivalent instructions were found:
25 …b. If all equivalent instructions do not dominate current instruction, we insert the instruction i…
26 2. If equivalent instructions weren't found, we set next `vn` to the current instruction field and …
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| D | scheduler_doc.md | 4 Rearrange adjacent instructions for better performance.
8 …instructions are executed on CPU they may stall the processor pipeline when input registers are no…
21 * It rearranges instructions only inside the basic block, but not between them
26 For each basic block we first scan instructions in reverse order marking barriers and calculating t…
27 Together with dependencies we calculate priority as a longest (critical) path to leaf instructions …
30 …. In initialization, `ready` is empty and `waiting` contains all leaf instructions (without incomi…
34 Next, we move all already available instructions (`ASAP` <= `cycle`) from `waiting` queue into `rea…
36 …t `ASAP` value for all dependent instructions and add some of them (which depend only on already s…
62 // Rearranges instructions in the basic block using list scheduling algorithm.
128 ... // Here we rearrange instructions in basic block according to sched_
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| D | memory_barriers_doc.md | 5 We need to encode barriers after the instructions NewArray, NewObject, NewMultiArray so that if the…
11 Reducing the number of instructions and speed up execution.
19 There is instruction flag `MEM_BARRIER`. The flag is set to `true` for the instructions NewObject, …
21 We pass through all instructions in PRO order. If the instruction has flag `MEM_BARRIER` we add the…
29 Codegen checks the flag `MEM_BARRIER` for the instructions NewObject, NewArray and NewMultiArray an…
93 Instructions `2.ref NewArray`, `5.ref NewObject` and `10.ref NewObject` have flag `MEM_BARRIER` …
94 `7.void CallStatic` don't have the instructions `2.ref NewArray`, `5.ref NewObject` as inputs.
95 So the pass `OptimizeMemoryBarriers` will remove the flag from these instructions and skip in `10.r…
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| D | code_sink_doc.md | 4 The optimization moves instructions into successor blocks, when possible, so that they are not exec…
39 …nstruction is dominated by a block that the instruction is sunk into. Instructions in a basic bloc…
41 Instructions that cannot sink:
43 * Instructions allocating memory
44 * Control flow instructions
45 * Instructions that can throw an exception
46 * Barrier instructions (calls, monitors, volatile, SafePoints, etc.)
47 * Store instructions
48 * Load instructions if they dominate in scope of current basic block:
53 To determine which load instruction can be sunk we keep a list of store instructions that have been…
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| D | if_conversion_doc.md | 4 …ies to remove branches in executable code by creating linear sections with predicate instructions.
8 …instructions after the branch speculatively before executing the branch itself. If the prediction …
58 5. The number of instructions in `JBB`(and `JBB 2` for Diamond) less than the limit(set by the opti…
65 1. `If` instructions removed from `BB`(the necessary information, such as the CC, is saved)
68 4. Select instructions are constructed at the end of `BB`(`JBB 2` for Diamond)
69 5. All Phi instructions in `PBB` are edited:
71 …b. If `PBB` doesn't have other predecessors, all Phi inputs are copied to Select instructions and …
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| /arkcompiler/runtime_core/isa/ |
| D | asserts.rb | 33 assert('Unique opcodes') { Panda.instructions.map(&:opcode).uniq? }
36 Panda.instructions.reject(&:prefix).size + Panda.prefixes.size <= 256
40 Panda.instructions.reject(&:prefix).sorted_by?(&:opcode_idx)
47 assert('All instructions for a prefix should fit one byte') do
49 … Panda.instructions.select { |insn| insn.prefix && (insn.prefix.name == prefix.name) }.size <= 256
54 Panda.instructions.map do |insn|
60 Panda.instructions.map do |insn|
85 uses = Panda.instructions.flat_map(&type.to_proc).uniq
93 uses = Panda.instructions.flat_map(&type.to_proc).uniq
99 assert('Format operands are parseable') { Panda.instructions.each(&:operands) }
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| D | combine.rb | 22 data['groups'].flat_map { |g| g['instructions'] }
45 # check that all instructions are prefixed:
46 instructions = data_instructions(plugin_data)
47 …raise 'Plugged in instructions must be prefixed' unless instructions.reject { |i| i['prefix'] }.em…
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| /arkcompiler/runtime_core/compiler/tests/ |
| D | iterators_test.cpp | 92 // Check InstForwardValidIterator with erasing instructions in Check()
120 // Check InstBackwardValidIterator with erasing instructions in Check()
154 void InitExpectData(std::vector<Inst *> &instructions) in InitExpectData() argument
160 for (auto inst : instructions) { in InitExpectData()
171 void PopulateBlock(BasicBlock *block, std::vector<Inst *> &instructions) in PopulateBlock() argument
173 for (auto inst : instructions) { in PopulateBlock()
197 std::vector<Inst *> instructions; in TEST_F() local
198 Check(instructions); in TEST_F()
210 std::vector<Inst *> instructions(IteratorsTest::INST_COUNT); in TEST_F() local
211 for (auto &inst : instructions) { in TEST_F()
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| /arkcompiler/runtime_core/docs/ |
| D | ir_format.md | 5 * Support all the features and instructions of Panda bytecode
7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
70 * Common properties will be introduced for the instructions, making it easier to add new instructio…
78 Panda bytecode has more than 200 instructions. We need to convert all Bytecode instructions in IR i…
79 The specifics and properties of instructions should be taken into account in optimizations and code…
83 …zations. For this, need to support ARMv8-M Instruction Set(only those instructions that are needed)
87 IR contains high- and low-level instructions with a single interface.
89 At the second step, the instructions will be split on several low level instructions(close to assem…
94 Typically, an overhead is considered to be the average number of 'native' instructions(ARM) that ar…
100 The goal is overhead about 100000 native instructions per guest (standard for JIT compilers)
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| D | irtoc.md | 13 …ove the `IrConstructor`. It reads compiler's `instructions.yaml` file to get information about ins…
15 Each opcode in the IR instructions has corresponding token in the irtoc lang. For example, IR instr…
33 ### Pseudo instructions
34 Pseudo instructions are not a real IR instructions in terms of compiler, those instructions are nee…
37 Pseudo instructions are described like regular instructions in the `instructions.yaml` file, but in…
41 …e `var` holds the newly created instruction `Add` and it can be input for the further instructions.
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| /arkcompiler/runtime_core/irtoc/lang/ |
| D | basic_block.rb | 19 attr_reader :index, :function, :preds, :instructions accessor in BasicBlock
23 @instructions = []
33 @instructions[-1]
37 @instructions.empty?
41 !empty? && @instructions[-1].terminator?
46 @instructions.prepend(inst)
48 @instructions << inst
81 @instructions.each(&:emit_ir)
86 @instructions.each(&:generate_builder)
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| D | instructions_data.rb | 19 @@instructions = {}
25 yaml_data['instructions'].each do |inst|
27 @@instructions[inst["opcode"].to_sym] = inst
31 @@instructions[inst["opcode"].to_sym] = inst
39 def self.instructions; @@instructions; end singletonMethod in InstructionsData
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| /arkcompiler/runtime_core/verification/absint/tests/ |
| D | exec_context_test.cpp | 60 uint8_t instructions[128]; in TEST_F() local
62 ExecContext exec_ctx {&instructions[0], &instructions[127]}; in TEST_F()
64 std::array<const uint8_t *, 6> cp = {&instructions[8], &instructions[17], &instructions[23], in TEST_F()
65 &instructions[49], &instructions[73], &instructions[103]}; in TEST_F()
96 const uint8_t *ep = &instructions[0]; in TEST_F()
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| /arkcompiler/runtime_core/compiler/optimizer/templates/ |
| D | generate_ecma.inl.erb | 26 % instructions = Panda::instructions.select{|b| b.namespace == "ecmascript"}
27 % if instructions.first && instructions.first.intrinsic_name
28 % instructions = instructions.group_by(&:intrinsic_name)
30 % instructions = instructions.group_by(&:opcode)
32 % instructions.each do |intrinsic_name, group|
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| /arkcompiler/runtime_core/tests/cts-generator/cts-template/ |
| D | monitor.yaml | 70 title: Monitor instructions
72 Monitor instructions are used to synchronize object access between threads. Each object
75 …These instructions take object reference in accumulator as input. If accumulator contains null then
91 instructions:
128 instructions:
166 instructions:
198 instructions:
238 instructions:
271 … - description: Check that a thread owns a monitor after several executed monitorexit instructions
288 …Check that a thread owns a monitor if amount of executed monitorexit instructions is less than amo…
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| D | f32toi64.yaml | 26 instructions:
66 instructions:
113 instructions:
136 instructions:
159 instructions:
175 instructions:
191 instructions:
214 instructions:
266 instructions:
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| D | f64tou32.yaml | 26 instructions:
60 instructions:
107 instructions:
130 instructions:
153 instructions:
169 instructions:
185 instructions:
209 instructions:
262 instructions:
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| D | f64tou64.yaml | 26 instructions:
69 instructions:
110 instructions:
136 instructions:
162 instructions:
178 instructions:
194 instructions:
217 instructions:
270 instructions:
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| D | f32tou32.yaml | 26 instructions:
60 instructions:
95 instructions:
118 instructions:
141 instructions:
157 instructions:
173 instructions:
197 instructions:
249 instructions:
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| D | f32tou64.yaml | 26 instructions:
69 instructions:
107 instructions:
133 instructions:
159 instructions:
175 instructions:
191 instructions:
214 instructions:
266 instructions:
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| D | f32toi32.yaml | 26 instructions:
64 instructions:
116 instructions:
144 instructions:
175 instructions:
196 instructions:
217 instructions:
245 instructions:
297 instructions:
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| D | f64toi32.yaml | 26 instructions:
64 instructions:
123 instructions:
151 instructions:
182 instructions:
203 instructions:
224 instructions:
252 instructions:
305 instructions:
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| D | f64toi64.yaml | 26 instructions:
67 instructions:
120 instructions:
146 instructions:
172 instructions:
188 instructions:
204 instructions:
227 instructions:
280 instructions:
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| /arkcompiler/runtime_core/tests/cts-coverage-tool/config/ |
| D | non_testable.yaml | 42 instructions:
55 instructions:
68 instructions:
81 instructions:
99 instructions:
114 Non-range instructions can be used to pass up to 4 arguments (unused register slot values will
122 instructions:
|