| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-s3c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
37 #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
38 #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
39 #define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
40 #define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
50 #define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
51 #define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/ |
| D | divider.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped adjustable clock rate divider that does not gate and has
17 ti,index-starts-at-one - valid divisor values start at 1, not the default
24 ti,index-power-of-two - valid divisor values are powers of two. E.g:
41 Any zero value in this array means the corresponding bit-value is invalid
45 unless the divider array is provided, min and max dividers. Optionally
52 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57 - #clock-cells : from common clock binding; shall be set to 0.
58 - clocks : link to phandle of parent clock
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| /kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/fw/api/ |
| D | rs.h | 8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
10 * Copyright(c) 2018 - 2020 Intel Corporation
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2018 - 2020 Intel Corporation
68 * enum iwl_tlc_mng_cfg_flags_enum - options for TLC config flags
82 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
83 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1),
84 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
85 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3),
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| D | location.h | 8 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
9 * Copyright (C) 2018 - 2020 Intel Corporation
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
30 * Copyright (C) 2018 - 2020 Intel Corporation
64 * enum iwl_location_subcmd_ids - location group command IDs
128 * struct iwl_tof_config_cmd - ToF configuration
130 * @one_sided_disabled: indicates if one-sided is disabled (or not)
142 * enum iwl_tof_bandwidth - values for iwl_tof_range_req_ap_entry.bandwidth
143 * @IWL_TOF_BW_20_LEGACY: 20 MHz non-HT
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| /kernel/linux/linux-5.10/drivers/clk/mvebu/ |
| D | dove-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
32 DIV_CTRL1_N_RESET_MASK = BIT(10),
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/modules/freesync/ |
| D | freesync.c | 36 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
40 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
44 /*Threshold to exit fixed refresh rate*/
69 core_freesync->dc = dc; in mod_freesync_create()
70 return &core_freesync->public; in mod_freesync_create()
115 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
116 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
133 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), in calc_v_total_from_refresh()
134 stream->timing.h_total), 1000000); in calc_v_total_from_refresh()
137 if (v_total < stream->timing.v_total) { in calc_v_total_from_refresh()
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| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu_mp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
13 static void ccu_mp_find_best(unsigned long parent, unsigned long rate, in ccu_mp_find_best() argument
25 if (tmp_rate > rate) in ccu_mp_find_best()
28 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_mp_find_best()
42 unsigned long rate, in ccu_mp_find_best_with_parent_adj() argument
56 * unsigned long in rate * m * p below in ccu_mp_find_best_with_parent_adj()
59 maxdiv = min(ULONG_MAX / rate, maxdiv); in ccu_mp_find_best_with_parent_adj()
68 if (rate * div == parent_rate_saved) { in ccu_mp_find_best_with_parent_adj()
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| /kernel/linux/linux-5.10/drivers/net/wireless/intersil/hostap/ |
| D | hostap_ap.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define WLAN_STA_AUTH BIT(0)
14 #define WLAN_STA_ASSOC BIT(1)
15 #define WLAN_STA_PS BIT(2)
16 #define WLAN_STA_TIM BIT(3) /* TIM bit is on for PS stations */
17 #define WLAN_STA_PERM BIT(4) /* permanent; do not remove entry on expiration */
18 #define WLAN_STA_AUTHORIZED BIT(5) /* If 802.1X is used, this flag is
20 * send and receive non-IEEE 802.1X frames
22 #define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
24 #define WLAN_RATE_1M BIT(0)
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| /kernel/linux/linux-5.10/drivers/clk/ti/ |
| D | divider.c | 6 * Tero Kristo <t-kristo@ti.com>
18 #include <linux/clk-provider.h>
34 for (clkt = table; clkt->div; clkt++) in _get_table_div()
35 if (clkt->val == val) in _get_table_div()
36 return clkt->div; in _get_table_div()
46 if (divider->table) { in _setup_mask()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
50 if (clkt->val > max_val) in _setup_mask()
51 max_val = clkt->val; in _setup_mask()
53 max_val = divider->max; in _setup_mask()
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-sscg-pll.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
33 #define PLL_LOCK_MASK BIT(31)
34 #define PLL_PD_MASK BIT(7)
65 #define SSCG_PLL_BYPASS1_MASK BIT(5)
66 #define SSCG_PLL_BYPASS2_MASK BIT(4)
102 val = readl_relaxed(pll->base + PLL_CFG0); in clk_sscg_pll_wait_lock()
106 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, in clk_sscg_pll_wait_lock()
115 int new_diff = temp_setup->fout - temp_setup->fout_request; in clk_sscg_pll2_check_match()
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| /kernel/linux/linux-5.10/drivers/pwm/ |
| D | pwm-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
76 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
77 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
78 #define EMC_CLKCHANGE_SR_ENABLE BIT(2)
80 #define EMC_TIMING_UPDATE BIT(0)
82 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
83 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
85 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
86 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
87 #define EMC_DBG_FORCE_UPDATE BIT(2)
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | rza_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0
23 #define WTSCR_WT BIT(6)
24 #define WTSCR_TME BIT(5)
32 #define WRCSR_RSTE BIT(6)
52 unsigned long rate = clk_get_rate(priv->clk); in rza_wdt_calc_timeout() local
55 if (priv->cks == CKS_4BIT) { in rza_wdt_calc_timeout()
56 ticks = DIV_ROUND_UP(timeout * rate, DIVIDER_4BIT); in rza_wdt_calc_timeout()
63 priv->count = 256 - ticks; in rza_wdt_calc_timeout()
67 priv->count = 0; in rza_wdt_calc_timeout()
71 timeout, priv->count); in rza_wdt_calc_timeout()
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| /kernel/linux/linux-5.10/drivers/net/wireless/intersil/prism54/ |
| D | isl_oid.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
45 u32 addr; /* 32bit bus address */
153 DOT11_MAXFRAMEBURST_MAX = 5000, /* Use this as max,
155 * recommended max. I'll update this as I find
156 * out what the real MAX is. Also note that you don't necessarily
162 * Long preamble uses 128-bit sync field, 8-bit CRC
163 * Short preamble uses 56-bit sync field, 16-bit CRC
165 * 802.11a -- not sure, both optionally ?
190 /* All you need to know, ERP is "Extended Rate PHY".
191 * An Extended Rate PHY (ERP) STA or AP shall support three different
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| /kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlegacy/ |
| D | commands.h | 8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
92 /* Multi-Station support */
138 /* RF-KILL commands and notifications */
184 * when sending the response to each driver-originated command, so
188 * There is one exception: uCode sets bit 15 when it originates
196 * 0:7 tfd idx - position within TX queue
199 * 14 huge - driver sets this to indicate command is in the
201 * 15 unsolicited RX or uCode-originated notification
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| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
51 #define SSC_CTL_HB BIT(4)
52 #define SSC_CTL_PH BIT(5)
53 #define SSC_CTL_PO BIT(6)
54 #define SSC_CTL_SR BIT(7)
55 #define SSC_CTL_MS BIT(8)
56 #define SSC_CTL_EN BIT(9)
57 #define SSC_CTL_LPB BIT(10)
58 #define SSC_CTL_EN_TX_FIFO BIT(11)
59 #define SSC_CTL_EN_RX_FIFO BIT(12)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | cs35l36.txt | 5 - compatible : "cirrus,cs35l36"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
18 - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
24 - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value.
32 - cirrus,multi-amp-mode : Boolean to determine if there are more than
33 one amplifier in the system. If more than one it is best to Hi-Z the ASP
36 - cirrus,boost-ctl-select : Boost conerter control source selection.
39 0x00 - Control Port Value
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| D | cs35l35.txt | 5 - compatible : "cirrus,cs35l35"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - interrupts : IRQ line info CS35L35.
14 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - cirrus,boost-ind-nanohenry: Inductor value for boost converter. The value is
21 - reset-gpios : gpio used to reset the amplifier
23 - cirrus,stereo-config : Boolean to determine if there are 2 AMPs for a
26 - cirrus,audio-channel : Set Location of Audio Signal on Serial Port
30 - cirrus,advisory-channel : Set Location of Advisory Signal on Serial Port
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| /kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/ |
| D | dm.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
19 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; in rtl92ee_dm_false_alarm_counter_statistics()
21 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); in rtl92ee_dm_false_alarm_counter_statistics()
22 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); in rtl92ee_dm_false_alarm_counter_statistics()
25 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
26 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); in rtl92ee_dm_false_alarm_counter_statistics()
29 falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
30 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); in rtl92ee_dm_false_alarm_counter_statistics()
33 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
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| /kernel/linux/linux-5.10/drivers/clk/pistachio/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
17 #define PLL_STATUS_LOCK BIT(0)
28 #define PLL_INT_CTRL1_PD BIT(24)
29 #define PLL_INT_CTRL1_DSMPD BIT(25)
30 #define PLL_INT_CTRL1_FOUTPOSTDIVPD BIT(26)
31 #define PLL_INT_CTRL1_FOUTVCOPD BIT(27)
40 #define PLL_INT_CTRL2_BYPASS BIT(28)
43 #define PLL_FRAC_CTRL3_PD BIT(0)
44 #define PLL_FRAC_CTRL3_DACPD BIT(1)
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| /kernel/linux/linux-5.10/Documentation/misc-devices/ |
| D | bh1770glc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - ROHM BH1770GLC
10 - OSRAM SFH7770
19 -----------
25 ALS produces 16 bit lux values. The chip contains interrupt logic to produce
28 Proximity part contains IR-led driver up to 3 IR leds. The chip measures
30 8 bit. Driver supports only one channel. Driver uses ALS results to estimate
49 -----
52 RO - shows detected chip type and version
55 RW - enable / disable chip
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| /kernel/linux/linux-5.10/include/sound/sof/ |
| D | dai-intel.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
40 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0)
42 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1)
44 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2)
46 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3)
48 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4)
50 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5)
52 /* DMIC max. four controllers for eight microphone channels */
55 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
87 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
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| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | ml26124.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 #define DVOL_CTL_DVMUTE_ON BIT(4) /* Digital volume MUTE On */
24 #define ML26124_SAI_NO_DELAY BIT(1)
25 #define ML26124_SAI_FRAME_SYNC (BIT(5) | BIT(0)) /* For mono (Telecodec) */
27 #define ML26124_VMID BIT(1)
36 u32 rate; member
44 u32 rate; member
53 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7150, 50, 0);
55 static const DECLARE_TLV_DB_SCALE(alclvl, -2250, 150, 0);
56 static const DECLARE_TLV_DB_SCALE(mingain, -1200, 600, 0);
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| /kernel/linux/linux-5.10/drivers/net/wireless/ti/wlcore/ |
| D | conf.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 CONF_HW_BIT_RATE_1MBPS = BIT(0),
15 CONF_HW_BIT_RATE_2MBPS = BIT(1),
16 CONF_HW_BIT_RATE_5_5MBPS = BIT(2),
17 CONF_HW_BIT_RATE_6MBPS = BIT(3),
18 CONF_HW_BIT_RATE_9MBPS = BIT(4),
19 CONF_HW_BIT_RATE_11MBPS = BIT(5),
20 CONF_HW_BIT_RATE_12MBPS = BIT(6),
21 CONF_HW_BIT_RATE_18MBPS = BIT(7),
22 CONF_HW_BIT_RATE_22MBPS = BIT(8),
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| /kernel/linux/linux-5.10/Documentation/sound/cards/ |
| D | hdspm.rst | 2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
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