| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/loongson/ |
| D | devices.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
20 - description: Classic Loongson64 Quad Core + LS7A
22 - const: loongson,loongson64c-4core-ls7a
24 - description: Classic Loongson64 Quad Core + RS780E
26 - const: loongson,loongson64c-4core-rs780e
28 - description: Classic Loongson64 Octa Core + RS780E
30 - const: loongson,loongson64c-8core-rs780e
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | actions.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
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| D | fsl.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Li Yang <leoyang.li@nxp.com>
18 - description: i.MX1 based Boards
20 - enum:
21 - armadeus,imx1-apf9328
22 - fsl,imx1ads
23 - const: fsl,imx1
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| D | sunxi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR X11)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
19 - description: Allwinner A100 Perf1 Board
21 - const: allwinner,a100-perf1
22 - const: allwinner,sun50i-a100
24 - description: Allwinner A23 Evaluation Board
26 - const: allwinner,sun8i-a23-evb
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| /kernel/linux/linux-5.10/arch/arm64/crypto/ |
| D | sha512-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
37 * The SHA-512 round constants
42 .quad 0x428a2f98d728ae22, 0x7137449123ef65cd
43 .quad 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
44 .quad 0x3956c25bf348b538, 0x59f111f1b605d019
45 .quad 0x923f82a4af194f9b, 0xab1c5ed5da6d8118
46 .quad 0xd807aa98a3030242, 0x12835b0145706fbe
47 .quad 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
48 .quad 0x72be5d74f27b896f, 0x80deb1fe3b1696b1
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| D | sha3-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
59 ld1 {v25.8b-v28.8b}, [x1], #32
60 ld1 {v29.8b-v31.8b}, [x1], #24
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/marvell/ |
| D | armada-7k-8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR X11)
3 ---
4 $id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gregory CLEMENT <gregory.clement@bootlin.com>
18 - description: Armada 7020 SoC
20 - const: marvell,armada7020
21 - const: marvell,armada-ap806-dual
22 - const: marvell,armada-ap806
24 - description: Armada 7040 SoC
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
105 tristate "Atmel Quad SPI Controller"
109 This enables support for the Quad SPI controller in master mode.
111 supports spi-mem interface.
181 this code to manage the per-word or per-transfer accesses to the
205 tristate "Cadence Quad SPI controller"
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| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | k10temp.rst | 8 Socket F: Quad-Core/Six-Core/Embedded Opteron (but see below)
10 Socket AM2+: Quad-Core Opteron, Phenom (II) X3/X4, Athlon X2 (but see below)
12 Socket AM3: Quad-Core Opteron, Athlon/Phenom II X2/X3/X4, Sempron II
20 * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
22 * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
24 * AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri",
53 BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
69 Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
88 -----------
109 control cooling systems. Tctl is a non-physical temperature on an
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| D | coretemp.rst | 5 * All Intel Core family
11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
19 Intel 64 and IA-32 Architectures Software Developer's Manual
27 -----------
30 inside Intel CPUs. This driver can read both the per-core and per-package
31 temperature using the appropriate sensors. The per-package sensor is new;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | qcom,spi-qcom-qspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
11 - Mukesh Savaliya <msavaliy@codeaurora.org>
12 - Akash Asthana <akashast@codeaurora.org>
15 dual, or quad wire transmission modes for read/write access to slaves such
19 - $ref: /spi/spi-controller.yaml#
24 - const: qcom,sdm845-qspi
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| D | st,stm32-qspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings
10 - Christophe Kerello <christophe.kerello@st.com>
11 - Patrice Chotard <patrice.chotard@st.com>
14 - $ref: "spi-controller.yaml#"
18 const: st,stm32f469-qspi
22 - description: registers
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| D | mediatek,spi-mtk-nor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
21 - $ref: /spi/spi-controller.yaml#
26 - items:
27 - enum:
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| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | marvel.rst | 13 ------------
16 - 88F5082
17 - 88F5181
18 - 88F5181L
19 - 88F5182
21 … - Datasheet: http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
22 …- Programmer's User Guide: http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensour…
23 … - User Manual: http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
24 - 88F5281
26 …- Datasheet: http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sh…
[all …]
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| /kernel/linux/linux-5.10/Documentation/infiniband/ |
| D | opa_vnic.rst | 2 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC)
5 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC) feature
6 supports Ethernet functionality over Omni-Path fabric by encapsulating
11 The patterns of exchanges of Omni-Path encapsulated Ethernet packets
12 involves one or more virtual Ethernet switches overlaid on the Omni-Path
13 fabric topology. A subset of HFI nodes on the Omni-Path fabric are
26 +-------------------+
30 +-------------------+
35 +-----------------------------+ +------------------------------+
37 | +---------+ +---------+ | | +---------+ +---------+ |
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| /kernel/linux/linux-5.10/arch/x86/events/intel/ |
| D | uncore_snb.c | 1 // SPDX-License-Identifier: GPL-2.0
93 #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1)
112 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1)
121 #define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1)
133 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
134 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
137 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
138 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
143 struct hw_perf_event *hwc = &event->hw; in snb_uncore_msr_enable_event()
145 if (hwc->idx < UNCORE_PMC_IDX_FIXED) in snb_uncore_msr_enable_event()
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| /kernel/linux/linux-5.10/include/linux/mtd/ |
| D | spi-nor.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
12 #include <linux/spi/spi-mem.h>
19 * requires a 4-byte (32-bit) address.
33 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
34 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
38 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
39 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
55 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
60 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
61 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
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| /kernel/linux/linux-5.10/arch/arm/mach-rockchip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
23 Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arc/ |
| D | hsdk.txt | 2 ---------------------------------------------------------------------------
4 ARC HSDK Board with quad-core ARC HS38x4 in silicon.
7 - compatible = "snps,hsdk";
|
| /kernel/linux/linux-5.10/Documentation/arm/sti/ |
| D | stih418-overview.rst | 6 ------------
8 The STiH418 is the new generation of SoC for UHDp60 set-top boxes
10 and IP-STB markets.
13 - ARM Cortex-A9 1.5 GHz quad core CPU (28nm)
14 - SATA2, USB 3.0, PCIe, Gbit Ethernet
15 - HEVC L5.1 Main 10
16 - VP9
19 ---------------
|
| /kernel/linux/linux-5.10/Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | imx6q-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx6q-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock bindings for Freescale i.MX6 Quad
10 - Anson Huang <Anson.Huang@nxp.com>
14 const: fsl,imx6q-ccm
24 - description: CCM interrupt request 1
25 - description: CCM interrupt request 2
27 '#clock-cells':
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| /kernel/linux/linux-5.10/arch/arc/plat-axs10x/ |
| D | axs10x.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
12 #include <asm/asm-offsets.h>
34 * --------------------- in axs10x_enable_gpio_intc_wire()
35 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
36 * --------------------- in axs10x_enable_gpio_intc_wire()
38 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
39 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
40 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
44 * ------------------------ in axs10x_enable_gpio_intc_wire()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/firmware/ |
| D | intel,stratix10-svc.txt | 3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
32 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
36 -------
38 reserved-memory {
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx8mq-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
18 const: fsl,imx8mq-iomuxc
37 be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
39 refer to i.MX8M Quad Reference Manual for detailed CONFIG settings.
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