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/kernel/linux/linux-5.10/drivers/video/fbdev/via/
Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
30 return ((pll.divisor - 2) << 16) in k800_encode_pll()
32 | (pll.multiplier - 2); in k800_encode_pll()
44 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
47 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
52 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
56 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap1/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0
3 * OMAP1 reset support
14 /* ARM_SYSST bit shifts related to SoC reset sources */
20 /* Standardized reset source bits (across all OMAP SoCs) */
31 * "Global Software Reset Affects Traffic Controller Frequency". in omap1_restart()
42 * omap1_get_reset_sources - return the source of the SoC's last reset
44 * Returns bits that represent the last reset source for the SoC. The
/kernel/linux/linux-5.10/drivers/reset/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,gcc-msm8996.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-msm8996.h
22 const: qcom,gcc-msm8996
26 - description: XO source
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Dqcom,gcc-sc7180.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SC7180
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-sc7180.h
22 const: qcom,gcc-sc7180
26 - description: Board XO source
[all …]
Dqcom,gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Taniya Das <tdas@codeaurora.org>
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sm8150.h
20 dt-bindings/clock/qcom,gpucc-sm8250.h
25 - qcom,sdm845-gpucc
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Dqcom,sdm845-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SDM845
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,dispcc-sdm845.h.
20 const: qcom,sdm845-dispcc
27 - description: Board XO source
28 - description: GPLL0 source from GCC
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Dqcom,msm8998-gpucc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,gpucc-msm8998.h.
20 const: qcom,msm8998-gpucc
24 - description: Board XO source
25 - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
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Dqcom,gcc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8250
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-sm8250.h
22 const: qcom,gcc-sm8250
26 - description: Board XO source
[all …]
Dqcom,gcc-sm8150.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM8150
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-sm8150.h
22 const: qcom,gcc-sm8150
26 - description: Board XO source
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Dsilabs,si5351.txt8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
20 - reg: i2c device address, shall be 0x60 or 0x61.
21 - #clock-cells: from common clock binding; shall be set to 1.
22 - clocks: from common clock binding; list of parent clock
26 - #address-cells: shall be set to 1.
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Dqcom,sc7180-dispcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller Binding for SC7180
10 - Taniya Das <tdas@codeaurora.org>
16 See also dt-bindings/clock/qcom,dispcc-sc7180.h.
20 const: qcom,sc7180-dispcc
24 - description: Board XO source
25 - description: GPLL0 source from GCC
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Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller Binding
10 - Jeffrey Hugo <jhugo@codeaurora.org>
11 - Taniya Das <tdas@codeaurora.org>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8660
23 - qcom,mmcc-msm8960
[all …]
Dqcom,gcc-msm8998.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for MSM8998
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <tdas@codeaurora.org>
18 - dt-bindings/clock/qcom,gcc-msm8998.h
22 const: qcom,gcc-msm8998
26 - description: Board XO source
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/
Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/
Dgpio-restart.txt4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
[all …]
/kernel/linux/linux-5.10/arch/sparc/include/asm/
Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx4/
Dreset.c8 * COPYING in the main directory of this source tree, or the
11 * Redistribution and use in source and binary forms, with or
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
44 void __iomem *reset; in mlx4_reset() local
65 * Reset the chip. This is somewhat ugly because we have to in mlx4_reset()
66 * save off the PCI header before reset and then restore it in mlx4_reset()
74 err = -ENOMEM; in mlx4_reset()
79 pcie_cap = pci_pcie_cap(dev->persist->pdev); in mlx4_reset()
84 if (pci_read_config_dword(dev->persist->pdev, i * 4, in mlx4_reset()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dopen-pic.txt13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a <u32> and the value shall be 2.
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
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/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dprm2xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2012 Texas Instruments, Inc.
22 #include "prm-regbits-24xx.h"
25 * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
33 * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
35 * reset source ID bit shifts (which is an OMAP SoC-independent
45 { -1, -1 },
49 * omap2xxx_prm_read_reset_sources - return the last SoC reset source
51 * Return a u32 representing the last reset sources of the SoC. The
52 * returned reset source bits are standardized across OMAP SoCs.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/touchscreen/
Dsis_i2c.txt4 - compatible: must be "sis,9200-ts"
5 - reg: i2c slave address
6 - interrupts: touch controller interrupt (see interrupt
10 - pinctrl-names: should be "default" (see pinctrl binding [1]).
11 - pinctrl-0: a phandle pointing to the pin settings for the
13 - attn-gpios: the gpio pin used as attention line
14 - reset-gpios: the gpio pin used to reset the controller
15 - wakeup-source: touchscreen can be used as a wakeup source
17 [0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
18 [1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
[all …]
Delan,elants_i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - David Heidelberg <david@ixit.cz>
13 - $ref: touchscreen.yaml#
18 - elan,ektf3624
19 - elan,ekth3500
27 wakeup-source:
29 description: touchscreen can be used as a wakeup source.
31 reset-gpios:
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dwm8804.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8804.c -- WM8804 S/PDIF transceiver driver
5 * Copyright 2010-11 Wolfson Microelectronics plc
26 #include <sound/soc-dapm.h>
37 { 3, 0x21 }, /* R3 - PLL1 */
38 { 4, 0xFD }, /* R4 - PLL2 */
39 { 5, 0x36 }, /* R5 - PLL3 */
40 { 6, 0x07 }, /* R6 - PLL4 */
41 { 7, 0x16 }, /* R7 - PLL5 */
42 { 8, 0x18 }, /* R8 - PLL6 */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
21 * 0=Release from reset.
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
25 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
26 * 0=Release from reset. Default 1.
27 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
28 * 0=Release from reset. Default 1.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dqcom_hidma_mgmt.txt18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
29 reading the source memory. Setting this value incorrectly can starve
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
35 applied back to back while reading the source before yielding the bus.
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
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