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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 ti,min-output-impedance:
37 MAC Interface Impedance control to set the programmable output impedance
40 ti,max-output-impedance:
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/kernel/linux/linux-5.10/drivers/net/phy/
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <dt-bindings/net/ti-dp83867.h>
183 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
190 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
195 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
196 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
199 return -EINVAL; in dp83867_set_wol()
213 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
215 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
217 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
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/kernel/linux/linux-5.10/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
365 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_write()
367 writew(val, ctx->base + offset); in cdns_regmap_write()
375 u32 offset = reg << ctx->reg_offset_shift; in cdns_regmap_read()
377 *val = readw(ctx->base + offset); in cdns_regmap_read()
387 writel(val, ctx->base + offset); in cdns_regmap_dptx_write()
398 *val = readl(ctx->base + offset); in cdns_regmap_dptx_read()
497 * Structure used to store values of PHY registers for voltage-related
498 * coefficients, for particular voltage swing and pre-emphasis level. Values
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/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
42 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
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/kernel/linux/patches/linux-5.10/yangfan_patch/
Ddrivers.patch6 Change-Id: I9825adaa8537a316db8a1831e759a74223b9e428
7 ---
9 drivers/block/nbd.c | 6 -
12 drivers/clk/clk.c | 2 +-
13 drivers/clk/rockchip/Kconfig | 42 +-
15 drivers/clk/rockchip/clk-cpu.c | 92 +-
16 drivers/clk/rockchip/clk-ddr.c | 171 +-
17 drivers/clk/rockchip/clk-half-divider.c | 35 +-
18 drivers/clk/rockchip/clk-pll.c | 779 ++-
19 drivers/clk/rockchip/clk-rk3399.c | 589 +-
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/kernel/linux/linux-5.10/drivers/net/ethernet/sfc/
Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0036_linux_drivers_staging.patch7 Change-Id: Ibe08cc261b06fe7f07187b5214df34e7cfed2515
9 diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
11 --- a/drivers/staging/Kconfig
13 @@ -90,6 +90,8 @@ source "drivers/staging/greybus/Kconfig"
21 source "drivers/staging/mt7621-pci/Kconfig"
22 @@ -118,6 +120,8 @@ source "drivers/staging/wfx/Kconfig"
31 diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
33 --- a/drivers/staging/Makefile
35 @@ -21,7 +21,7 @@ obj-$(CONFIG_IIO) += iio/
36 obj-$(CONFIG_FB_SM750) += sm750fb/
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