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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sram/
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 System Control Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 by a regular node for the SRAM controller itself, with sub-nodes
19 "#address-cells":
22 "#size-cells":
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/kernel/linux/linux-5.10/drivers/soc/sunxi/
Dsunxi_sram.c6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),
87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
91 .compatible = "allwinner,sun4i-a10-sram-c1",
95 .compatible = "allwinner,sun4i-a10-sram-d",
99 .compatible = "allwinner,sun50i-a64-sram-c",
120 seq_puts(s, "--------------------\n\n"); in sunxi_sram_show()
122 for_each_child_of_node(sram_dev->of_node, sram_node) { in sunxi_sram_show()
132 sram_data = match->data; in sunxi_sram_show()
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
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Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
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Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
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Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
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Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
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Dsun8i-r40.dtsi2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
50 #include <dt-bindings/thermal/thermal.h>
53 #address-cells = <1>;
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Dsun8i-a23-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
51 interrupt-parent = <&gic>;
52 #address-cells = <1>;
53 #size-cells = <1>;
56 #address-cells = <1>;
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Dsun8i-v3s.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
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/kernel/linux/linux-5.10/drivers/crypto/allwinner/sun4i-ss/
Dsun4i-ss-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
24 #include "sun4i-ss.h"
50 .cra_driver_name = "md5-sun4i-ss",
77 .cra_driver_name = "sha1-sun4i-ss",
99 .cra_driver_name = "cbc-aes-sun4i-ss",
120 .cra_driver_name = "ecb-aes-sun4i-ss",
142 .cra_driver_name = "cbc-des-sun4i-ss",
163 .cra_driver_name = "ecb-des-sun4i-ss",
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
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Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-tcon-top.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/thermal/thermal.h>
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Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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/kernel/linux/linux-5.10/drivers/ata/
Dahci_sunxi.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #define DRV_NAME "ahci-sunxi"
118 if (--timeout == 0) { in ahci_sunxi_phy_init()
120 return -EIO; in ahci_sunxi_phy_init()
133 if (--timeout == 0) { in ahci_sunxi_phy_init()
135 return -EIO; in ahci_sunxi_phy_init()
150 struct ahci_host_priv *hpriv = ap->host->private_data; in ahci_sunxi_start_engine()
156 * User's Guide document (TMS320C674x/OMAP-L1x Processor in ahci_sunxi_start_engine()
158 * March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR), in ahci_sunxi_start_engine()
173 * transmit (system bus read, device write) operation. [...] in ahci_sunxi_start_engine()
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/kernel/linux/linux-5.10/drivers/net/ethernet/allwinner/
Dsun4i-emac.c4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
33 #include "sun4i-emac.h"
35 #define DRV_NAME "sun4i-emac"
40 static int debug = -1; /* defaults above */;
51 * The EMAC uses an address register to control where data written
56 * protect the system, but the calls themselves save the address
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
100 if (db->speed == SPEED_100) in emac_update_speed()
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
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/kernel/linux/linux-5.10/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
111 supports spi-mem interface.
178 With a few GPIO pins, your system can bitbang the SPI protocol.
181 this code to manage the per-word or per-transfer accesses to the
211 Flash over 1/2/4-bit wide bus. Enable this option if you have a
219 This enables dedicated general purpose SPI/Microwire1-compatible
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/kernel/linux/linux-5.10/drivers/mfd/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 bool "Altera Arria10 DevKit System Resource chip"
28 Support for the Altera Arria10 DevKit MAX5 System Resource chip
34 bool "Altera SOCFPGA System Manager"
38 Select this to get System Manager support for all Altera branded
39 SOCFPGAs. The SOCFPGA System Manager handles all SOCFPGAs by
44 tristate "Active-semi ACT8945A"
49 Support for the ACT8945A PMIC from Active-semi. This device
50 features three step-down DC/DC converters and four low-dropout
62 Select this to get support for Allwinner SoCs (A10, A13 and A31) ADC.
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/kernel/linux/linux-5.10/drivers/mmc/host/
Dsunxi-mmc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
13 #include <linux/clk/sunxi-ng.h>
16 #include <linux/dma-mapping.h>
27 #include <linux/mmc/slot-gpio.h>
40 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
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/kernel/linux/linux-5.10/
DMAINTAINERS9 -------------------------
30 ``diff -u`` to make the patch easy to merge. Be prepared to get your
40 See Documentation/process/coding-style.rst for guidance here.
46 See Documentation/process/submitting-patches.rst for details.
57 include a Signed-off-by: line. The current version of this
59 Documentation/process/submitting-patches.rst.
70 that the bug would present a short-term risk to other users if it
76 Documentation/admin-guide/security-bugs.rst for details.
81 ---------------------------------------------------
95 it has been replaced by a better system and you
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