| /kernel/linux/linux-5.10/drivers/phy/hisilicon/ |
| D | phy-histb-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
14 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
45 struct regmap *syscon; member
48 struct phy *phy; member
49 struct histb_combphy_mode mode; member
55 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
73 static int is_mode_fixed(struct histb_combphy_mode *mode) in is_mode_fixed() argument
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| D | phy-hi3660-usb3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Phy provider for USB 3.0 controller on HiSilicon 3660 platform
5 * Copyright (C) 2017-2018 Hilisicon Electronics Co., Ltd.
12 #include <linux/mfd/syscon.h>
14 #include <linux/phy/phy.h>
54 /* This value config the default txtune parameter of the usb 2.0 phy */
65 static int hi3660_phy_init(struct phy *phy) in hi3660_phy_init() argument
67 struct hi3660_priv *priv = phy_get_drvdata(phy); in hi3660_phy_init()
72 ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, USB_REFCLK_ISO_EN); in hi3660_phy_init()
78 ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, val); in hi3660_phy_init()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | hisilicon-hns-dsaf.txt | 4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
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| D | cortina,gemini-ethernet.txt | 9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
23 - port0: contains the resources for ethernet port 0
24 - port1: contains the resources for ethernet port 1
27 - compatible: must be "cortina,gemini-ethernet-port"
28 - reg: must contain two register areas: the DMA/TOE memory and
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| D | allwinner,sun8i-a83t-emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-emac
19 - const: allwinner,sun8i-v3s-emac
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| D | socionext,uniphier-ave4.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/socionext,uniphier-ave4.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17 - $ref: ethernet-controller.yaml#
22 - socionext,uniphier-pro4-ave4
23 - socionext,uniphier-pxs2-ave4
24 - socionext,uniphier-ld11-ave4
25 - socionext,uniphier-ld20-ave4
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| D | stm32-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Alexandre Torgue <alexandre.torgue@st.com>
12 - Christophe Roullier <christophe.roullier@st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
26 - compatible
29 - $ref: "snps,dwmac.yaml#"
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| D | hisilicon-hip04-net.txt | 6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
10 phandle, specifies a reference to the syscon ppe node
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
28 - compatible: "hisilicon,hip04-ppe", "syscon".
29 - reg: address and length of the register set for the device.
36 - compatible: should be "hisilicon,mdio".
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| D | mediatek-net.txt | 10 - compatible: Should be
11 "mediatek,mt2701-eth": for MT2701 SoC
12 "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13 "mediatek,mt7622-eth": for MT7622 SoC
14 "mediatek,mt7629-eth": for MT7629 SoC
15 "ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC
16 - reg: Address and length of the register set for the device
17 - interrupts: Should contain the three frame engines interrupts in numeric
19 - clocks: the clock used by the core
20 - clock-names: the names of the clock listed in the clocks property. These are
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| D | cpsw.txt | 2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
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| D | socfpga-dwmac.txt | 9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
16 On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
26 phy-mode: The phy mode the ethernet operates in
27 altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
32 - compatible : Should be altr,gmii-to-sgmii-2.0
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| /kernel/linux/linux-5.10/drivers/phy/ti/ |
| D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/phy/phy.h>
19 #include <linux/phy/omap_control_phy.h>
21 #include <linux/mfd/syscon.h>
177 unsigned int dpll_reset_reg; /* reg. index within syscon */
178 unsigned int power_reg; /* power reg. index within syscon */
179 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
181 enum pipe3_mode mode; member
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | ti-pci.txt | 4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../designware-pcie.txt
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| D | pci-keystone.txt | 6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
24 (required if the compatible is "ti,keystone-pcie")
25 msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
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| D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
12 the PHY controller, and configuration address space.
13 - reg-names: Must include the following entries:
14 - "dbi"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | samsung-phy.txt | 2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
14 In case of exynos5433 compatible PHY:
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
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| D | brcm,brcmstb-usb-phy.txt | 1 Broadcom STB USB PHY
4 - compatible: should be one of
5 "brcm,brcmstb-usb-phy"
6 "brcm,bcm7216-usb-phy"
7 "brcm,bcm7211-usb-phy"
9 - reg and reg-names properties requirements are specific to the
11 "brcm,brcmstb-usb-phy":
12 - reg: 1 or 2 offset and length pairs. One for the base CTRL registers
14 - reg-names: not specified
15 "brcm,bcm7216-usb-phy":
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| D | rockchip-pcie-phy.txt | 1 Rockchip PCIE PHY
2 -----------------------
5 - compatible: rockchip,rk3399-pcie-phy
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "refclk"
9 - resets: Must contain an entry in reset-names.
11 - reset-names: Must be "phy"
13 Required properties for legacy PHY mode (deprecated):
14 - #phy-cells: must be 0
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| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
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| /kernel/linux/linux-5.10/drivers/media/platform/omap3isp/ |
| D | ispcsiphy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - CSI PHY module
23 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, in csiphy_routing_cfg_3630() argument
28 u32 shift, mode; in csiphy_routing_cfg_3630() local
30 regmap_read(phy->isp->syscon, phy->isp->syscon_offset, ®); in csiphy_routing_cfg_3630()
41 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
49 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; in csiphy_routing_cfg_3630()
53 /* Select data/clock or data/strobe mode for CCP2 */ in csiphy_routing_cfg_3630()
57 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE; in csiphy_routing_cfg_3630()
59 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK; in csiphy_routing_cfg_3630()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-socfpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Adopted from dwmac-sti.c
7 #include <linux/mfd/altera-sysmgr.h>
11 #include <linux/phy.h>
64 void __iomem *splitter_base = dwmac->splitter_base; in socfpga_dwmac_fix_mac_speed()
65 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base; in socfpga_dwmac_fix_mac_speed()
66 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
67 struct device *dev = dwmac->dev; in socfpga_dwmac_fix_mac_speed()
69 struct phy_device *phy_dev = ndev->phydev; in socfpga_dwmac_fix_mac_speed()
97 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); in socfpga_dwmac_fix_mac_speed()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pci-j721e.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
14 #include <linux/mfd/syscon.h>
22 #include "pcie-cadence.h"
53 u32 mode; member
67 enum j721e_pcie_mode mode; member
76 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
82 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
87 return readl(pcie->intd_cfg_base + offset); in j721e_pcie_intd_readl()
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pci-dra7xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
22 #include <linux/phy/phy.h>
27 #include <linux/mfd/syscon.h>
32 #include "pcie-designware.h"
90 int phy_count; /* DT phy-names count */
91 struct phy **phy; member
93 enum dw_pcie_device_mode mode; member
97 enum dw_pcie_device_mode mode; member
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | rk3xxx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
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