Home
last modified time | relevance | path

Searched +full:system +full:- +full:clock +full:- +full:frequency (Results 1 – 25 of 873) sorted by relevance

12345678910>>...35

/kernel/linux/linux-5.10/Documentation/timers/
Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
[all …]
/kernel/linux/linux-5.10/arch/sparc/include/asm/
Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
33 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
[all …]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dmpc5121.h1 /* SPDX-License-Identifier: GPL-2.0-only */
23 * Clock Control Module
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
29 u32 scfr1; /* System Clock Frequency Register 1 */
30 u32 scfr2; /* System Clock Frequency Register 2 */
31 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
33 u32 psc_ccr[12]; /* PSC Clock Control Registers */
34 u32 spccr; /* SPDIF Clock Control Register */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dbrcm,bcm2835-system-timer.txt1 BCM2835 System Timer
3 The System Timer peripheral provides four 32-bit timer channels and a
4 single 64-bit free running counter. Each channel has an output compare
10 - compatible : should be "brcm,bcm2835-system-timer"
11 - reg : Specifies base physical address and size of the registers.
12 - interrupts : A list of 4 interrupt sinks; one per timer channel.
13 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
18 compatible = "brcm,bcm2835-system-timer";
21 clock-frequency = <1000000>;
Darm,armv7m-systick.txt1 * ARMv7M System Timer
3 ARMv7-M includes a system timer, known as SysTick. Current driver only
7 - compatible : Should be "arm,armv7m-systick"
8 - reg : The address range of the timer
11 - clocks : The input clock of the timer
12 - clock-frequency : The rate in HZ in input of the ARM SysTick
17 compatible = "arm,armv7m-systick";
23 compatible = "arm,armv7m-systick";
25 clock-frequency = <90000000>;
/kernel/linux/linux-5.10/include/linux/
Dptp_clock_kernel.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * PTP 1588 clock support
31 * struct ptp_system_timestamp - system time corresponding to a PHC timestamp
39 * struct ptp_clock_info - describes a PTP hardware clock
41 * @owner: The clock driver should set to THIS_MODULE.
42 * @name: A short "friendly name" to identify the clock and to
45 * @max_adj: The maximum possible frequency adjustment, in parts per billon.
50 * @pps: Indicates whether the clock supports a PPS callback.
55 * clock operations
57 * @adjfine: Adjusts the frequency of the hardware clock.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
[all …]
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
Drenesas,emev2-smu.txt1 Device tree Clock bindings for Renesas EMMA Mobile EV2
3 This binding uses the common clock binding.
6 System Management Unit described in user's manual R19UH0037EJ1000_SMU.
7 This is not a clock provider, but clocks under SMU depend on it.
10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
15 "Serial clock generator" in fig."Clock System Overview" of the manual,
16 and "xxx frequency division setting register" (XXXCLKDIV) registers.
17 This makes internal (neither input nor output) clock that is provided
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/ptp/
Dptp-qoriq.txt1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfreq - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
20 * @delta: Desired frequency change in parts per billion
22 * Adjust the frequency of the PHC cycle counter by the indicated delta from
23 * the base frequency.
29 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfreq()
[all …]
/kernel/liteos_m/kernel/include/
Dlos_tick.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
56 * system time configuration modules in Los_config.h.
62 * Tick error code: The system tick timer uninitialized.
77 * system time configuration modules according to the SysTick_Config function.
83 * @brief: System timer cycles get function.
86 * This API is used to get system timer cycles.
93 * @retval: current system cycles.
128 * System Clock
166 * System time basic function error code: Null pointer.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
18 clock from a group of clients. Typically, a system has a single Arbitration
20 Arbitration Domains to increase the effective system bandwidth.
22 Protocol Arbiter, which manage a related pool of memory devices. A system
[all …]
Dnvidia,tegra20-emc.txt4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
16 Child device nodes describe the memory settings for different configurations and clock rates.
[all …]
/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/
2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
10 /sys/devices/system/cpu/cpu#/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
15 /sys/devices/system/cpu/possible
16 /sys/devices/system/cpu/present
18 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/wireless/
Dti,wlcore.txt5 connects the device to the system.
8 - compatible: should be one of the following:
20 - interrupts : specifies attributes for the out-of-band interrupt.
23 - ref-clock-frequency : ref clock frequency in Hz
24 - tcxo-clock-frequency : tcxo clock frequency in Hz
26 Note: the *-clock-frequency properties assume internal clocks. In case of external
27 clock, new bindings (for parsing the clock nodes) have to be added.
32 vmmc-supply = <&wlan_en_reg>;
33 bus-width = <4>;
34 cap-power-off-card;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of
17 platform. Audio system topology, clocking and power can all be
25 [2] include/dt-bindings/pinctrl/lochnagar.h
26 [3] include/dt-bindings/clock/lochnagar.h
28 And these documents for the required sub-node binding details:
29 [4] Clock: ../clock/cirrus,lochnagar.yaml
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-img-scb.txt4 - compatible: "img,scb-i2c"
5 - reg: Physical base address and length of controller registers
6 - interrupts: Interrupt number used by the controller
7 - clocks : Should contain a clock specifier for each entry in clock-names
8 - clock-names : Should contain the following entries:
9 "scb", for the SCB core clock.
10 "sys", for the system clock.
11 - clock-frequency: The I2C bus frequency in Hz
12 - #address-cells: Should be <1>
13 - #size-cells: Should be <0>
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ds5pv210-smdkc110.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
10 * Board device tree source for YIC System SMDC110 board.
12 * NOTE: This file is completely based on original board file for mach-smdkc110
17 /dts-v1/;
18 #include <dt-bindings/input/input.h>
22 model = "YIC System SMDKC110 based on S5PC110";
34 pmic_ap_clk: clock-0 {
35 /* Workaround for missing PMIC and its clock */
36 compatible = "fixed-clock";
[all …]
Dimx27-phytec-phycore-rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include "imx27-phytec-phycore-som.dtsi"
9 compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
12 stdout-path = &uart1;
16 model = "Sharp-LQ035Q7";
17 bits-per-pixel = <16>;
20 display-timings {
21 native-mode = <&timing0>;
23 clock-frequency = <5500000>;
26 hback-porch = <5>;
[all …]
/kernel/linux/linux-5.10/drivers/staging/mt7621-dts/
Dgbpc1.dts1 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
9 compatible = "gnubee,gb-pc1", "mediatek,mt7621-soc";
10 model = "GB-PC1";
27 gpio-keys {
28 compatible = "gpio-keys";
37 gpio-leds {
38 compatible = "gpio-leds";
40 system {
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/
Dpq2.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "fsl-soc.h"
17 #define PQ2_SCCR (0x10c80/4) /* System Clock Configuration Register */
18 #define PQ2_SCMR (0x10c88/4) /* System Clock Mode Register */
21 3, 2, 2, 2, 4, 4, 5, 9, 6, 11, 8, 10, 3, 12, 7, -1,
22 6, 5, 13, 2, 14, 4, 15, 9, 0, 11, 8, 10, 16, 12, 7, -1
25 /* Get various clocks from crystal frequency.
26 * Returns zero on failure and non-zero on success.
74 /* Set common device tree fields based on the given clock frequencies. */
83 setprop(node, "clock-frequency", &sysfreq, 4); in pq2_set_clocks()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/
Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx8qm-flexcan
21 - fsl,imx8mp-flexcan
22 - fsl,imx6q-flexcan
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "CPU Frequency scaling"
5 bool "CPU Frequency scaling"
8 CPU Frequency scaling allows you to change the clock speed of
10 the lower the CPU clock speed, the less power the CPU consumes.
13 clock speed, you need to either enable a dynamic cpufreq governor
16 For details, take a look at <file:Documentation/cpu-freq>.
31 bool "CPU frequency transition statistics"
33 Export CPU frequency statistics information through sysfs.
52 the frequency statically to the highest frequency supported by
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Dcu1830-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,tcu.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1830-neo", "ingenic,x1830";
11 model = "YSH & ATIL General Board CU1830-Neo";
18 stdout-path = "serial1:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
[all …]

12345678910>>...35