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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
[all …]
Dnvidia,tegra186-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
4 - compatible: Should contain one of the following:
5 - "nvidia,tegra186-pmc": for Tegra186
6 - "nvidia,tegra194-pmc": for Tegra194
7 - "nvidia,tegra234-pmc": for Tegra234
8 - reg: Must contain an (offset, length) pair of the register set for each
9 entry in reg-names.
10 - reg-names: Must include the following entries:
11 - "pmc"
12 - "wake"
[all …]
/kernel/linux/linux-5.10/drivers/soc/tegra/
Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
36 #include <linux/pinctrl/pinconf-generic.h>
47 #include <soc/tegra/common.h>
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-tegra/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
12 #include <linux/clk/tegra.h>
21 #include <soc/tegra/flowctrl.h>
22 #include <soc/tegra/fuse.h>
23 #include <soc/tegra/pmc.h>
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
[all …]
Dtegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NVIDIA Tegra SoC device tree board support
11 #include <linux/clk/tegra.h>
12 #include <linux/dma-mapping.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/pmc.h>
35 #include <asm/hardware/cache-l2x0.h>
38 #include <asm/mach-types.h>
50 * Storage for debug-macro.S's state.
53 * kernel is loaded. The data is declared here rather than debug-macro.S so
[all …]
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU complex suspend & resume functions for Tegra SoCs
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
8 #include <linux/clk/tegra.h>
21 #include <soc/tegra/flowctrl.h>
22 #include <soc/tegra/fuse.h>
23 #include <soc/tegra/pm.h>
24 #include <soc/tegra/pmc.h>
29 #include <asm/proc-fns.h>
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
[all …]
/kernel/linux/linux-5.10/drivers/cpuidle/
Dcpuidle-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU idle driver for Tegra CPUs
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
15 #define pr_fmt(fmt) "tegra-cpuidle: " fmt
26 #include <linux/clk/tegra.h>
29 #include <soc/tegra/cpuidle.h>
30 #include <soc/tegra/flowctrl.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/irq.h>
33 #include <soc/tegra/pm.h>
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/include/nvif/
Dos.h1 /* SPDX-License-Identifier: MIT */
15 #include <linux/i2c-algo-bit.h>
17 #include <linux/io-mapping.h>
35 #include <soc/tegra/fuse.h>
36 #include <soc/tegra/pmc.h>
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
59 * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
Dclk-tegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
12 #include <linux/clk/tegra.h>
14 #include <soc/tegra/pmc.h>
16 #include <dt-bindings/clock/tegra30-car.h>
19 #include "clk-id.h"
110 /* Tegra CPU clock and reset control regs */
593 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
594 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
595 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
[all …]
Dclk-tegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <linux/clk/tegra.h>
13 #include <dt-bindings/clock/tegra20-car.h>
16 #include "clk-id.h"
111 /* Tegra CPU clock and reset control regs */
442 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
443 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
444 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
446 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
[all …]
Dclk-tegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
12 #include <linux/clk/tegra.h>
13 #include <dt-bindings/clock/tegra114-car.h>
16 #include "clk-id.h"
20 #define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
21 #define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
112 /* Tegra CPU clock and reset control regs */
613 #define MASK(x) (BIT(x) - 1)
870 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
7 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
44 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
[all …]
Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
144 pmc {
145 nvidia,pins = "pmc";
[all …]
Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
19 stdout-path = "serial0:115200n8";
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 hdmi-supply = <&vdd_5v0_hdmi>;
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra20-trimslice.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
19 stdout-path = "serial0:115200n8";
30 vdd-supply = <&hdmi_vdd_reg>;
31 pll-supply = <&hdmi_pll_reg>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
40 pinctrl-names = "default";
[all …]
Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
31 * pre-existing /chosen node to be available to insert the
40 reserved-memory {
41 #address-cells = <1>;
[all …]
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra20-pinmux.txt4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
12 Tegra's pin configuration nodes act as a container for an arbitrary number of
16 parameters, such as pull-up, tristate, drive strength, etc.
30 Required subnode-properties:
31 - nvidia,pins : An array of strings. Each string contains the name of a pin or
34 Optional subnode-properties:
35 - nvidia,function: A string containing the name of the function to mux to the
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dnvidia,tegra124-xusb.txt1 NVIDIA Tegra xHCI controller
4 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
5 the Tegra XUSB pad controller.
8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
[all …]
/kernel/linux/linux-5.10/drivers/ata/
Dahci_tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <soc/tegra/fuse.h>
21 #include <soc/tegra/pmc.h>
25 #define DRV_NAME "tegra-ahci"
179 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks() local
182 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
183 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
185 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
191 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init() local
203 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
Dvic.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
19 #include <soc/tegra/pmc.h>
53 writel(value, vic->regs + offset); in vic_writel()
61 err = clk_prepare_enable(vic->clk); in vic_runtime_resume()
67 err = reset_control_deassert(vic->rst); in vic_runtime_resume()
76 clk_disable_unprepare(vic->clk); in vic_runtime_resume()
85 err = reset_control_assert(vic->rst); in vic_runtime_suspend()
91 clk_disable_unprepare(vic->clk); in vic_runtime_suspend()
93 vic->booted = false; in vic_runtime_suspend()
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
34 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
35 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
68 /* NVIDIA Tegra Combined UART */
89 /* SH-SCI */
100 /* Sharp LH7a40x -- an ARM9 SoC series */
159 /* MN10300 on-chip UART numbers */
165 /* SH-SCI */
[all …]

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