| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-zevio.c | 51 void __iomem *timer1, *timer2; member
67 writel(delta, timer->timer1 + IO_CURRENT_VAL); in zevio_timer_set_event()
69 timer->timer1 + IO_CONTROL); in zevio_timer_set_event()
83 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_shutdown()
108 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_interrupt()
131 timer->timer1 = timer->base + IO_TIMER1; in zevio_timer_add()
164 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_add()
165 writel(0, timer->timer1 + IO_DIVIDER); in zevio_timer_add()
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| D | timer-orion.c | 142 /* we are only interested in timer1 irq */ in orion_timer_init()
145 pr_err("%pOFn: unable to parse timer1 irq\n", np); in orion_timer_init()
169 /* setup timer1 as clockevent timer */ in orion_timer_init()
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| D | arc_timer.c | 7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
9 * We've designated TIMER0 for clockevents and TIMER1 for clocksource
193 * 32bit TIMER1 to keep counting monotonically and wraparound
207 .name = "ARC Timer1",
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| D | timer-ixp4xx.c | 170 * We use OS timer1 on the CPU for the timer tick and the timestamp
211 tmr->clkevt.name = "ixp4xx timer1"; in ixp4xx_timer_register()
222 IRQF_TIMER, "IXP4XX-TIMER1", tmr); in ixp4xx_timer_register()
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| D | timer-owl.c | 131 timer1_irq = of_irq_get_byname(node, "timer1"); in owl_timer_init()
133 pr_err("Can't parse timer1 IRQ\n"); in owl_timer_init()
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| D | Kconfig | 165 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
166 where TIMER0 serves as clockevent and TIMER1 serves as clocksource.
311 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
313 TIMER0 serves as clockevent while TIMER1 provides clocksource.
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| /kernel/linux/linux-5.10/sound/isa/gus/ |
| D | gus_timer.c | 91 struct snd_timer *timer = gus->gf1.timer1; in snd_gf1_interrupt_timer1()
132 gus->gf1.timer1 = NULL; in snd_gf1_timer1_free()
146 if (gus->gf1.timer1 != NULL || gus->gf1.timer2 != NULL) in snd_gf1_timers_init()
164 gus->gf1.timer1 = timer; in snd_gf1_timers_init()
180 if (gus->gf1.timer1) { in snd_gf1_timers_done()
181 snd_device_free(gus->card, gus->gf1.timer1); in snd_gf1_timers_done()
182 gus->gf1.timer1 = NULL; in snd_gf1_timers_done()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | ezchip,nps400-timer1.txt | 5 - compatible : should be "ezchip,nps400-timer1"
7 Clocks required for compatible = "ezchip,nps400-timer1":
13 compatible = "ezchip,nps400-timer1";
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| D | snps,arc-timer.txt | 4 - Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
6 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
24 timer1 {
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| D | cirrus,clps711x-timer.txt | 13 timer0 = &timer1;
14 timer1 = &timer2;
17 timer1: timer@80000300 {
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| D | actions,owl-timer.txt | 10 "timer0", "timer1", "timer2", "timer3"
20 interrupt-names = "timer0", "timer1";
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| D | arm,sp804.yaml | 56 be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
96 clock-names = "timer1", "timer2", "apb_pclk";
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| D | marvell,orion-timer.txt | 6 - interrupts: should contain the interrupts for Timer0 and Timer1
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| D | nxp,lpc3220-timer.txt | 20 timer1: timer@40085000 {
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| D | arm,mps2-timer.txt | 16 timer1: mps2-timer@40000000 {
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| /kernel/linux/linux-5.10/arch/arc/boot/dts/ |
| D | skeleton.dtsi | 38 /* TIMER1 for free running clocksource */
39 timer1 {
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| D | skeleton_hs.dtsi | 39 /* TIMER1 for free running clocksource: Fallback if rtc not found */
40 timer1 {
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray.dtsi | 346 clock-names = "timer1", "timer2", "apb_pclk";
350 timer1: timer@40000 { label
357 clock-names = "timer1", "timer2", "apb_pclk";
367 clock-names = "timer1", "timer2", "apb_pclk";
378 clock-names = "timer1", "timer2", "apb_pclk";
389 clock-names = "timer1", "timer2", "apb_pclk";
400 clock-names = "timer1", "timer2", "apb_pclk";
411 clock-names = "timer1", "timer2", "apb_pclk";
422 clock-names = "timer1", "timer2", "apb_pclk";
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | ep7209.dtsi | 21 timer0 = &timer1;
22 timer1 = &timer2;
114 timer1: timer@80000300 { label
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| /kernel/linux/linux-5.10/arch/arm/mach-cns3xxx/ |
| D | core.c | 154 .name = "cns3xxx timer1",
204 /* disable timer1 and timer2 */ in __cns3xxx_timer_init()
209 /* timer1 */ in __cns3xxx_timer_init()
216 /* mask irq, non-mask timer1 overflow */ in __cns3xxx_timer_init()
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| /kernel/linux/linux-5.10/sound/drivers/opl3/ |
| D | opl3_lib.c | 98 /* Set timer1 to 0xff */ in snd_opl3_detect()
251 opl3->timer1 = timer; in snd_opl3_timer1_init()
297 timer = opl3->timer1; in snd_opl3_interrupt()
457 snd_device_free(opl3->card, opl3->timer1); in snd_opl3_timer_new()
458 opl3->timer1 = NULL; in snd_opl3_timer_new()
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| /kernel/linux/linux-5.10/arch/m68k/bvme6000/ |
| D | config.c | 187 * So, when reading the elapsed time, you should read timer1,
251 rtc->t1cr_omr |= 0x40; /* Latch timer1 */ in bvme6000_read_clk()
252 msb = rtc->t1msb; /* Read timer1 */ in bvme6000_read_clk()
253 v = (msb << 8) | rtc->t1lsb; /* Read timer1 */ in bvme6000_read_clk()
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| /kernel/linux/linux-5.10/drivers/pci/hotplug/ |
| D | cpcihp_zt5550.c | 113 * Disable timer0, timer1 and ENUM interrupts in zt5550_hc_config()
115 dbg("disabling timer0, timer1 and ENUM interrupts"); in zt5550_hc_config()
117 dbg("disabled timer0, timer1 and ENUM interrupts"); in zt5550_hc_config()
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-clps711x.c | 94 /* Timer1 in free running mode. in clps711x_clk_init_dt()
117 clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0, in clps711x_clk_init_dt()
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| /kernel/linux/linux-5.10/drivers/net/wireless/ath/ath5k/ |
| D | pcu.c | 650 u32 timer1, timer2, timer3; in ath5k_hw_init_beacon_timers() local
658 /* In STA mode timer1 is used as next wakeup in ath5k_hw_init_beacon_timers()
663 timer1 = 0xffffffff; in ath5k_hw_init_beacon_timers()
666 timer1 = 0x0000ffff; in ath5k_hw_init_beacon_timers()
676 /* On non-STA modes timer1 is used as next DMA in ath5k_hw_init_beacon_timers()
679 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; in ath5k_hw_init_beacon_timers()
698 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); in ath5k_hw_init_beacon_timers()
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