| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,vic.txt | 5 nested or have the outputs wire-OR'd together.
9 - compatible : should be one of
10 "arm,pl190-vic"
11 "arm,pl192-vic"
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
16 - reg : The register bank for the VIC.
20 - interrupts : Interrupt source for parent controllers if the VIC is nested.
21 - valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
24 clear means otherwise. If unspecified, defaults to all valid.
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| D | arm,versatile-fpga-irq.txt | 9 - compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
10 - interrupt-controller: Identifies the node as an interrupt controller
11 - #interrupt-cells: The number of cells to define the interrupts. Must be 1
14 - reg: The register bank for the FPGA interrupt controller.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
18 the interrupts are valid. Unconnected/unused lines are set to 0, and
25 compatible = "arm,versatile-fpga-irq";
26 #interrupt-cells = <1>;
27 interrupt-controller;
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| /kernel/linux/linux-5.10/net/netlabel/ |
| D | netlabel_addrlist.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
27 * struct netlbl_af4list - NetLabel IPv4 address list
29 * @mask: IPv4 address mask
30 * @valid: valid flag
35 __be32 mask; member
37 u32 valid; member
42 * struct netlbl_af6list - NetLabel IPv6 address list
44 * @mask: IPv6 address mask
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| D | netlabel_addrlist.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
36 * netlbl_af4list_search - Search for a matching IPv4 address entry
52 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
59 * netlbl_af4list_search_exact - Search for an exact IPv4 address entry
61 * @mask: IPv4 address mask
71 __be32 mask, in netlbl_af4list_search_exact() argument
77 if (iter->valid && iter->addr == addr && iter->mask == mask) in netlbl_af4list_search_exact()
86 * netlbl_af6list_search - Search for a matching IPv6 address entry
[all …]
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| D | netlabel_unlabeled.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Author: Paul Moore <paul@paul-moore.com>
13 * (c) Copyright Hewlett-Packard Development Company, L.P., 2006 - 2008
87 u32 valid; member
126 .len = IFNAMSIZ - 1 },
135 * netlbl_unlhsh_free_iface - Frees an interface entry from the hash table
162 netlbl_af4list_foreach_safe(iter4, tmp4, &iface->addr4_list) { in netlbl_unlhsh_free_iface()
167 netlbl_af6list_foreach_safe(iter6, tmp6, &iface->addr6_list) { in netlbl_unlhsh_free_iface()
176 * netlbl_unlhsh_hash - Hashing function for the hash table
188 return ifindex & (netlbl_unlhsh_rcu_deref(netlbl_unlhsh)->size - 1); in netlbl_unlhsh_hash()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/apm/xgene/ |
| D | xgene_enet_cle.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Classifier structures
27 if (pdata->enet_id == XGENE_ENET1) { in xgene_cle_idt_to_hw()
41 buf[0] = SET_VAL(CLE_DROP, dbptr->drop); in xgene_cle_dbptr_to_hw()
42 buf[4] = SET_VAL(CLE_FPSEL, dbptr->fpsel) | in xgene_cle_dbptr_to_hw()
43 SET_VAL(CLE_NFPSEL, dbptr->nxtfpsel) | in xgene_cle_dbptr_to_hw()
44 SET_VAL(CLE_DSTQIDL, dbptr->dstqid); in xgene_cle_dbptr_to_hw()
46 buf[5] = SET_VAL(CLE_DSTQIDH, (u32)dbptr->dstqid >> CLE_DSTQIDL_LEN) | in xgene_cle_dbptr_to_hw()
47 SET_VAL(CLE_PRIORITY, dbptr->cle_priority); in xgene_cle_dbptr_to_hw()
55 buf[j++] = SET_VAL(CLE_TYPE, kn->node_type); in xgene_cle_kn_to_hw()
[all …]
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-versatile-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Versatile FPGA-based IRQ controllers
10 #include <linux/irqchip/versatile-fpga.h>
35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
39 * @valid: mask for valid IRQs on this controller
45 u32 valid; member
57 u32 mask = 1 << d->hwirq; in fpga_irq_mask() local
59 writel(mask, f->base + IRQ_ENABLE_CLEAR); in fpga_irq_mask()
65 u32 mask = 1 << d->hwirq; in fpga_irq_unmask() local
67 writel(mask, f->base + IRQ_ENABLE_SET); in fpga_irq_unmask()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/macsec/ |
| D | macsec_struct.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
21 /*! The match mask is per-nibble. 0 means don't care, i.e. every value
68 /*! This is to specify the 40bit SNAP header if the SNAP header's mask
72 /*! This is to specify the 24bit LLC header if the LLC header's mask is
122 /*! Mask is per-byte.
132 * 1: enable comparison of extracted VLAN Valid field.
135 /*! This is bit mask to enable comparison the 8 bit TCI field,
142 /*! Mask is per-byte.
151 /*! Mask is per-byte.
156 /*! Mask is per-byte.
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| /kernel/linux/linux-5.10/drivers/net/ethernet/pensando/ionic/ |
| D | ionic_regs.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2 /* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */
9 /** struct ionic_intr - interrupt control register set.
11 * @mask: interrupt mask value.
13 * @mask_assert: interrupt mask value on assert.
18 u32 mask; member
28 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
30 * @IONIC_INTR_MASK_SET: mask interrupt.
37 /** enum ionic_intr_credits_bits - bitwise composition of credits values.
38 * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | s3c6400.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
23 valid-mask = <0xfffffe1f>;
24 valid-wakeup-mask = <0x00200004>;
28 valid-mask = <0xffffffff>;
29 valid-wakeup-mask = <0x53020000>;
33 clocks: clock-controller@7e00f000 {
34 compatible = "samsung,s3c6400-clock";
36 #clock-cells = <1>;
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| D | s3c6410.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
37 clocks: clock-controller@7e00f000 {
38 compatible = "samsung,s3c6410-clock";
40 #clock-cells = <1>;
44 compatible = "samsung,s3c2440-i2c";
46 interrupt-parent = <&vic0>;
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ipa/ |
| D | ipa_smp2p.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2020 Linaro Ltd.
34 * whether the clock is enabled using two SMP2P state bits--one to
36 * clock state bit is valid. The modem will poll the valid bit until it
44 * struct ipa_smp2p - IPA SMP2P information
46 * @valid_state: SMEM state indicating enabled state is valid
48 * @valid_bit: Valid bit in 32-bit SMEM state mask
49 * @enabled_bit: Enabled bit in 32-bit SMEM state mask
50 * @enabled_bit: Enabled bit in 32-bit SMEM state mask
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| /kernel/liteos_m/kernel/include/ |
| D | los_event.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
68 * Bit 25 of the event mask cannot be set to an event because it is set to an error code.
72 * Solution: Set bits excluding bit 25 of the event mask to events.
81 …* Solution: Increase the waiting time for event reading, or make another task write a mask for the…
87 …* Event reading error code: The EVENTMASK input parameter value is valid. The input parameter valu…
91 * Solution: Pass in a valid EVENTMASK value.
114 * Solution: Pass in a valid uwFlags value.
160 * Event reading error code: The event is being read in a system-level task.
163 * Solution: Read the event in a valid task.
[all …]
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| /kernel/liteos_a/kernel/include/ |
| D | los_event.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
69 * Bit 25 of the event mask cannot be set to an event because it is set to an error code.
73 * Solution: Set bits excluding bit 25 of the event mask to events.
83 …* Solution: Increase the waiting time for event reading, or make another task write a mask for the…
89 …* Event reading error code: The EVENTMASK input parameter value is valid. The input parameter valu…
93 * Solution: Pass in a valid EVENTMASK value.
116 * Solution: Pass in a valid flag value.
142 * Event reading error code: The event is being read in system-level task.
165 UINT32 uwEventID; /**< Event mask in the event control block,
[all …]
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| /kernel/linux/linux-5.10/include/linux/ |
| D | regmap.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
48 * struct reg_default - Default value for a register.
62 * struct reg_sequence - An individual write from a sequence of writes.
85 * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs
92 * tight-loops). Should be less than ~20ms since usleep_range
93 * is used (see Documentation/timers/timers-howto.rst).
96 * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
112 * regmap_read_poll_timeout_atomic - Poll until a condition is met or a timeout occurs
118 * @delay_us: Time to udelay between reads in us (0 tight-loops).
120 * (see Documentation/timers/timers-howto.rst).
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | mfp-pxa2xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
13 #include <linux/gpio-pxa.h>
20 #include <mach/pxa2xx-regs.h>
21 #include "mfp-pxa2xx.h"
30 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
39 unsigned valid : 1; member
43 unsigned int mask; /* bit mask in PWER or PKWR */ member
44 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
54 unsigned long gafr, mask = GPIO_bit(gpio); in __mfp_config_gpio() local
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/hwmon/ |
| D | max6697.txt | 4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
24 Only valid for MAX6581. Set to enable extended temperature range.
26 - beta-compensation-enable
27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
34 - over-temperature-mask
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | vc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
24 * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
35 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
36 * @i2c_mcode_mask: MCODE field mask for I2C config register
39 * XXX VALID should probably be a shift, not a mask
43 u32 valid; member
63 * struct omap_vc_channel - VC per-instance data
69 * @i2c_high_speed: whether or not to use I2C high-speed mode
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | davinci-nand.txt | 7 Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
8 Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
15 - reg: Contains 2 offset/length values:
16 - offset and length for the access window.
17 - offset and length for accessing the AEMIF
20 - ti,davinci-chipselect: number of chipselect. Indicates on the
23 Can be in the range [0-3].
27 - ti,davinci-mask-ale: mask for ALE. Needed for executing address
[all …]
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| /kernel/linux/linux-5.10/drivers/misc/cxl/ |
| D | hcalls.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 * The 'flags' parameter regroups the various bit-fields
59 * cxl_h_detach_process - Detach a process element from a coherent
65 * cxl_h_reset_afu - Perform a reset to the coherent platform function.
70 * cxl_h_suspend_process - Suspend a process from being executed
71 * Parameter1 = process-token as returned from H_ATTACH_CA_PROCESS when
77 * cxl_h_resume_process - Resume a process to be executed
78 * Parameter1 = process-token as returned from H_ATTACH_CA_PROCESS when
84 * cxl_h_read_error_state - Reads the error state of the coherent
91 * cxl_h_get_afu_err - collect the AFU error buffer
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_types.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
21 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
22 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
23 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg)
75 DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK,
144 /* total number of valid entries belonging to this hash table. This
209 htbl->refcount--; in mlx5dr_htbl_put()
210 if (!htbl->refcount) in mlx5dr_htbl_put()
216 htbl->refcount++; in mlx5dr_htbl_get()
257 ste->refcount--; in mlx5dr_ste_put()
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| /kernel/linux/linux-5.10/arch/x86/include/asm/fpu/ |
| D | internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * x86-64 work by Andi Kleen 2002
96 xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT | xfeatures_mask_all; in fpstate_init_xstate()
101 fx->cwd = 0x37f; in fpstate_init_fxstate()
102 fx->mxcsr = MXCSR_DEFAULT; in fpstate_init_fxstate()
106 /* Returns 0 or the negated trap number, which results in -EFAULT for #PF */
132 "3: movl $-1,%[err]\n" \
203 asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave)); in copy_fxregs_to_kernel()
205 asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave)); in copy_fxregs_to_kernel()
225 * the operation raises an exception. For faults this results in -EFAULT.
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4_filter.c | 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
46 static inline bool is_field_set(u32 val, u32 mask) in is_field_set() argument
48 return val || mask; in is_field_set()
51 static inline bool unsupported(u32 conf, u32 conf_mask, u32 val, u32 mask) in unsupported() argument
53 return !(conf & conf_mask) && is_field_set(val, mask); in unsupported()
57 unsigned int ftid, u16 word, u64 mask, u64 val, in set_tcb_field() argument
65 return -ENOMEM; in set_tcb_field()
69 req->reply_ctrl = htons(REPLY_CHAN_V(0) | in set_tcb_field()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ti/ |
| D | clkt_dpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
17 #include <linux/clk-provider.h>
30 #define DPLL_MULT_UNDERFLOW -1
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
51 #define DPLL_FINT_UNDERFLOW -1
52 #define DPLL_FINT_INVALID -2
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
[all …]
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| /kernel/linux/linux-5.10/drivers/ata/ |
| D | pata_acpi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
26 unsigned long mask[2]; member
30 * pacpi_pre_reset - check for 40/80 pin
39 struct ata_port *ap = link->ap; in pacpi_pre_reset()
40 struct pata_acpi *acpi = ap->private_data; in pacpi_pre_reset()
41 if (ACPI_HANDLE(&ap->tdev) == NULL || ata_acpi_gtm(ap, &acpi->gtm) < 0) in pacpi_pre_reset()
42 return -ENODEV; in pacpi_pre_reset()
48 * pacpi_cable_detect - cable type detection
56 struct pata_acpi *acpi = ap->private_data; in pacpi_cable_detect()
58 if ((acpi->mask[0] | acpi->mask[1]) & (0xF8 << ATA_SHIFT_UDMA)) in pacpi_cable_detect()
[all …]
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