1 /* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARCH_CONFIG_H 33 #define _ARCH_CONFIG_H 34 35 36 #define CPSR_INT_DISABLE 0xC0 /* Disable both FIQ and IRQ */ 37 #define CPSR_IRQ_DISABLE 0x80 /* IRQ disabled when =1 */ 38 #define CPSR_FIQ_DISABLE 0x40 /* FIQ disabled when =1 */ 39 #define CPSR_THUMB_ENABLE 0x20 /* Thumb mode when =1 */ 40 #define CPSR_USER_MODE 0x10 41 #define CPSR_FIQ_MODE 0x11 42 #define CPSR_IRQ_MODE 0x12 43 #define CPSR_SVC_MODE 0x13 44 #define CPSR_ABT_MODE 0x17 45 #define CPSR_UNDEF_MODE 0x1B 46 #define CPSR_MASK_MODE 0x1F 47 48 /* Define exception type ID */ 49 #define OS_EXCEPT_RESET 0x00 50 #define OS_EXCEPT_UNDEF_INSTR 0x01 51 #define OS_EXCEPT_SWI 0x02 52 #define OS_EXCEPT_PREFETCH_ABORT 0x03 53 #define OS_EXCEPT_DATA_ABORT 0x04 54 #define OS_EXCEPT_FIQ 0x05 55 #define OS_EXCEPT_ADDR_ABORT 0x06 56 #define OS_EXCEPT_IRQ 0x07 57 58 /* Define core num */ 59 #ifdef LOSCFG_KERNEL_SMP 60 #define CORE_NUM LOSCFG_KERNEL_SMP_CORE_NUM 61 #else 62 #define CORE_NUM 1 63 #endif 64 65 /* Initial bit32 stack value. */ 66 #define OS_STACK_INIT 0xCACACACA 67 /* Bit32 stack top magic number. */ 68 #define OS_STACK_MAGIC_WORD 0xCCCCCCCC 69 70 #ifdef LOSCFG_GDB 71 #define OS_EXC_UNDEF_STACK_SIZE 512 72 #define OS_EXC_ABT_STACK_SIZE 512 73 #else 74 #define OS_EXC_UNDEF_STACK_SIZE 40 75 #define OS_EXC_ABT_STACK_SIZE 40 76 #endif 77 #define OS_EXC_FIQ_STACK_SIZE 64 78 #define OS_EXC_IRQ_STACK_SIZE 64 79 #define OS_EXC_SVC_STACK_SIZE 0x2000 80 #define OS_EXC_STACK_SIZE 0x1000 81 82 #define REG_R0 0 83 #define REG_R1 1 84 #define REG_R2 2 85 #define REG_R3 3 86 #define REG_R4 4 87 #define REG_R5 5 88 #define REG_R6 6 89 #define REG_R7 7 90 #define REG_R8 8 91 #define REG_R9 9 92 #define REG_R10 10 93 #define REG_R11 11 94 #define REG_R12 12 95 #define REG_R13 13 96 #define REG_R14 14 97 #define REG_R15 15 98 #define REG_CPSR 16 99 #define REG_SP REG_R13 100 #define REG_LR REG_R14 101 #define REG_PC REG_R15 102 #endif