1 /* 2 * Copyright (C) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __DRV_I2C_H_ 20 #define __DRV_I2C_H_ 21 22 #include "hi_type.h" 23 24 #ifdef __cplusplus 25 #if __cplusplus 26 extern "C" { 27 #endif 28 #endif /* __cplusplus */ 29 30 #if defined(HI_FPGA) 31 #define I2C_DFT_SYSCLK (12500000) 32 #else 33 #define I2C_DFT_SYSCLK (100000000) 34 #endif 35 36 #define I2C_DFT_RATE (100000) 37 38 #define I2C0_PHY_ADDR (0xF8B10000) 39 #define I2C1_PHY_ADDR (0xF8B11000) 40 #define I2C2_PHY_ADDR (0xF8B12000) 41 #define I2C3_PHY_ADDR (0xF8B13000) 42 #define I2C_TUNER_ADDR (0xF8B1D000) 43 #define I2C_DTMB_ADDR (0xFF2F1000) 44 #define I2C_ADC_ADDR (0xFF2F2000) 45 46 #define I2C_CTRL_REG (0x000) 47 #define I2C_COM_REB (0x004) 48 #define I2C_ICR_REG (0x008) 49 #define I2C_SR_REG (0x00C) 50 #define I2C_SCL_H_REG (0x010) 51 #define I2C_SCL_L_REG (0x014) 52 #define I2C_TXR_REG (0x018) 53 #define I2C_RXR_REG (0x01C) 54 55 #define READ_OPERATION (1) 56 #define WRITE_OPERATION 0xfe 57 58 /* I2C_CTRL_REG */ 59 #define I2C_ENABLE (1 << 8) 60 #define I2C_UNMASK_TOTAL (1 << 7) 61 #define I2C_UNMASK_START (1 << 6) 62 #define I2C_UNMASK_END (1 << 5) 63 #define I2C_UNMASK_SEND (1 << 4) 64 #define I2C_UNMASK_RECEIVE (1 << 3) 65 #define I2C_UNMASK_ACK (1 << 2) 66 #define I2C_UNMASK_ARBITRATE (1 << 1) 67 #define I2C_UNMASK_OVER (1 << 0) 68 #define I2C_UNMASK_ALL (I2C_UNMASK_START | I2C_UNMASK_END | \ 69 I2C_UNMASK_SEND | I2C_UNMASK_RECEIVE | \ 70 I2C_UNMASK_ACK | I2C_UNMASK_ARBITRATE | \ 71 I2C_UNMASK_OVER) 72 73 /* I2C_COM_REB */ 74 #define I2C_SEND_ACK (~(1 << 4)) 75 #define I2C_START (1 << 3) 76 #define I2C_READ (1 << 2) 77 #define I2C_WRITE (1 << 1) 78 #define I2C_STOP (1 << 0) 79 80 /* I2C_ICR_REG */ 81 #define I2C_CLEAR_START (1 << 6) 82 #define I2C_CLEAR_END (1 << 5) 83 #define I2C_CLEAR_SEND (1 << 4) 84 #define I2C_CLEAR_RECEIVE (1 << 3) 85 #define I2C_CLEAR_ACK (1 << 2) 86 #define I2C_CLEAR_ARBITRATE (1 << 1) 87 #define I2C_CLEAR_OVER (1 << 0) 88 #define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \ 89 I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \ 90 I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \ 91 I2C_CLEAR_OVER) 92 93 /* I2C_SR_REG */ 94 #define I2C_BUSY (1 << 7) 95 #define I2C_START_INTR (1 << 6) 96 #define I2C_END_INTR (1 << 5) 97 #define I2C_SEND_INTR (1 << 4) 98 #define I2C_RECEIVE_INTR (1 << 3) 99 #define I2C_ACK_INTR (1 << 2) 100 #define I2C_ARBITRATE_INTR (1 << 1) 101 #define I2C_OVER_INTR (1 << 0) 102 103 hi_void i2c_drv_set_rate(hi_u32 i2c_num, hi_u32 i2c_rate); 104 hi_s32 i2c_drv_get_rate(hi_u32 i2c_num); 105 hi_s32 hi_drv_i2c_cmd_write(unsigned int cmd, hi_void *arg, hi_void *private_data); 106 hi_s32 hi_drv_i2c_cmd_read(unsigned int cmd, hi_void *arg, hi_void *private_data); 107 hi_s32 hi_drv_i2c_cmd_set_rate(unsigned int cmd, hi_void *arg, hi_void *private_data); 108 109 #define I2C0 (0) 110 #define I2C1 (1) 111 #define I2C2 (2) 112 #define I2C3 (3) 113 #define I2C7 (4) 114 115 hi_s32 i2c_pm_resume(hi_void *private_data); 116 hi_s32 i2c_pm_suspend(hi_void *private_data); 117 hi_s32 i2c_drv_lowpower_enter(hi_void *private_data); 118 hi_s32 i2c_drv_lowpower_exit(hi_void *private_data); 119 120 #ifdef __cplusplus 121 #if __cplusplus 122 } 123 #endif 124 #endif /* __cplusplus */ 125 126 #endif 127