1 /* 2 * Copyright (C) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __DRV_MMZ_IOCTL_H__ 20 #define __DRV_MMZ_IOCTL_H__ 21 22 #define HIL_MAX_NAME_LEN 16 23 24 /* remove pclint warning anonymous struct or union */ 25 struct mmb_info { 26 HI_U32 phys_addr; /* phys-memory address */ 27 HI_U32 smmu_addr; 28 HI_U32 align; /* phys-memory's special align size */ 29 HI_U32 size; /* length of memory, in bytes */ 30 HI_U8 *mapped; /* userspace mapped ptr */ 31 32 struct { 33 HI_U32 prot : 8; /* PROT_READ or PROT_WRITE */ 34 HI_U32 flags : 12; /* MAP_SHARED or MAP_PRIVATE */ 35 HI_U32 reserved : 12; /* reserved, do not use */ 36 }; 37 char mmb_name[HIL_MAX_NAME_LEN]; 38 char mmz_name[HIL_MAX_NAME_LEN]; 39 HI_U32 gfp; /* reserved, do set to 0 */ 40 41 HI_U32 ref; /* reference count of current memory block */ 42 HI_U8 source; /* query result of smmu addr */ 43 HI_S32 fd; /* exported fd of dma buffer */ 44 45 HI_U32 pt_addr; /* pg_table addr */ 46 HI_U32 err_rd_addr; 47 HI_U32 err_wr_addr; 48 }; 49 50 struct dirty_area { 51 HI_U32 dirty_phys_start; /* dirty physical address */ 52 HI_U8 *dirty_virt_start; /* dirty virtual address, 53 must be coherent with dirty_phys_addr */ 54 HI_U32 dirty_size; 55 }; 56 57 struct sec_info { 58 char mmb_name[HIL_MAX_NAME_LEN]; 59 char mmz_name[HIL_MAX_NAME_LEN]; 60 HI_U32 sec_smmu; 61 HI_U32 nosec_smmu; 62 HI_U32 phys_addr; 63 HI_U32 size; 64 HI_U32 align; 65 }; 66 67 #define IOC_MMB_ALLOC _IOWR('m', 10, struct mmb_info) 68 #define IOC_MMB_FREE _IOW('m', 12, struct mmb_info) 69 #define IOC_MMB_GET _IOW('m', 13, struct mmb_info) 70 #define IOC_MMB_PUT _IOW('m', 15, struct mmb_info) 71 72 #define IOC_MMB_USER_REMAP _IOWR('m', 20, struct mmb_info) 73 #define IOC_MMB_USER_REMAP_CACHED _IOWR('m', 21, struct mmb_info) 74 #define IOC_MMB_USER_UNMAP _IOWR('m', 22, struct mmb_info) 75 #define IOC_MMB_USER_GETPHYADDR _IOWR('m', 23, struct mmb_info) 76 77 #define IOC_MMB_USER_CMA_MAPTO_SMMU _IOWR('m', 25, struct mmb_info) 78 #define IOC_MMB_USER_CMA_UNMAPTO_SMMU _IOWR('m', 26, struct mmb_info) 79 #define IOC_MMB_USER_QUERY_REF _IOWR('m', 27, struct mmb_info) 80 #define IOC_MMB_USER_QUERY_SRC _IOWR('m', 28, struct mmb_info) 81 82 #define IOC_MMB_SECSMMU_ALLOC _IOWR('s', 12, struct sec_info) 83 #define IOC_MMB_SECSMMU_FREE _IOWR('s', 13, struct sec_info) 84 #define IOC_MMB_SECSMMU_MAPTOSECSMMU _IOWR('s', 10, struct sec_info) 85 #define IOC_MMB_SECSMMU_UNMAPFROMSMMU _IOWR('s', 11, struct sec_info) 86 87 #define IOC_MMB_FLUSH_DCACHE _IOWR('c', 40, struct mmb_info) 88 89 #define IOC_MMB_TEST_CACHE _IOW('t', 11, struct mmb_info) 90 91 /* notice that these two CMDs are not managed by mmz */ 92 #define IOC_DMA_BUF_EXPORT_FD _IOWR('m', 29, struct mmb_info) 93 #define IOC_SMMU_GET_PGTABLE_ADDR _IOWR('m', 30, struct mmb_info) 94 95 #endif /* __DRV_MMZ_IOCTL_H__ */ 96 97