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Searched refs:writeback (Results 1 – 25 of 30) sorted by relevance

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/third_party/python/Lib/
Dshelve.py84 def __init__(self, dict, protocol=None, writeback=False, argument
90 self.writeback = writeback
115 if self.writeback:
120 if self.writeback:
165 if self.writeback and self.cache:
166 self.writeback = False
169 self.writeback = True
188 def __init__(self, dict, protocol=None, writeback=False, argument
190 Shelf.__init__(self, dict, protocol, writeback, keyencoding)
225 def __init__(self, filename, flag='c', protocol=None, writeback=False): argument
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/third_party/python/Doc/library/
Dshelve.rst20 .. function:: open(filename, flag='c', protocol=None, writeback=False)
35 optional *writeback* parameter is set to ``True``, all entries accessed are also
73 Write back all entries in the cache if the shelf was opened with *writeback*
114 .. class:: Shelf(dict, protocol=None, writeback=False, keyencoding='utf-8')
124 If the *writeback* parameter is ``True``, the object will hold a cache of all
147 .. class:: BsdDbShelf(dict, protocol=None, writeback=False, keyencoding='utf-8')
156 optional *protocol*, *writeback*, and *keyencoding* parameters have the same
160 .. class:: DbfilenameShelf(filename, flag='c', protocol=None, writeback=False)
166 function. The optional *protocol* and *writeback* parameters have the same
193 # as d was opened WITHOUT writeback=True, beware:
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/third_party/ntfs-3g/libntfs-3g/
Dlcnalloc.c172 u8 *writeback) in bitmap_writeback() argument
178 if (!*writeback) in bitmap_writeback()
181 *writeback = 0; in bitmap_writeback()
244 u8 *buf, *byte, bit, writeback; in ntfs_cluster_alloc() local
336 writeback = 0; in ntfs_cluster_alloc()
370 writeback = 1; in ntfs_cluster_alloc()
423 if (bitmap_writeback(vol, last_read_pos, br, buf, &writeback)) { in ntfs_cluster_alloc()
537 if (bitmap_writeback(vol, last_read_pos, br, buf, &writeback)) { in ntfs_cluster_alloc()
554 if (bitmap_writeback(vol, last_read_pos, br, buf, &writeback)) in ntfs_cluster_alloc()
/third_party/python/Lib/test/
Dtest_shelve.py53 s = shelve.Shelf(d1, protocol=2, writeback=False)
101 with shelve.Shelf(d1, protocol=2, writeback=False) as s:
108 with shelve.Shelf(d2, protocol=2, writeback=True) as s:
135 with shelve.Shelf(d, writeback=True) as s:
144 with shelve.Shelf(d1, protocol=2, writeback=False) as s:
/third_party/mesa3d/src/panfrost/lib/
Dpan_format.h46 /* enum mali_mfbd_color_format */ uint16_t writeback; member
Dpan_format.c47 #define BFMT2(pipe, internal, writeback, srgb) \ argument
50 MALI_COLOR_FORMAT_## writeback, \
57 #define BFMT2(pipe, internal, writeback, srgb) \ argument
60 MALI_COLOR_FORMAT_## writeback, \
69 #define BFMT_SRGB(pipe, writeback) \ argument
70 BFMT2(pipe ##_UNORM, R8G8B8A8, writeback, 0), \
71 BFMT2(pipe ##_SRGB, R8G8B8A8, writeback, 1)
Dpan_shader.c193 unsigned wb_fmt = panfrost_blendable_formats_v6[fmt].writeback; in GENX()
Dpan_cs.c370 cfg->writeback_format = fmt.writeback; in pan_rt_init_format()
783 cfg.color_writeback_format = fmt.writeback; in pan_emit_sfbd()
/third_party/mesa3d/.gitlab-ci/
Dcrosvm-runner.sh41 --shared-dir /:my_root:type=fs:writeback=true:timeout=60:cache=always \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td63 // consumes the pipe for one cycle at issue and another cycle at writeback.
92 // but only consume the pipe for one cycle at issue and a cycle at writeback.
205 // The ID pipe is consumed for 2 cycles: issue and writeback.
212 // The ID pipe is consumed for 2 cycles: issue and writeback.
628 // Only the first WriteVLD and WriteAdr for writeback matches def operands.
769 // Only the WriteAdr for writeback matches a def operands.
DAArch64InstrFormats.td1542 def writeback : BaseAuthLoad<M, 1, (outs GPR64sp:$wback, GPR64:$Rt),
1551 (!cast<Instruction>(NAME # "writeback") GPR64sp:$wback, GPR64:$Rt, 0), 0>;
/third_party/ffmpeg/libavcodec/arm/
Dvp9lpf_16bpp_neon.S835 @ If we didn't need to do the flat8in part, we use the same writeback
Dvp9lpf_neon.S900 @ The same writeback as in loop_filter_h_8_8
917 @ The same writeback as in loop_filter_h_4_8
/third_party/ltp/testcases/kernel/mce-test/doc/cases/
Dsoft-inj_recoverable_ucr.txt47 * Exception message is "Action optional: last level cache writeback error"
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1880 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction() local
1882 if (P && writeback) in DecodeAddrMode2IdxInstruction()
1884 else if (!P && writeback) in DecodeAddrMode2IdxInstruction()
1887 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1987 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction() local
2009 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2023 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2040 if (!type && writeback && Rn == 15) in DecodeAddrMode3Instruction()
2042 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2057 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleA9.td447 // register file writeback!).
2336 // A9WriteAdr consumes AGU regardless address writeback. But it's
2346 // Store either has no def operands, or the one def for address writeback.
2364 // Load multiple with address writeback has an extra def operand in
2368 // resources are identical, For stores only the address writeback
2383 // Note: Unlike VLDM, VLD1 expects the writeback operand after the
2404 // address writeback.
DARMScheduleA57.td595 // TODO: no writeback latency defined in documentation (implemented as 1 cyc)
629 // Store, immed pre-indexed (1cyc "S, I0/I1", 1cyc writeback)
691 // TODO: no writeback latency defined in documentation
1270 // 1-2 reg: 5cyc L, +I for writeback, 1 cyc wb latency
1275 // 3-4 reg: 6cyc L, +I for writeback, 1 cyc wb latency
DARMInstrMVE.td4906 class MVE_vldst24_base<bit writeback, bit fourregs, bits<2> stage, bits<2> size,
4915 let Inst{21} = writeback;
4929 // A parameter class used to encapsulate all the ways the writeback
4930 // variants of VLD20 and friends differ from the non-writeback ones.
4933 bit writeback = b;
4964 : MVE_vldst24_base<wb.writeback, n.bit0, pat, size, 1,
4973 : MVE_vldst24_base<wb.writeback, n.bit0, pat, size, 0,
4981 // vector lane; writeback or no writeback.
5145 // generate three writeback modes (none, preindex, postindex).
5209 // names shown in the defm, with _pre or _post appended for writeback,
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DARMInstrNEON.td650 // ...with address register writeback:
830 // ...with address register writeback:
903 // ...with address register writeback:
963 // ...with address register writeback:
1113 // ...with address register writeback:
1176 // ...with address register writeback:
1247 // ...with address register writeback:
1325 // ...with address register writeback:
1417 // ...with address register writeback:
1499 // ...with address register writeback:
[all …]
DARMInstrVFP.td199 let Inst{21} = 0; // No writeback
227 let Inst{21} = 0; // No writeback
335 let Inst{21} = 0; // No writeback
DARMScheduleSwift.td93 // Plain load without writeback.
DARMInstrThumb2.td1912 let Inst{21} = 0; // No writeback
1942 let Inst{21} = 0; // No writeback
1981 let Inst{21} = 0; // No writeback
2017 let Inst{21} = 0; // No writeback
DARMInstrInfo.td3293 let Inst{21} = 0; // No writeback
3313 let Inst{21} = 0; // No writeback
3333 let Inst{21} = 0; // No writeback
3353 let Inst{21} = 0; // No writeback
DARMInstrThumb.td830 // There is no non-writeback version of STM for Thumb.
/third_party/e2fsprogs/doc/RelNotes/
Dv1.40.txt38 default data=ordered or data=writeback modes. However, if a block

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