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["gfx10"], 1069 "map": {"at": 1044, "to": "mm"}, 1070 "name": "SQ_WAVE_GPR_ALLOC", 1071 "type_ref": "SQ_WAVE_GPR_ALLOC" 1072 }, 1073 { 1074 "chips": ["gfx10"], 1075 "map": {"at": 1048, "to": "mm"}, 1076 "name": "SQ_WAVE_LDS_ALLOC", 1077 "type_ref": "SQ_WAVE_LDS_ALLOC" 1078 }, 1079 { 1080 "chips": ["gfx10"], 1081 "map": {"at": 1052, "to": "mm"}, 1082 "name": "SQ_WAVE_IB_STS", 1083 "type_ref": "SQ_WAVE_IB_STS" 1084 }, 1085 { 1086 "chips": ["gfx10"], 1087 "map": {"at": 1056, "to": "mm"}, 1088 "name": "SQ_WAVE_PC_LO" 1089 }, 1090 { 1091 "chips": ["gfx10"], 1092 "map": {"at": 1060, "to": "mm"}, 1093 "name": "SQ_WAVE_PC_HI", 1094 "type_ref": "SQ_WAVE_PC_HI" 1095 }, 1096 { 1097 "chips": ["gfx10"], 1098 "map": {"at": 1064, "to": "mm"}, 1099 "name": "SQ_WAVE_INST_DW0" 1100 }, 1101 { 1102 "chips": ["gfx10"], 1103 "map": {"at": 1076, "to": "mm"}, 1104 "name": "SQ_WAVE_IB_DBG1", 1105 "type_ref": "SQ_WAVE_IB_DBG1" 1106 }, 1107 { 1108 "chips": ["gfx10"], 1109 "map": {"at": 1080, "to": "mm"}, 1110 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"name": "SQ_WAVE_TTMP0" 1152 }, 1153 { 1154 "chips": ["gfx10"], 1155 "map": {"at": 2484, "to": "mm"}, 1156 "name": "SQ_WAVE_TTMP1" 1157 }, 1158 { 1159 "chips": ["gfx10"], 1160 "map": {"at": 2488, "to": "mm"}, 1161 "name": "SQ_WAVE_TTMP2" 1162 }, 1163 { 1164 "chips": ["gfx10"], 1165 "map": {"at": 2492, "to": "mm"}, 1166 "name": "SQ_WAVE_TTMP3" 1167 }, 1168 { 1169 "chips": ["gfx10"], 1170 "map": {"at": 2496, "to": "mm"}, 1171 "name": "SQ_WAVE_TTMP4" 1172 }, 1173 { 1174 "chips": ["gfx10"], 1175 "map": {"at": 2500, "to": "mm"}, 1176 "name": "SQ_WAVE_TTMP5" 1177 }, 1178 { 1179 "chips": ["gfx10"], 1180 "map": {"at": 2504, "to": "mm"}, 1181 "name": "SQ_WAVE_TTMP6" 1182 }, 1183 { 1184 "chips": ["gfx10"], 1185 "map": {"at": 2508, "to": "mm"}, 1186 "name": "SQ_WAVE_TTMP7" 1187 }, 1188 { 1189 "chips": ["gfx10"], 1190 "map": {"at": 2512, "to": "mm"}, 1191 "name": "SQ_WAVE_TTMP8" 1192 }, 1193 { 1194 "chips": ["gfx10"], 1195 "map": {"at": 2516, "to": "mm"}, 1196 "name": "SQ_WAVE_TTMP9" 1197 }, 1198 { 1199 "chips": ["gfx10"], 1200 "map": {"at": 2520, "to": "mm"}, 1201 "name": "SQ_WAVE_TTMP10" 1202 }, 1203 { 1204 "chips": ["gfx10"], 1205 "map": {"at": 2524, "to": "mm"}, 1206 "name": "SQ_WAVE_TTMP11" 1207 }, 1208 { 1209 "chips": ["gfx10"], 1210 "map": {"at": 2528, "to": "mm"}, 1211 "name": "SQ_WAVE_TTMP12" 1212 }, 1213 { 1214 "chips": ["gfx10"], 1215 "map": {"at": 2532, "to": "mm"}, 1216 "name": "SQ_WAVE_TTMP13" 1217 }, 1218 { 1219 "chips": ["gfx10"], 1220 "map": {"at": 2536, "to": "mm"}, 1221 "name": "SQ_WAVE_TTMP14" 1222 }, 1223 { 1224 "chips": ["gfx10"], 1225 "map": {"at": 2540, "to": "mm"}, 1226 "name": "SQ_WAVE_TTMP15" 1227 }, 1228 { 1229 "chips": ["gfx10"], 1230 "map": {"at": 2544, "to": "mm"}, 1231 "name": "SQ_WAVE_M0" 1232 }, 1233 { 1234 "chips": ["gfx10"], 1235 "map": {"at": 2552, "to": "mm"}, 1236 "name": "SQ_WAVE_EXEC_LO" 1237 }, 1238 { 1239 "chips": ["gfx10"], 1240 "map": {"at": 2556, "to": "mm"}, 1241 "name": "SQ_WAVE_EXEC_HI" 1242 }, 1243 { 1244 "chips": ["gfx10"], 1245 "map": {"at": 2560, "to": "mm"}, 1246 "name": "SQ_WAVE_FLAT_SCRATCH_LO" 1247 }, 1248 { 1249 "chips": ["gfx10"], 1250 "map": {"at": 2564, "to": "mm"}, 1251 "name": "SQ_WAVE_FLAT_SCRATCH_HI" 1252 }, 1253 { 1254 "chips": ["gfx10"], 1255 "map": {"at": 2568, "to": "mm"}, 1256 "name": "SQ_WAVE_FLAT_XNACK_MASK" 1257 }, 1258 { 1259 "chips": ["gfx10"], 1260 "map": {"at": 32776, "to": "mm"}, 1261 "name": "GRBM_STATUS2", 1262 "type_ref": "GRBM_STATUS2" 1263 }, 1264 { 1265 "chips": ["gfx10"], 1266 "map": {"at": 32784, "to": "mm"}, 1267 "name": "GRBM_STATUS", 1268 "type_ref": "GRBM_STATUS" 1269 }, 1270 { 1271 "chips": ["gfx10"], 1272 "map": {"at": 32788, "to": "mm"}, 1273 "name": "GRBM_STATUS_SE0", 1274 "type_ref": "GRBM_STATUS_SE0" 1275 }, 1276 { 1277 "chips": ["gfx10"], 1278 "map": {"at": 32792, "to": "mm"}, 1279 "name": "GRBM_STATUS_SE1", 1280 "type_ref": "GRBM_STATUS_SE0" 1281 }, 1282 { 1283 "chips": ["gfx10"], 1284 "map": {"at": 32796, "to": "mm"}, 1285 "name": "GRBM_STATUS3", 1286 "type_ref": "GRBM_STATUS3" 1287 }, 1288 { 1289 "chips": ["gfx10"], 1290 "map": {"at": 32824, "to": "mm"}, 1291 "name": "GRBM_STATUS_SE2", 1292 "type_ref": "GRBM_STATUS_SE0" 1293 }, 1294 { 1295 "chips": ["gfx10"], 1296 "map": {"at": 32828, "to": "mm"}, 1297 "name": "GRBM_STATUS_SE3", 1298 "type_ref": "GRBM_STATUS_SE0" 1299 }, 1300 { 1301 "chips": ["gfx10"], 1302 "map": {"at": 33296, "to": "mm"}, 1303 "name": "CP_CPC_STATUS", 1304 "type_ref": "CP_CPC_STATUS" 1305 }, 1306 { 1307 "chips": ["gfx10"], 1308 "map": {"at": 33300, "to": "mm"}, 1309 "name": "CP_CPC_BUSY_STAT", 1310 "type_ref": "CP_CPC_BUSY_STAT" 1311 }, 1312 { 1313 "chips": ["gfx10"], 1314 "map": {"at": 33304, "to": "mm"}, 1315 "name": "CP_CPC_STALLED_STAT1", 1316 "type_ref": "CP_CPC_STALLED_STAT1" 1317 }, 1318 { 1319 "chips": ["gfx10"], 1320 "map": {"at": 33308, "to": "mm"}, 1321 "name": "CP_CPF_STATUS", 1322 "type_ref": "CP_CPF_STATUS" 1323 }, 1324 { 1325 "chips": ["gfx10"], 1326 "map": {"at": 33312, "to": "mm"}, 1327 "name": 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"map": {"at": 33356, "to": "mm"}, 1368 "name": "CP_CPF_BUSY_STAT2", 1369 "type_ref": "CP_CPF_BUSY_STAT2" 1370 }, 1371 { 1372 "chips": ["gfx10"], 1373 "map": {"at": 33436, "to": "mm"}, 1374 "name": "CP_CPC_HALT_HYST_COUNT", 1375 "type_ref": "CP_CPC_HALT_HYST_COUNT" 1376 }, 1377 { 1378 "chips": ["gfx10"], 1379 "map": {"at": 36096, "to": "mm"}, 1380 "name": "SQ_THREAD_TRACE_BUF0_BASE" 1381 }, 1382 { 1383 "chips": ["gfx10"], 1384 "map": {"at": 36100, "to": "mm"}, 1385 "name": "SQ_THREAD_TRACE_BUF0_SIZE", 1386 "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE" 1387 }, 1388 { 1389 "chips": ["gfx10"], 1390 "map": {"at": 36104, "to": "mm"}, 1391 "name": "SQ_THREAD_TRACE_BUF1_BASE" 1392 }, 1393 { 1394 "chips": ["gfx10"], 1395 "map": {"at": 36108, "to": "mm"}, 1396 "name": "SQ_THREAD_TRACE_BUF1_SIZE", 1397 "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE" 1398 }, 1399 { 1400 "chips": ["gfx10"], 1401 "map": {"at": 36112, "to": "mm"}, 1402 "name": "SQ_THREAD_TRACE_WPTR", 1403 "type_ref": "SQ_THREAD_TRACE_WPTR" 1404 }, 1405 { 1406 "chips": ["gfx10"], 1407 "map": {"at": 36116, "to": "mm"}, 1408 "name": "SQ_THREAD_TRACE_MASK", 1409 "type_ref": "SQ_THREAD_TRACE_MASK" 1410 }, 1411 { 1412 "chips": ["gfx10"], 1413 "map": {"at": 36120, "to": "mm"}, 1414 "name": "SQ_THREAD_TRACE_TOKEN_MASK", 1415 "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK" 1416 }, 1417 { 1418 "chips": ["gfx10"], 1419 "map": {"at": 36124, "to": "mm"}, 1420 "name": "SQ_THREAD_TRACE_CTRL", 1421 "type_ref": "SQ_THREAD_TRACE_CTRL" 1422 }, 1423 { 1424 "chips": ["gfx10"], 1425 "map": {"at": 36128, "to": "mm"}, 1426 "name": "SQ_THREAD_TRACE_STATUS", 1427 "type_ref": "SQ_THREAD_TRACE_STATUS" 1428 }, 1429 { 1430 "chips": ["gfx10"], 1431 "map": {"at": 36132, "to": "mm"}, 1432 "name": "SQ_THREAD_TRACE_DROPPED_CNTR" 1433 }, 1434 { 1435 "chips": ["gfx10"], 1436 "map": {"at": 36140, "to": "mm"}, 1437 "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR" 1438 }, 1439 { 1440 "chips": ["gfx10"], 1441 "map": {"at": 36144, "to": "mm"}, 1442 "name": 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"GB_TILE_MODE0" 1483 }, 1484 { 1485 "chips": ["gfx10"], 1486 "map": {"at": 39196, "to": "mm"}, 1487 "name": "GB_TILE_MODE3", 1488 "type_ref": "GB_TILE_MODE0" 1489 }, 1490 { 1491 "chips": ["gfx10"], 1492 "map": {"at": 39200, "to": "mm"}, 1493 "name": "GB_TILE_MODE4", 1494 "type_ref": "GB_TILE_MODE0" 1495 }, 1496 { 1497 "chips": ["gfx10"], 1498 "map": {"at": 39204, "to": "mm"}, 1499 "name": "GB_TILE_MODE5", 1500 "type_ref": "GB_TILE_MODE0" 1501 }, 1502 { 1503 "chips": ["gfx10"], 1504 "map": {"at": 39208, "to": "mm"}, 1505 "name": "GB_TILE_MODE6", 1506 "type_ref": "GB_TILE_MODE0" 1507 }, 1508 { 1509 "chips": ["gfx10"], 1510 "map": {"at": 39212, "to": "mm"}, 1511 "name": "GB_TILE_MODE7", 1512 "type_ref": "GB_TILE_MODE0" 1513 }, 1514 { 1515 "chips": ["gfx10"], 1516 "map": {"at": 39216, "to": "mm"}, 1517 "name": "GB_TILE_MODE8", 1518 "type_ref": "GB_TILE_MODE0" 1519 }, 1520 { 1521 "chips": ["gfx10"], 1522 "map": {"at": 39220, "to": "mm"}, 1523 "name": "GB_TILE_MODE9", 1524 "type_ref": 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"GB_TILE_MODE0" 1609 }, 1610 { 1611 "chips": ["gfx10"], 1612 "map": {"at": 39280, "to": "mm"}, 1613 "name": "GB_TILE_MODE24", 1614 "type_ref": "GB_TILE_MODE0" 1615 }, 1616 { 1617 "chips": ["gfx10"], 1618 "map": {"at": 39284, "to": "mm"}, 1619 "name": "GB_TILE_MODE25", 1620 "type_ref": "GB_TILE_MODE0" 1621 }, 1622 { 1623 "chips": ["gfx10"], 1624 "map": {"at": 39288, "to": "mm"}, 1625 "name": "GB_TILE_MODE26", 1626 "type_ref": "GB_TILE_MODE0" 1627 }, 1628 { 1629 "chips": ["gfx10"], 1630 "map": {"at": 39292, "to": "mm"}, 1631 "name": "GB_TILE_MODE27", 1632 "type_ref": "GB_TILE_MODE0" 1633 }, 1634 { 1635 "chips": ["gfx10"], 1636 "map": {"at": 39296, "to": "mm"}, 1637 "name": "GB_TILE_MODE28", 1638 "type_ref": "GB_TILE_MODE0" 1639 }, 1640 { 1641 "chips": ["gfx10"], 1642 "map": {"at": 39300, "to": "mm"}, 1643 "name": "GB_TILE_MODE29", 1644 "type_ref": "GB_TILE_MODE0" 1645 }, 1646 { 1647 "chips": ["gfx10"], 1648 "map": {"at": 39304, "to": "mm"}, 1649 "name": "GB_TILE_MODE30", 1650 "type_ref": "GB_TILE_MODE0" 1651 }, 1652 { 1653 "chips": ["gfx10"], 1654 "map": {"at": 39308, "to": "mm"}, 1655 "name": "GB_TILE_MODE31", 1656 "type_ref": "GB_TILE_MODE0" 1657 }, 1658 { 1659 "chips": ["gfx10"], 1660 "map": {"at": 39312, "to": "mm"}, 1661 "name": "GB_MACROTILE_MODE0", 1662 "type_ref": "GB_MACROTILE_MODE0" 1663 }, 1664 { 1665 "chips": ["gfx10"], 1666 "map": {"at": 39316, "to": "mm"}, 1667 "name": "GB_MACROTILE_MODE1", 1668 "type_ref": "GB_MACROTILE_MODE0" 1669 }, 1670 { 1671 "chips": ["gfx10"], 1672 "map": {"at": 39320, "to": "mm"}, 1673 "name": "GB_MACROTILE_MODE2", 1674 "type_ref": "GB_MACROTILE_MODE0" 1675 }, 1676 { 1677 "chips": ["gfx10"], 1678 "map": {"at": 39324, "to": "mm"}, 1679 "name": "GB_MACROTILE_MODE3", 1680 "type_ref": "GB_MACROTILE_MODE0" 1681 }, 1682 { 1683 "chips": ["gfx10"], 1684 "map": {"at": 39328, "to": "mm"}, 1685 "name": "GB_MACROTILE_MODE4", 1686 "type_ref": "GB_MACROTILE_MODE0" 1687 }, 1688 { 1689 "chips": ["gfx10"], 1690 "map": {"at": 39332, "to": "mm"}, 1691 "name": "GB_MACROTILE_MODE5", 1692 "type_ref": "GB_MACROTILE_MODE0" 1693 }, 1694 { 1695 "chips": ["gfx10"], 1696 "map": {"at": 39336, "to": "mm"}, 1697 "name": "GB_MACROTILE_MODE6", 1698 "type_ref": "GB_MACROTILE_MODE0" 1699 }, 1700 { 1701 "chips": ["gfx10"], 1702 "map": {"at": 39340, "to": "mm"}, 1703 "name": "GB_MACROTILE_MODE7", 1704 "type_ref": "GB_MACROTILE_MODE0" 1705 }, 1706 { 1707 "chips": ["gfx10"], 1708 "map": {"at": 39344, "to": "mm"}, 1709 "name": "GB_MACROTILE_MODE8", 1710 "type_ref": "GB_MACROTILE_MODE0" 1711 }, 1712 { 1713 "chips": ["gfx10"], 1714 "map": {"at": 39348, "to": "mm"}, 1715 "name": "GB_MACROTILE_MODE9", 1716 "type_ref": "GB_MACROTILE_MODE0" 1717 }, 1718 { 1719 "chips": ["gfx10"], 1720 "map": {"at": 39352, "to": "mm"}, 1721 "name": "GB_MACROTILE_MODE10", 1722 "type_ref": "GB_MACROTILE_MODE0" 1723 }, 1724 { 1725 "chips": ["gfx10"], 1726 "map": {"at": 39356, "to": "mm"}, 1727 "name": "GB_MACROTILE_MODE11", 1728 "type_ref": "GB_MACROTILE_MODE0" 1729 }, 1730 { 1731 "chips": ["gfx10"], 1732 "map": {"at": 39360, "to": "mm"}, 1733 "name": "GB_MACROTILE_MODE12", 1734 "type_ref": "GB_MACROTILE_MODE0" 1735 }, 1736 { 1737 "chips": ["gfx10"], 1738 "map": {"at": 39364, "to": "mm"}, 1739 "name": "GB_MACROTILE_MODE13", 1740 "type_ref": "GB_MACROTILE_MODE0" 1741 }, 1742 { 1743 "chips": ["gfx10"], 1744 "map": {"at": 39368, "to": "mm"}, 1745 "name": "GB_MACROTILE_MODE14", 1746 "type_ref": "GB_MACROTILE_MODE0" 1747 }, 1748 { 1749 "chips": ["gfx10"], 1750 "map": {"at": 39372, "to": "mm"}, 1751 "name": "GB_MACROTILE_MODE15", 1752 "type_ref": "GB_MACROTILE_MODE0" 1753 }, 1754 { 1755 "chips": ["gfx10"], 1756 "map": {"at": 45060, "to": "mm"}, 1757 "name": "SPI_SHADER_PGM_RSRC4_PS", 1758 "type_ref": "SPI_SHADER_PGM_RSRC4_PS" 1759 }, 1760 { 1761 "chips": ["gfx10"], 1762 "map": {"at": 45080, "to": "mm"}, 1763 "name": "SPI_SHADER_PGM_CHKSUM_PS" 1764 }, 1765 { 1766 "chips": ["gfx10"], 1767 "map": {"at": 45084, "to": "mm"}, 1768 "name": "SPI_SHADER_PGM_RSRC3_PS", 1769 "type_ref": "SPI_SHADER_PGM_RSRC3_PS" 1770 }, 1771 { 1772 "chips": ["gfx10"], 1773 "map": {"at": 45088, "to": "mm"}, 1774 "name": "SPI_SHADER_PGM_LO_PS" 1775 }, 1776 { 1777 "chips": ["gfx10"], 1778 "map": {"at": 45092, "to": "mm"}, 1779 "name": "SPI_SHADER_PGM_HI_PS", 1780 "type_ref": "SPI_SHADER_PGM_HI_PS" 1781 }, 1782 { 1783 "chips": ["gfx10"], 1784 "map": {"at": 45096, "to": "mm"}, 1785 "name": "SPI_SHADER_PGM_RSRC1_PS", 1786 "type_ref": "SPI_SHADER_PGM_RSRC1_PS" 1787 }, 1788 { 1789 "chips": ["gfx10"], 1790 "map": {"at": 45100, "to": "mm"}, 1791 "name": "SPI_SHADER_PGM_RSRC2_PS", 1792 "type_ref": "SPI_SHADER_PGM_RSRC2_PS" 1793 }, 1794 { 1795 "chips": ["gfx10"], 1796 "map": {"at": 45104, "to": "mm"}, 1797 "name": "SPI_SHADER_USER_DATA_PS_0" 1798 }, 1799 { 1800 "chips": ["gfx10"], 1801 "map": {"at": 45108, "to": "mm"}, 1802 "name": "SPI_SHADER_USER_DATA_PS_1" 1803 }, 1804 { 1805 "chips": ["gfx10"], 1806 "map": {"at": 45112, "to": "mm"}, 1807 "name": "SPI_SHADER_USER_DATA_PS_2" 1808 }, 1809 { 1810 "chips": ["gfx10"], 1811 "map": {"at": 45116, "to": "mm"}, 1812 "name": "SPI_SHADER_USER_DATA_PS_3" 1813 }, 1814 { 1815 "chips": ["gfx10"], 1816 "map": {"at": 45120, "to": "mm"}, 1817 "name": "SPI_SHADER_USER_DATA_PS_4" 1818 }, 1819 { 1820 "chips": ["gfx10"], 1821 "map": {"at": 45124, "to": "mm"}, 1822 "name": "SPI_SHADER_USER_DATA_PS_5" 1823 }, 1824 { 1825 "chips": ["gfx10"], 1826 "map": {"at": 45128, "to": "mm"}, 1827 "name": "SPI_SHADER_USER_DATA_PS_6" 1828 }, 1829 { 1830 "chips": ["gfx10"], 1831 "map": {"at": 45132, "to": "mm"}, 1832 "name": "SPI_SHADER_USER_DATA_PS_7" 1833 }, 1834 { 1835 "chips": ["gfx10"], 1836 "map": {"at": 45136, "to": "mm"}, 1837 "name": "SPI_SHADER_USER_DATA_PS_8" 1838 }, 1839 { 1840 "chips": ["gfx10"], 1841 "map": {"at": 45140, "to": "mm"}, 1842 "name": "SPI_SHADER_USER_DATA_PS_9" 1843 }, 1844 { 1845 "chips": ["gfx10"], 1846 "map": {"at": 45144, "to": "mm"}, 1847 "name": "SPI_SHADER_USER_DATA_PS_10" 1848 }, 1849 { 1850 "chips": ["gfx10"], 1851 "map": {"at": 45148, "to": "mm"}, 1852 "name": "SPI_SHADER_USER_DATA_PS_11" 1853 }, 1854 { 1855 "chips": ["gfx10"], 1856 "map": {"at": 45152, "to": "mm"}, 1857 "name": "SPI_SHADER_USER_DATA_PS_12" 1858 }, 1859 { 1860 "chips": ["gfx10"], 1861 "map": {"at": 45156, "to": "mm"}, 1862 "name": "SPI_SHADER_USER_DATA_PS_13" 1863 }, 1864 { 1865 "chips": ["gfx10"], 1866 "map": {"at": 45160, "to": "mm"}, 1867 "name": "SPI_SHADER_USER_DATA_PS_14" 1868 }, 1869 { 1870 "chips": ["gfx10"], 1871 "map": {"at": 45164, "to": "mm"}, 1872 "name": "SPI_SHADER_USER_DATA_PS_15" 1873 }, 1874 { 1875 "chips": ["gfx10"], 1876 "map": {"at": 45168, "to": "mm"}, 1877 "name": "SPI_SHADER_USER_DATA_PS_16" 1878 }, 1879 { 1880 "chips": ["gfx10"], 1881 "map": {"at": 45172, "to": "mm"}, 1882 "name": "SPI_SHADER_USER_DATA_PS_17" 1883 }, 1884 { 1885 "chips": ["gfx10"], 1886 "map": {"at": 45176, "to": "mm"}, 1887 "name": "SPI_SHADER_USER_DATA_PS_18" 1888 }, 1889 { 1890 "chips": ["gfx10"], 1891 "map": {"at": 45180, "to": "mm"}, 1892 "name": "SPI_SHADER_USER_DATA_PS_19" 1893 }, 1894 { 1895 "chips": ["gfx10"], 1896 "map": {"at": 45184, "to": "mm"}, 1897 "name": "SPI_SHADER_USER_DATA_PS_20" 1898 }, 1899 { 1900 "chips": ["gfx10"], 1901 "map": {"at": 45188, "to": "mm"}, 1902 "name": "SPI_SHADER_USER_DATA_PS_21" 1903 }, 1904 { 1905 "chips": ["gfx10"], 1906 "map": {"at": 45192, "to": "mm"}, 1907 "name": "SPI_SHADER_USER_DATA_PS_22" 1908 }, 1909 { 1910 "chips": ["gfx10"], 1911 "map": {"at": 45196, "to": "mm"}, 1912 "name": "SPI_SHADER_USER_DATA_PS_23" 1913 }, 1914 { 1915 "chips": ["gfx10"], 1916 "map": {"at": 45200, "to": "mm"}, 1917 "name": "SPI_SHADER_USER_DATA_PS_24" 1918 }, 1919 { 1920 "chips": ["gfx10"], 1921 "map": {"at": 45204, "to": "mm"}, 1922 "name": "SPI_SHADER_USER_DATA_PS_25" 1923 }, 1924 { 1925 "chips": ["gfx10"], 1926 "map": {"at": 45208, "to": "mm"}, 1927 "name": "SPI_SHADER_USER_DATA_PS_26" 1928 }, 1929 { 1930 "chips": ["gfx10"], 1931 "map": {"at": 45212, "to": "mm"}, 1932 "name": "SPI_SHADER_USER_DATA_PS_27" 1933 }, 1934 { 1935 "chips": ["gfx10"], 1936 "map": {"at": 45216, "to": "mm"}, 1937 "name": "SPI_SHADER_USER_DATA_PS_28" 1938 }, 1939 { 1940 "chips": ["gfx10"], 1941 "map": {"at": 45220, "to": "mm"}, 1942 "name": "SPI_SHADER_USER_DATA_PS_29" 1943 }, 1944 { 1945 "chips": ["gfx10"], 1946 "map": {"at": 45224, "to": "mm"}, 1947 "name": "SPI_SHADER_USER_DATA_PS_30" 1948 }, 1949 { 1950 "chips": ["gfx10"], 1951 "map": {"at": 45228, "to": "mm"}, 1952 "name": "SPI_SHADER_USER_DATA_PS_31" 1953 }, 1954 { 1955 "chips": ["gfx10"], 1956 "map": {"at": 45248, "to": "mm"}, 1957 "name": "SPI_SHADER_REQ_CTRL_PS", 1958 "type_ref": "SPI_SHADER_REQ_CTRL_PS" 1959 }, 1960 { 1961 "chips": ["gfx10"], 1962 "map": {"at": 45252, "to": "mm"}, 1963 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS", 1964 "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS" 1965 }, 1966 { 1967 "chips": ["gfx10"], 1968 "map": {"at": 45256, "to": "mm"}, 1969 "name": "SPI_SHADER_USER_ACCUM_PS_0", 1970 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 1971 }, 1972 { 1973 "chips": ["gfx10"], 1974 "map": {"at": 45260, "to": "mm"}, 1975 "name": "SPI_SHADER_USER_ACCUM_PS_1", 1976 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 1977 }, 1978 { 1979 "chips": ["gfx10"], 1980 "map": {"at": 45264, "to": "mm"}, 1981 "name": "SPI_SHADER_USER_ACCUM_PS_2", 1982 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 1983 }, 1984 { 1985 "chips": ["gfx10"], 1986 "map": {"at": 45268, "to": "mm"}, 1987 "name": "SPI_SHADER_USER_ACCUM_PS_3", 1988 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 1989 }, 1990 { 1991 "chips": ["gfx10"], 1992 "map": {"at": 45316, "to": "mm"}, 1993 "name": "SPI_SHADER_PGM_RSRC4_VS", 1994 "type_ref": "SPI_SHADER_PGM_RSRC4_PS" 1995 }, 1996 { 1997 "chips": ["gfx10"], 1998 "map": {"at": 45332, "to": "mm"}, 1999 "name": "SPI_SHADER_PGM_CHKSUM_VS" 2000 }, 2001 { 2002 "chips": ["gfx10"], 2003 "map": {"at": 45336, "to": "mm"}, 2004 "name": "SPI_SHADER_PGM_RSRC3_VS", 2005 "type_ref": "SPI_SHADER_PGM_RSRC3_PS" 2006 }, 2007 { 2008 "chips": ["gfx10"], 2009 "map": {"at": 45340, "to": "mm"}, 2010 "name": "SPI_SHADER_LATE_ALLOC_VS", 2011 "type_ref": "SPI_SHADER_LATE_ALLOC_VS" 2012 }, 2013 { 2014 "chips": ["gfx10"], 2015 "map": {"at": 45344, "to": "mm"}, 2016 "name": "SPI_SHADER_PGM_LO_VS" 2017 }, 2018 { 2019 "chips": ["gfx10"], 2020 "map": {"at": 45348, "to": "mm"}, 2021 "name": "SPI_SHADER_PGM_HI_VS", 2022 "type_ref": "SPI_SHADER_PGM_HI_PS" 2023 }, 2024 { 2025 "chips": ["gfx10"], 2026 "map": {"at": 45352, "to": "mm"}, 2027 "name": "SPI_SHADER_PGM_RSRC1_VS", 2028 "type_ref": "SPI_SHADER_PGM_RSRC1_VS" 2029 }, 2030 { 2031 "chips": ["gfx10"], 2032 "map": {"at": 45356, "to": "mm"}, 2033 "name": "SPI_SHADER_PGM_RSRC2_VS", 2034 "type_ref": "SPI_SHADER_PGM_RSRC2_VS" 2035 }, 2036 { 2037 "chips": ["gfx10"], 2038 "map": {"at": 45360, "to": "mm"}, 2039 "name": "SPI_SHADER_USER_DATA_VS_0" 2040 }, 2041 { 2042 "chips": ["gfx10"], 2043 "map": {"at": 45364, "to": "mm"}, 2044 "name": "SPI_SHADER_USER_DATA_VS_1" 2045 }, 2046 { 2047 "chips": ["gfx10"], 2048 "map": {"at": 45368, "to": "mm"}, 2049 "name": "SPI_SHADER_USER_DATA_VS_2" 2050 }, 2051 { 2052 "chips": ["gfx10"], 2053 "map": {"at": 45372, "to": "mm"}, 2054 "name": "SPI_SHADER_USER_DATA_VS_3" 2055 }, 2056 { 2057 "chips": ["gfx10"], 2058 "map": {"at": 45376, "to": "mm"}, 2059 "name": "SPI_SHADER_USER_DATA_VS_4" 2060 }, 2061 { 2062 "chips": ["gfx10"], 2063 "map": {"at": 45380, "to": "mm"}, 2064 "name": "SPI_SHADER_USER_DATA_VS_5" 2065 }, 2066 { 2067 "chips": ["gfx10"], 2068 "map": {"at": 45384, "to": "mm"}, 2069 "name": "SPI_SHADER_USER_DATA_VS_6" 2070 }, 2071 { 2072 "chips": ["gfx10"], 2073 "map": {"at": 45388, "to": "mm"}, 2074 "name": "SPI_SHADER_USER_DATA_VS_7" 2075 }, 2076 { 2077 "chips": ["gfx10"], 2078 "map": {"at": 45392, "to": "mm"}, 2079 "name": "SPI_SHADER_USER_DATA_VS_8" 2080 }, 2081 { 2082 "chips": ["gfx10"], 2083 "map": {"at": 45396, "to": "mm"}, 2084 "name": "SPI_SHADER_USER_DATA_VS_9" 2085 }, 2086 { 2087 "chips": ["gfx10"], 2088 "map": {"at": 45400, "to": "mm"}, 2089 "name": "SPI_SHADER_USER_DATA_VS_10" 2090 }, 2091 { 2092 "chips": ["gfx10"], 2093 "map": {"at": 45404, "to": "mm"}, 2094 "name": "SPI_SHADER_USER_DATA_VS_11" 2095 }, 2096 { 2097 "chips": ["gfx10"], 2098 "map": {"at": 45408, "to": "mm"}, 2099 "name": "SPI_SHADER_USER_DATA_VS_12" 2100 }, 2101 { 2102 "chips": ["gfx10"], 2103 "map": {"at": 45412, "to": "mm"}, 2104 "name": "SPI_SHADER_USER_DATA_VS_13" 2105 }, 2106 { 2107 "chips": ["gfx10"], 2108 "map": {"at": 45416, "to": "mm"}, 2109 "name": "SPI_SHADER_USER_DATA_VS_14" 2110 }, 2111 { 2112 "chips": ["gfx10"], 2113 "map": {"at": 45420, "to": "mm"}, 2114 "name": "SPI_SHADER_USER_DATA_VS_15" 2115 }, 2116 { 2117 "chips": ["gfx10"], 2118 "map": {"at": 45424, "to": "mm"}, 2119 "name": "SPI_SHADER_USER_DATA_VS_16" 2120 }, 2121 { 2122 "chips": ["gfx10"], 2123 "map": {"at": 45428, "to": "mm"}, 2124 "name": "SPI_SHADER_USER_DATA_VS_17" 2125 }, 2126 { 2127 "chips": ["gfx10"], 2128 "map": {"at": 45432, "to": "mm"}, 2129 "name": "SPI_SHADER_USER_DATA_VS_18" 2130 }, 2131 { 2132 "chips": ["gfx10"], 2133 "map": {"at": 45436, "to": "mm"}, 2134 "name": "SPI_SHADER_USER_DATA_VS_19" 2135 }, 2136 { 2137 "chips": ["gfx10"], 2138 "map": {"at": 45440, "to": "mm"}, 2139 "name": "SPI_SHADER_USER_DATA_VS_20" 2140 }, 2141 { 2142 "chips": ["gfx10"], 2143 "map": {"at": 45444, "to": "mm"}, 2144 "name": "SPI_SHADER_USER_DATA_VS_21" 2145 }, 2146 { 2147 "chips": ["gfx10"], 2148 "map": {"at": 45448, "to": "mm"}, 2149 "name": "SPI_SHADER_USER_DATA_VS_22" 2150 }, 2151 { 2152 "chips": ["gfx10"], 2153 "map": {"at": 45452, "to": "mm"}, 2154 "name": "SPI_SHADER_USER_DATA_VS_23" 2155 }, 2156 { 2157 "chips": ["gfx10"], 2158 "map": {"at": 45456, "to": "mm"}, 2159 "name": "SPI_SHADER_USER_DATA_VS_24" 2160 }, 2161 { 2162 "chips": ["gfx10"], 2163 "map": {"at": 45460, "to": "mm"}, 2164 "name": "SPI_SHADER_USER_DATA_VS_25" 2165 }, 2166 { 2167 "chips": ["gfx10"], 2168 "map": {"at": 45464, "to": "mm"}, 2169 "name": "SPI_SHADER_USER_DATA_VS_26" 2170 }, 2171 { 2172 "chips": ["gfx10"], 2173 "map": {"at": 45468, "to": "mm"}, 2174 "name": "SPI_SHADER_USER_DATA_VS_27" 2175 }, 2176 { 2177 "chips": ["gfx10"], 2178 "map": {"at": 45472, "to": "mm"}, 2179 "name": "SPI_SHADER_USER_DATA_VS_28" 2180 }, 2181 { 2182 "chips": ["gfx10"], 2183 "map": {"at": 45476, "to": "mm"}, 2184 "name": "SPI_SHADER_USER_DATA_VS_29" 2185 }, 2186 { 2187 "chips": ["gfx10"], 2188 "map": {"at": 45480, "to": "mm"}, 2189 "name": "SPI_SHADER_USER_DATA_VS_30" 2190 }, 2191 { 2192 "chips": ["gfx10"], 2193 "map": {"at": 45484, "to": "mm"}, 2194 "name": "SPI_SHADER_USER_DATA_VS_31" 2195 }, 2196 { 2197 "chips": ["gfx10"], 2198 "map": {"at": 45504, "to": "mm"}, 2199 "name": "SPI_SHADER_REQ_CTRL_VS", 2200 "type_ref": "SPI_SHADER_REQ_CTRL_PS" 2201 }, 2202 { 2203 "chips": ["gfx10"], 2204 "map": {"at": 45508, "to": "mm"}, 2205 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_VS", 2206 "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS" 2207 }, 2208 { 2209 "chips": ["gfx10"], 2210 "map": {"at": 45512, "to": "mm"}, 2211 "name": "SPI_SHADER_USER_ACCUM_VS_0", 2212 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2213 }, 2214 { 2215 "chips": ["gfx10"], 2216 "map": {"at": 45516, "to": "mm"}, 2217 "name": "SPI_SHADER_USER_ACCUM_VS_1", 2218 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2219 }, 2220 { 2221 "chips": ["gfx10"], 2222 "map": {"at": 45520, "to": "mm"}, 2223 "name": "SPI_SHADER_USER_ACCUM_VS_2", 2224 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2225 }, 2226 { 2227 "chips": ["gfx10"], 2228 "map": {"at": 45524, "to": "mm"}, 2229 "name": "SPI_SHADER_USER_ACCUM_VS_3", 2230 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2231 }, 2232 { 2233 "chips": ["gfx10"], 2234 "map": {"at": 45548, "to": "mm"}, 2235 "name": "SPI_SHADER_PGM_RSRC2_GS_VS", 2236 "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS" 2237 }, 2238 { 2239 "chips": ["gfx10"], 2240 "map": {"at": 45552, "to": "mm"}, 2241 "name": "SPI_SHADER_PGM_RSRC2_ES_VS", 2242 "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS" 2243 }, 2244 { 2245 "chips": ["gfx10"], 2246 "map": {"at": 45556, "to": "mm"}, 2247 "name": "SPI_SHADER_PGM_RSRC2_LS_VS", 2248 "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS" 2249 }, 2250 { 2251 "chips": ["gfx10"], 2252 "map": {"at": 45568, "to": "mm"}, 2253 "name": "SPI_SHADER_PGM_CHKSUM_GS" 2254 }, 2255 { 2256 "chips": ["gfx10"], 2257 "map": {"at": 45572, "to": "mm"}, 2258 "name": "SPI_SHADER_PGM_RSRC4_GS", 2259 "type_ref": "SPI_SHADER_PGM_RSRC4_GS" 2260 }, 2261 { 2262 "chips": ["gfx10"], 2263 "map": {"at": 45576, "to": "mm"}, 2264 "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS" 2265 }, 2266 { 2267 "chips": ["gfx10"], 2268 "map": {"at": 45580, "to": "mm"}, 2269 "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS" 2270 }, 2271 { 2272 "chips": ["gfx10"], 2273 "map": {"at": 45584, "to": "mm"}, 2274 "name": "SPI_SHADER_PGM_LO_ES_GS" 2275 }, 2276 { 2277 "chips": ["gfx10"], 2278 "map": {"at": 45588, "to": "mm"}, 2279 "name": "SPI_SHADER_PGM_HI_ES_GS", 2280 "type_ref": "SPI_SHADER_PGM_HI_PS" 2281 }, 2282 { 2283 "chips": ["gfx10"], 2284 "map": {"at": 45596, "to": "mm"}, 2285 "name": "SPI_SHADER_PGM_RSRC3_GS", 2286 "type_ref": "SPI_SHADER_PGM_RSRC3_GS" 2287 }, 2288 { 2289 "chips": ["gfx10"], 2290 "map": {"at": 45600, "to": "mm"}, 2291 "name": "SPI_SHADER_PGM_LO_GS" 2292 }, 2293 { 2294 "chips": ["gfx10"], 2295 "map": {"at": 45604, "to": "mm"}, 2296 "name": "SPI_SHADER_PGM_HI_GS", 2297 "type_ref": "SPI_SHADER_PGM_HI_PS" 2298 }, 2299 { 2300 "chips": ["gfx10"], 2301 "map": {"at": 45608, "to": "mm"}, 2302 "name": "SPI_SHADER_PGM_RSRC1_GS", 2303 "type_ref": "SPI_SHADER_PGM_RSRC1_GS" 2304 }, 2305 { 2306 "chips": ["gfx10"], 2307 "map": {"at": 45612, "to": "mm"}, 2308 "name": "SPI_SHADER_PGM_RSRC2_GS", 2309 "type_ref": "SPI_SHADER_PGM_RSRC2_GS" 2310 }, 2311 { 2312 "chips": ["gfx10"], 2313 "map": {"at": 45616, "to": "mm"}, 2314 "name": "SPI_SHADER_USER_DATA_GS_0" 2315 }, 2316 { 2317 "chips": ["gfx10"], 2318 "map": {"at": 45620, "to": "mm"}, 2319 "name": "SPI_SHADER_USER_DATA_GS_1" 2320 }, 2321 { 2322 "chips": ["gfx10"], 2323 "map": {"at": 45624, "to": "mm"}, 2324 "name": "SPI_SHADER_USER_DATA_GS_2" 2325 }, 2326 { 2327 "chips": ["gfx10"], 2328 "map": {"at": 45628, "to": "mm"}, 2329 "name": "SPI_SHADER_USER_DATA_GS_3" 2330 }, 2331 { 2332 "chips": ["gfx10"], 2333 "map": {"at": 45632, "to": "mm"}, 2334 "name": "SPI_SHADER_USER_DATA_GS_4" 2335 }, 2336 { 2337 "chips": ["gfx10"], 2338 "map": {"at": 45636, "to": "mm"}, 2339 "name": "SPI_SHADER_USER_DATA_GS_5" 2340 }, 2341 { 2342 "chips": ["gfx10"], 2343 "map": {"at": 45640, "to": "mm"}, 2344 "name": "SPI_SHADER_USER_DATA_GS_6" 2345 }, 2346 { 2347 "chips": ["gfx10"], 2348 "map": {"at": 45644, "to": "mm"}, 2349 "name": "SPI_SHADER_USER_DATA_GS_7" 2350 }, 2351 { 2352 "chips": ["gfx10"], 2353 "map": {"at": 45648, "to": "mm"}, 2354 "name": "SPI_SHADER_USER_DATA_GS_8" 2355 }, 2356 { 2357 "chips": ["gfx10"], 2358 "map": {"at": 45652, "to": "mm"}, 2359 "name": "SPI_SHADER_USER_DATA_GS_9" 2360 }, 2361 { 2362 "chips": ["gfx10"], 2363 "map": {"at": 45656, "to": "mm"}, 2364 "name": "SPI_SHADER_USER_DATA_GS_10" 2365 }, 2366 { 2367 "chips": ["gfx10"], 2368 "map": {"at": 45660, "to": "mm"}, 2369 "name": "SPI_SHADER_USER_DATA_GS_11" 2370 }, 2371 { 2372 "chips": ["gfx10"], 2373 "map": {"at": 45664, "to": "mm"}, 2374 "name": "SPI_SHADER_USER_DATA_GS_12" 2375 }, 2376 { 2377 "chips": ["gfx10"], 2378 "map": {"at": 45668, "to": "mm"}, 2379 "name": "SPI_SHADER_USER_DATA_GS_13" 2380 }, 2381 { 2382 "chips": ["gfx10"], 2383 "map": {"at": 45672, "to": "mm"}, 2384 "name": "SPI_SHADER_USER_DATA_GS_14" 2385 }, 2386 { 2387 "chips": ["gfx10"], 2388 "map": {"at": 45676, "to": "mm"}, 2389 "name": "SPI_SHADER_USER_DATA_GS_15" 2390 }, 2391 { 2392 "chips": ["gfx10"], 2393 "map": {"at": 45680, "to": "mm"}, 2394 "name": "SPI_SHADER_USER_DATA_GS_16" 2395 }, 2396 { 2397 "chips": ["gfx10"], 2398 "map": {"at": 45684, "to": "mm"}, 2399 "name": "SPI_SHADER_USER_DATA_GS_17" 2400 }, 2401 { 2402 "chips": ["gfx10"], 2403 "map": {"at": 45688, "to": "mm"}, 2404 "name": "SPI_SHADER_USER_DATA_GS_18" 2405 }, 2406 { 2407 "chips": ["gfx10"], 2408 "map": {"at": 45692, "to": "mm"}, 2409 "name": "SPI_SHADER_USER_DATA_GS_19" 2410 }, 2411 { 2412 "chips": ["gfx10"], 2413 "map": {"at": 45696, "to": "mm"}, 2414 "name": "SPI_SHADER_USER_DATA_GS_20" 2415 }, 2416 { 2417 "chips": ["gfx10"], 2418 "map": {"at": 45700, "to": "mm"}, 2419 "name": "SPI_SHADER_USER_DATA_GS_21" 2420 }, 2421 { 2422 "chips": ["gfx10"], 2423 "map": {"at": 45704, "to": "mm"}, 2424 "name": "SPI_SHADER_USER_DATA_GS_22" 2425 }, 2426 { 2427 "chips": ["gfx10"], 2428 "map": {"at": 45708, "to": "mm"}, 2429 "name": "SPI_SHADER_USER_DATA_GS_23" 2430 }, 2431 { 2432 "chips": ["gfx10"], 2433 "map": {"at": 45712, "to": "mm"}, 2434 "name": "SPI_SHADER_USER_DATA_GS_24" 2435 }, 2436 { 2437 "chips": ["gfx10"], 2438 "map": {"at": 45716, "to": "mm"}, 2439 "name": "SPI_SHADER_USER_DATA_GS_25" 2440 }, 2441 { 2442 "chips": ["gfx10"], 2443 "map": {"at": 45720, "to": "mm"}, 2444 "name": "SPI_SHADER_USER_DATA_GS_26" 2445 }, 2446 { 2447 "chips": ["gfx10"], 2448 "map": {"at": 45724, "to": "mm"}, 2449 "name": "SPI_SHADER_USER_DATA_GS_27" 2450 }, 2451 { 2452 "chips": ["gfx10"], 2453 "map": {"at": 45728, "to": "mm"}, 2454 "name": "SPI_SHADER_USER_DATA_GS_28" 2455 }, 2456 { 2457 "chips": ["gfx10"], 2458 "map": {"at": 45732, "to": "mm"}, 2459 "name": "SPI_SHADER_USER_DATA_GS_29" 2460 }, 2461 { 2462 "chips": ["gfx10"], 2463 "map": {"at": 45736, "to": "mm"}, 2464 "name": "SPI_SHADER_USER_DATA_GS_30" 2465 }, 2466 { 2467 "chips": ["gfx10"], 2468 "map": {"at": 45740, "to": "mm"}, 2469 "name": "SPI_SHADER_USER_DATA_GS_31" 2470 }, 2471 { 2472 "chips": ["gfx10"], 2473 "map": {"at": 45760, "to": "mm"}, 2474 "name": "SPI_SHADER_REQ_CTRL_ESGS", 2475 "type_ref": "SPI_SHADER_REQ_CTRL_PS" 2476 }, 2477 { 2478 "chips": ["gfx10"], 2479 "map": {"at": 45764, "to": "mm"}, 2480 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS", 2481 "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS" 2482 }, 2483 { 2484 "chips": ["gfx10"], 2485 "map": {"at": 45768, "to": "mm"}, 2486 "name": "SPI_SHADER_USER_ACCUM_ESGS_0", 2487 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2488 }, 2489 { 2490 "chips": ["gfx10"], 2491 "map": {"at": 45772, "to": "mm"}, 2492 "name": "SPI_SHADER_USER_ACCUM_ESGS_1", 2493 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2494 }, 2495 { 2496 "chips": ["gfx10"], 2497 "map": {"at": 45776, "to": "mm"}, 2498 "name": "SPI_SHADER_USER_ACCUM_ESGS_2", 2499 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2500 }, 2501 { 2502 "chips": ["gfx10"], 2503 "map": {"at": 45780, "to": "mm"}, 2504 "name": "SPI_SHADER_USER_ACCUM_ESGS_3", 2505 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2506 }, 2507 { 2508 "chips": ["gfx10"], 2509 "map": {"at": 45808, "to": "mm"}, 2510 "name": "SPI_SHADER_PGM_RSRC2_ES_GS", 2511 "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS" 2512 }, 2513 { 2514 "chips": ["gfx10"], 2515 "map": {"at": 45852, "to": "mm"}, 2516 "name": "SPI_SHADER_PGM_RSRC3_ES", 2517 "type_ref": "SPI_SHADER_PGM_RSRC3_GS" 2518 }, 2519 { 2520 "chips": ["gfx10"], 2521 "map": {"at": 45856, "to": "mm"}, 2522 "name": "SPI_SHADER_PGM_LO_ES" 2523 }, 2524 { 2525 "chips": ["gfx10"], 2526 "map": {"at": 45860, "to": "mm"}, 2527 "name": "SPI_SHADER_PGM_HI_ES", 2528 "type_ref": "SPI_SHADER_PGM_HI_PS" 2529 }, 2530 { 2531 "chips": ["gfx10"], 2532 "map": {"at": 45864, "to": "mm"}, 2533 "name": "SPI_SHADER_PGM_RSRC1_ES", 2534 "type_ref": "SPI_SHADER_PGM_RSRC1_ES" 2535 }, 2536 { 2537 "chips": ["gfx10"], 2538 "map": {"at": 45868, "to": "mm"}, 2539 "name": "SPI_SHADER_PGM_RSRC2_ES", 2540 "type_ref": "SPI_SHADER_PGM_RSRC2_ES_VS" 2541 }, 2542 { 2543 "chips": ["gfx10"], 2544 "map": {"at": 45872, "to": "mm"}, 2545 "name": "SPI_SHADER_USER_DATA_ES_0" 2546 }, 2547 { 2548 "chips": ["gfx10"], 2549 "map": {"at": 45876, "to": "mm"}, 2550 "name": "SPI_SHADER_USER_DATA_ES_1" 2551 }, 2552 { 2553 "chips": ["gfx10"], 2554 "map": {"at": 45880, "to": "mm"}, 2555 "name": "SPI_SHADER_USER_DATA_ES_2" 2556 }, 2557 { 2558 "chips": ["gfx10"], 2559 "map": {"at": 45884, "to": "mm"}, 2560 "name": "SPI_SHADER_USER_DATA_ES_3" 2561 }, 2562 { 2563 "chips": ["gfx10"], 2564 "map": {"at": 45888, "to": "mm"}, 2565 "name": "SPI_SHADER_USER_DATA_ES_4" 2566 }, 2567 { 2568 "chips": ["gfx10"], 2569 "map": {"at": 45892, "to": "mm"}, 2570 "name": "SPI_SHADER_USER_DATA_ES_5" 2571 }, 2572 { 2573 "chips": ["gfx10"], 2574 "map": {"at": 45896, "to": "mm"}, 2575 "name": "SPI_SHADER_USER_DATA_ES_6" 2576 }, 2577 { 2578 "chips": ["gfx10"], 2579 "map": {"at": 45900, "to": "mm"}, 2580 "name": "SPI_SHADER_USER_DATA_ES_7" 2581 }, 2582 { 2583 "chips": ["gfx10"], 2584 "map": {"at": 45904, "to": "mm"}, 2585 "name": "SPI_SHADER_USER_DATA_ES_8" 2586 }, 2587 { 2588 "chips": ["gfx10"], 2589 "map": {"at": 45908, "to": "mm"}, 2590 "name": "SPI_SHADER_USER_DATA_ES_9" 2591 }, 2592 { 2593 "chips": ["gfx10"], 2594 "map": {"at": 45912, "to": "mm"}, 2595 "name": "SPI_SHADER_USER_DATA_ES_10" 2596 }, 2597 { 2598 "chips": ["gfx10"], 2599 "map": {"at": 45916, "to": "mm"}, 2600 "name": "SPI_SHADER_USER_DATA_ES_11" 2601 }, 2602 { 2603 "chips": ["gfx10"], 2604 "map": {"at": 45920, "to": "mm"}, 2605 "name": "SPI_SHADER_USER_DATA_ES_12" 2606 }, 2607 { 2608 "chips": ["gfx10"], 2609 "map": {"at": 45924, "to": "mm"}, 2610 "name": "SPI_SHADER_USER_DATA_ES_13" 2611 }, 2612 { 2613 "chips": ["gfx10"], 2614 "map": {"at": 45928, "to": "mm"}, 2615 "name": "SPI_SHADER_USER_DATA_ES_14" 2616 }, 2617 { 2618 "chips": ["gfx10"], 2619 "map": {"at": 45932, "to": "mm"}, 2620 "name": "SPI_SHADER_USER_DATA_ES_15" 2621 }, 2622 { 2623 "chips": ["gfx10"], 2624 "map": {"at": 46068, "to": "mm"}, 2625 "name": "SPI_SHADER_PGM_RSRC2_LS_ES", 2626 "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS" 2627 }, 2628 { 2629 "chips": ["gfx10"], 2630 "map": {"at": 46080, "to": "mm"}, 2631 "name": "SPI_SHADER_PGM_CHKSUM_HS" 2632 }, 2633 { 2634 "chips": ["gfx10"], 2635 "map": {"at": 46084, "to": "mm"}, 2636 "name": "SPI_SHADER_PGM_RSRC4_HS", 2637 "type_ref": "SPI_SHADER_PGM_RSRC4_PS" 2638 }, 2639 { 2640 "chips": ["gfx10"], 2641 "map": {"at": 46088, "to": "mm"}, 2642 "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS" 2643 }, 2644 { 2645 "chips": ["gfx10"], 2646 "map": {"at": 46092, "to": "mm"}, 2647 "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS" 2648 }, 2649 { 2650 "chips": ["gfx10"], 2651 "map": {"at": 46096, "to": "mm"}, 2652 "name": "SPI_SHADER_PGM_LO_LS_HS" 2653 }, 2654 { 2655 "chips": ["gfx10"], 2656 "map": {"at": 46100, "to": "mm"}, 2657 "name": "SPI_SHADER_PGM_HI_LS_HS", 2658 "type_ref": "SPI_SHADER_PGM_HI_PS" 2659 }, 2660 { 2661 "chips": ["gfx10"], 2662 "map": {"at": 46108, "to": "mm"}, 2663 "name": "SPI_SHADER_PGM_RSRC3_HS", 2664 "type_ref": "SPI_SHADER_PGM_RSRC3_HS" 2665 }, 2666 { 2667 "chips": ["gfx10"], 2668 "map": {"at": 46112, "to": "mm"}, 2669 "name": "SPI_SHADER_PGM_LO_HS" 2670 }, 2671 { 2672 "chips": ["gfx10"], 2673 "map": {"at": 46116, "to": "mm"}, 2674 "name": "SPI_SHADER_PGM_HI_HS", 2675 "type_ref": "SPI_SHADER_PGM_HI_PS" 2676 }, 2677 { 2678 "chips": ["gfx10"], 2679 "map": {"at": 46120, "to": "mm"}, 2680 "name": "SPI_SHADER_PGM_RSRC1_HS", 2681 "type_ref": "SPI_SHADER_PGM_RSRC1_HS" 2682 }, 2683 { 2684 "chips": ["gfx10"], 2685 "map": {"at": 46124, "to": "mm"}, 2686 "name": "SPI_SHADER_PGM_RSRC2_HS", 2687 "type_ref": "SPI_SHADER_PGM_RSRC2_HS" 2688 }, 2689 { 2690 "chips": ["gfx10"], 2691 "map": {"at": 46128, "to": "mm"}, 2692 "name": "SPI_SHADER_USER_DATA_HS_0" 2693 }, 2694 { 2695 "chips": ["gfx10"], 2696 "map": {"at": 46132, "to": "mm"}, 2697 "name": "SPI_SHADER_USER_DATA_HS_1" 2698 }, 2699 { 2700 "chips": ["gfx10"], 2701 "map": {"at": 46136, "to": "mm"}, 2702 "name": "SPI_SHADER_USER_DATA_HS_2" 2703 }, 2704 { 2705 "chips": ["gfx10"], 2706 "map": {"at": 46140, "to": "mm"}, 2707 "name": "SPI_SHADER_USER_DATA_HS_3" 2708 }, 2709 { 2710 "chips": ["gfx10"], 2711 "map": {"at": 46144, "to": "mm"}, 2712 "name": "SPI_SHADER_USER_DATA_HS_4" 2713 }, 2714 { 2715 "chips": ["gfx10"], 2716 "map": {"at": 46148, "to": "mm"}, 2717 "name": "SPI_SHADER_USER_DATA_HS_5" 2718 }, 2719 { 2720 "chips": ["gfx10"], 2721 "map": {"at": 46152, "to": "mm"}, 2722 "name": "SPI_SHADER_USER_DATA_HS_6" 2723 }, 2724 { 2725 "chips": ["gfx10"], 2726 "map": {"at": 46156, "to": "mm"}, 2727 "name": "SPI_SHADER_USER_DATA_HS_7" 2728 }, 2729 { 2730 "chips": ["gfx10"], 2731 "map": {"at": 46160, "to": "mm"}, 2732 "name": "SPI_SHADER_USER_DATA_HS_8" 2733 }, 2734 { 2735 "chips": ["gfx10"], 2736 "map": {"at": 46164, "to": "mm"}, 2737 "name": "SPI_SHADER_USER_DATA_HS_9" 2738 }, 2739 { 2740 "chips": ["gfx10"], 2741 "map": {"at": 46168, "to": "mm"}, 2742 "name": "SPI_SHADER_USER_DATA_HS_10" 2743 }, 2744 { 2745 "chips": ["gfx10"], 2746 "map": {"at": 46172, "to": "mm"}, 2747 "name": "SPI_SHADER_USER_DATA_HS_11" 2748 }, 2749 { 2750 "chips": ["gfx10"], 2751 "map": {"at": 46176, "to": "mm"}, 2752 "name": "SPI_SHADER_USER_DATA_HS_12" 2753 }, 2754 { 2755 "chips": ["gfx10"], 2756 "map": {"at": 46180, "to": "mm"}, 2757 "name": "SPI_SHADER_USER_DATA_HS_13" 2758 }, 2759 { 2760 "chips": ["gfx10"], 2761 "map": {"at": 46184, "to": "mm"}, 2762 "name": "SPI_SHADER_USER_DATA_HS_14" 2763 }, 2764 { 2765 "chips": ["gfx10"], 2766 "map": {"at": 46188, "to": "mm"}, 2767 "name": "SPI_SHADER_USER_DATA_HS_15" 2768 }, 2769 { 2770 "chips": ["gfx10"], 2771 "map": {"at": 46192, "to": "mm"}, 2772 "name": "SPI_SHADER_USER_DATA_HS_16" 2773 }, 2774 { 2775 "chips": ["gfx10"], 2776 "map": {"at": 46196, "to": "mm"}, 2777 "name": "SPI_SHADER_USER_DATA_HS_17" 2778 }, 2779 { 2780 "chips": ["gfx10"], 2781 "map": {"at": 46200, "to": "mm"}, 2782 "name": "SPI_SHADER_USER_DATA_HS_18" 2783 }, 2784 { 2785 "chips": ["gfx10"], 2786 "map": {"at": 46204, "to": "mm"}, 2787 "name": "SPI_SHADER_USER_DATA_HS_19" 2788 }, 2789 { 2790 "chips": ["gfx10"], 2791 "map": {"at": 46208, "to": "mm"}, 2792 "name": "SPI_SHADER_USER_DATA_HS_20" 2793 }, 2794 { 2795 "chips": ["gfx10"], 2796 "map": {"at": 46212, "to": "mm"}, 2797 "name": "SPI_SHADER_USER_DATA_HS_21" 2798 }, 2799 { 2800 "chips": ["gfx10"], 2801 "map": {"at": 46216, "to": "mm"}, 2802 "name": "SPI_SHADER_USER_DATA_HS_22" 2803 }, 2804 { 2805 "chips": ["gfx10"], 2806 "map": {"at": 46220, "to": "mm"}, 2807 "name": "SPI_SHADER_USER_DATA_HS_23" 2808 }, 2809 { 2810 "chips": ["gfx10"], 2811 "map": {"at": 46224, "to": "mm"}, 2812 "name": "SPI_SHADER_USER_DATA_HS_24" 2813 }, 2814 { 2815 "chips": ["gfx10"], 2816 "map": {"at": 46228, "to": "mm"}, 2817 "name": "SPI_SHADER_USER_DATA_HS_25" 2818 }, 2819 { 2820 "chips": ["gfx10"], 2821 "map": {"at": 46232, "to": "mm"}, 2822 "name": "SPI_SHADER_USER_DATA_HS_26" 2823 }, 2824 { 2825 "chips": ["gfx10"], 2826 "map": {"at": 46236, "to": "mm"}, 2827 "name": "SPI_SHADER_USER_DATA_HS_27" 2828 }, 2829 { 2830 "chips": ["gfx10"], 2831 "map": {"at": 46240, "to": "mm"}, 2832 "name": "SPI_SHADER_USER_DATA_HS_28" 2833 }, 2834 { 2835 "chips": ["gfx10"], 2836 "map": {"at": 46244, "to": "mm"}, 2837 "name": "SPI_SHADER_USER_DATA_HS_29" 2838 }, 2839 { 2840 "chips": ["gfx10"], 2841 "map": {"at": 46248, "to": "mm"}, 2842 "name": "SPI_SHADER_USER_DATA_HS_30" 2843 }, 2844 { 2845 "chips": ["gfx10"], 2846 "map": {"at": 46252, "to": "mm"}, 2847 "name": "SPI_SHADER_USER_DATA_HS_31" 2848 }, 2849 { 2850 "chips": ["gfx10"], 2851 "map": {"at": 46272, "to": "mm"}, 2852 "name": "SPI_SHADER_REQ_CTRL_LSHS", 2853 "type_ref": "SPI_SHADER_REQ_CTRL_PS" 2854 }, 2855 { 2856 "chips": ["gfx10"], 2857 "map": {"at": 46276, "to": "mm"}, 2858 "name": "SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS", 2859 "type_ref": "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS" 2860 }, 2861 { 2862 "chips": ["gfx10"], 2863 "map": {"at": 46280, "to": "mm"}, 2864 "name": "SPI_SHADER_USER_ACCUM_LSHS_0", 2865 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2866 }, 2867 { 2868 "chips": ["gfx10"], 2869 "map": {"at": 46284, "to": "mm"}, 2870 "name": "SPI_SHADER_USER_ACCUM_LSHS_1", 2871 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2872 }, 2873 { 2874 "chips": ["gfx10"], 2875 "map": {"at": 46288, "to": "mm"}, 2876 "name": "SPI_SHADER_USER_ACCUM_LSHS_2", 2877 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2878 }, 2879 { 2880 "chips": ["gfx10"], 2881 "map": {"at": 46292, "to": "mm"}, 2882 "name": "SPI_SHADER_USER_ACCUM_LSHS_3", 2883 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 2884 }, 2885 { 2886 "chips": ["gfx10"], 2887 "map": {"at": 46324, "to": "mm"}, 2888 "name": "SPI_SHADER_PGM_RSRC2_LS_HS", 2889 "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS" 2890 }, 2891 { 2892 "chips": ["gfx10"], 2893 "map": {"at": 46364, "to": "mm"}, 2894 "name": "SPI_SHADER_PGM_RSRC3_LS", 2895 "type_ref": "SPI_SHADER_PGM_RSRC3_GS" 2896 }, 2897 { 2898 "chips": ["gfx10"], 2899 "map": {"at": 46368, "to": "mm"}, 2900 "name": "SPI_SHADER_PGM_LO_LS" 2901 }, 2902 { 2903 "chips": ["gfx10"], 2904 "map": {"at": 46372, "to": "mm"}, 2905 "name": "SPI_SHADER_PGM_HI_LS", 2906 "type_ref": "SPI_SHADER_PGM_HI_PS" 2907 }, 2908 { 2909 "chips": ["gfx10"], 2910 "map": {"at": 46376, "to": "mm"}, 2911 "name": "SPI_SHADER_PGM_RSRC1_LS", 2912 "type_ref": "SPI_SHADER_PGM_RSRC1_LS" 2913 }, 2914 { 2915 "chips": ["gfx10"], 2916 "map": {"at": 46380, "to": "mm"}, 2917 "name": "SPI_SHADER_PGM_RSRC2_LS", 2918 "type_ref": "SPI_SHADER_PGM_RSRC2_LS_VS" 2919 }, 2920 { 2921 "chips": ["gfx10"], 2922 "map": {"at": 46384, "to": "mm"}, 2923 "name": "SPI_SHADER_USER_DATA_LS_0" 2924 }, 2925 { 2926 "chips": ["gfx10"], 2927 "map": {"at": 46388, "to": "mm"}, 2928 "name": "SPI_SHADER_USER_DATA_LS_1" 2929 }, 2930 { 2931 "chips": ["gfx10"], 2932 "map": {"at": 46392, "to": "mm"}, 2933 "name": "SPI_SHADER_USER_DATA_LS_2" 2934 }, 2935 { 2936 "chips": ["gfx10"], 2937 "map": {"at": 46396, "to": "mm"}, 2938 "name": "SPI_SHADER_USER_DATA_LS_3" 2939 }, 2940 { 2941 "chips": ["gfx10"], 2942 "map": {"at": 46400, "to": "mm"}, 2943 "name": "SPI_SHADER_USER_DATA_LS_4" 2944 }, 2945 { 2946 "chips": ["gfx10"], 2947 "map": {"at": 46404, "to": "mm"}, 2948 "name": "SPI_SHADER_USER_DATA_LS_5" 2949 }, 2950 { 2951 "chips": ["gfx10"], 2952 "map": {"at": 46408, "to": "mm"}, 2953 "name": "SPI_SHADER_USER_DATA_LS_6" 2954 }, 2955 { 2956 "chips": ["gfx10"], 2957 "map": {"at": 46412, "to": "mm"}, 2958 "name": "SPI_SHADER_USER_DATA_LS_7" 2959 }, 2960 { 2961 "chips": ["gfx10"], 2962 "map": {"at": 46416, "to": "mm"}, 2963 "name": "SPI_SHADER_USER_DATA_LS_8" 2964 }, 2965 { 2966 "chips": ["gfx10"], 2967 "map": {"at": 46420, "to": "mm"}, 2968 "name": "SPI_SHADER_USER_DATA_LS_9" 2969 }, 2970 { 2971 "chips": ["gfx10"], 2972 "map": {"at": 46424, "to": "mm"}, 2973 "name": "SPI_SHADER_USER_DATA_LS_10" 2974 }, 2975 { 2976 "chips": ["gfx10"], 2977 "map": {"at": 46428, "to": "mm"}, 2978 "name": "SPI_SHADER_USER_DATA_LS_11" 2979 }, 2980 { 2981 "chips": ["gfx10"], 2982 "map": {"at": 46432, "to": "mm"}, 2983 "name": "SPI_SHADER_USER_DATA_LS_12" 2984 }, 2985 { 2986 "chips": ["gfx10"], 2987 "map": {"at": 46436, "to": "mm"}, 2988 "name": "SPI_SHADER_USER_DATA_LS_13" 2989 }, 2990 { 2991 "chips": ["gfx10"], 2992 "map": {"at": 46440, "to": "mm"}, 2993 "name": "SPI_SHADER_USER_DATA_LS_14" 2994 }, 2995 { 2996 "chips": ["gfx10"], 2997 "map": {"at": 46444, "to": "mm"}, 2998 "name": "SPI_SHADER_USER_DATA_LS_15" 2999 }, 3000 { 3001 "chips": ["gfx10"], 3002 "map": {"at": 47104, "to": "mm"}, 3003 "name": "COMPUTE_DISPATCH_INITIATOR", 3004 "type_ref": "COMPUTE_DISPATCH_INITIATOR" 3005 }, 3006 { 3007 "chips": ["gfx10"], 3008 "map": {"at": 47108, "to": "mm"}, 3009 "name": "COMPUTE_DIM_X" 3010 }, 3011 { 3012 "chips": ["gfx10"], 3013 "map": {"at": 47112, "to": "mm"}, 3014 "name": "COMPUTE_DIM_Y" 3015 }, 3016 { 3017 "chips": ["gfx10"], 3018 "map": {"at": 47116, "to": "mm"}, 3019 "name": "COMPUTE_DIM_Z" 3020 }, 3021 { 3022 "chips": ["gfx10"], 3023 "map": {"at": 47120, "to": "mm"}, 3024 "name": "COMPUTE_START_X" 3025 }, 3026 { 3027 "chips": ["gfx10"], 3028 "map": {"at": 47124, "to": "mm"}, 3029 "name": "COMPUTE_START_Y" 3030 }, 3031 { 3032 "chips": ["gfx10"], 3033 "map": {"at": 47128, "to": "mm"}, 3034 "name": "COMPUTE_START_Z" 3035 }, 3036 { 3037 "chips": ["gfx10"], 3038 "map": {"at": 47132, "to": "mm"}, 3039 "name": "COMPUTE_NUM_THREAD_X", 3040 "type_ref": "COMPUTE_NUM_THREAD_X" 3041 }, 3042 { 3043 "chips": ["gfx10"], 3044 "map": {"at": 47136, "to": "mm"}, 3045 "name": "COMPUTE_NUM_THREAD_Y", 3046 "type_ref": "COMPUTE_NUM_THREAD_X" 3047 }, 3048 { 3049 "chips": ["gfx10"], 3050 "map": {"at": 47140, "to": "mm"}, 3051 "name": "COMPUTE_NUM_THREAD_Z", 3052 "type_ref": "COMPUTE_NUM_THREAD_X" 3053 }, 3054 { 3055 "chips": ["gfx10"], 3056 "map": {"at": 47144, "to": "mm"}, 3057 "name": "COMPUTE_PIPELINESTAT_ENABLE", 3058 "type_ref": "COMPUTE_PIPELINESTAT_ENABLE" 3059 }, 3060 { 3061 "chips": ["gfx10"], 3062 "map": {"at": 47148, "to": "mm"}, 3063 "name": "COMPUTE_PERFCOUNT_ENABLE", 3064 "type_ref": "COMPUTE_PERFCOUNT_ENABLE" 3065 }, 3066 { 3067 "chips": ["gfx10"], 3068 "map": {"at": 47152, "to": "mm"}, 3069 "name": "COMPUTE_PGM_LO" 3070 }, 3071 { 3072 "chips": ["gfx10"], 3073 "map": {"at": 47156, "to": "mm"}, 3074 "name": "COMPUTE_PGM_HI", 3075 "type_ref": "COMPUTE_PGM_HI" 3076 }, 3077 { 3078 "chips": ["gfx10"], 3079 "map": {"at": 47160, "to": "mm"}, 3080 "name": "COMPUTE_DISPATCH_PKT_ADDR_LO" 3081 }, 3082 { 3083 "chips": ["gfx10"], 3084 "map": {"at": 47164, "to": "mm"}, 3085 "name": "COMPUTE_DISPATCH_PKT_ADDR_HI", 3086 "type_ref": "COMPUTE_PGM_HI" 3087 }, 3088 { 3089 "chips": ["gfx10"], 3090 "map": {"at": 47168, "to": "mm"}, 3091 "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO" 3092 }, 3093 { 3094 "chips": ["gfx10"], 3095 "map": {"at": 47172, "to": "mm"}, 3096 "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI", 3097 "type_ref": "COMPUTE_PGM_HI" 3098 }, 3099 { 3100 "chips": ["gfx10"], 3101 "map": {"at": 47176, "to": "mm"}, 3102 "name": "COMPUTE_PGM_RSRC1", 3103 "type_ref": "COMPUTE_PGM_RSRC1" 3104 }, 3105 { 3106 "chips": ["gfx10"], 3107 "map": {"at": 47180, "to": "mm"}, 3108 "name": "COMPUTE_PGM_RSRC2", 3109 "type_ref": "COMPUTE_PGM_RSRC2" 3110 }, 3111 { 3112 "chips": ["gfx10"], 3113 "map": {"at": 47184, "to": "mm"}, 3114 "name": "COMPUTE_VMID", 3115 "type_ref": "COMPUTE_VMID" 3116 }, 3117 { 3118 "chips": ["gfx10"], 3119 "map": {"at": 47188, "to": "mm"}, 3120 "name": "COMPUTE_RESOURCE_LIMITS", 3121 "type_ref": "COMPUTE_RESOURCE_LIMITS" 3122 }, 3123 { 3124 "chips": ["gfx10"], 3125 "map": {"at": 47192, "to": "mm"}, 3126 "name": "COMPUTE_DESTINATION_EN_SE0" 3127 }, 3128 { 3129 "chips": ["gfx10"], 3130 "map": {"at": 47196, "to": "mm"}, 3131 "name": "COMPUTE_DESTINATION_EN_SE1" 3132 }, 3133 { 3134 "chips": ["gfx10"], 3135 "map": {"at": 47200, "to": "mm"}, 3136 "name": "COMPUTE_TMPRING_SIZE", 3137 "type_ref": "COMPUTE_TMPRING_SIZE" 3138 }, 3139 { 3140 "chips": ["gfx10"], 3141 "map": {"at": 47204, "to": "mm"}, 3142 "name": "COMPUTE_DESTINATION_EN_SE2" 3143 }, 3144 { 3145 "chips": ["gfx10"], 3146 "map": {"at": 47208, "to": "mm"}, 3147 "name": "COMPUTE_DESTINATION_EN_SE3" 3148 }, 3149 { 3150 "chips": ["gfx10"], 3151 "map": {"at": 47212, "to": "mm"}, 3152 "name": "COMPUTE_RESTART_X" 3153 }, 3154 { 3155 "chips": ["gfx10"], 3156 "map": {"at": 47216, "to": "mm"}, 3157 "name": "COMPUTE_RESTART_Y" 3158 }, 3159 { 3160 "chips": ["gfx10"], 3161 "map": {"at": 47220, "to": "mm"}, 3162 "name": "COMPUTE_RESTART_Z" 3163 }, 3164 { 3165 "chips": ["gfx10"], 3166 "map": {"at": 47224, "to": "mm"}, 3167 "name": "COMPUTE_THREAD_TRACE_ENABLE", 3168 "type_ref": "COMPUTE_THREAD_TRACE_ENABLE" 3169 }, 3170 { 3171 "chips": ["gfx10"], 3172 "map": {"at": 47228, "to": "mm"}, 3173 "name": "COMPUTE_MISC_RESERVED", 3174 "type_ref": "COMPUTE_MISC_RESERVED" 3175 }, 3176 { 3177 "chips": ["gfx10"], 3178 "map": {"at": 47232, "to": "mm"}, 3179 "name": "COMPUTE_DISPATCH_ID" 3180 }, 3181 { 3182 "chips": ["gfx10"], 3183 "map": {"at": 47236, "to": "mm"}, 3184 "name": "COMPUTE_THREADGROUP_ID" 3185 }, 3186 { 3187 "chips": ["gfx10"], 3188 "map": {"at": 47240, "to": "mm"}, 3189 "name": "COMPUTE_REQ_CTRL", 3190 "type_ref": "COMPUTE_REQ_CTRL" 3191 }, 3192 { 3193 "chips": ["gfx10"], 3194 "map": {"at": 47248, "to": "mm"}, 3195 "name": "COMPUTE_USER_ACCUM_0", 3196 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 3197 }, 3198 { 3199 "chips": ["gfx10"], 3200 "map": {"at": 47252, "to": "mm"}, 3201 "name": "COMPUTE_USER_ACCUM_1", 3202 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 3203 }, 3204 { 3205 "chips": ["gfx10"], 3206 "map": {"at": 47256, "to": "mm"}, 3207 "name": "COMPUTE_USER_ACCUM_2", 3208 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 3209 }, 3210 { 3211 "chips": ["gfx10"], 3212 "map": {"at": 47260, "to": "mm"}, 3213 "name": "COMPUTE_USER_ACCUM_3", 3214 "type_ref": "SPI_SHADER_USER_ACCUM_PS_0" 3215 }, 3216 { 3217 "chips": ["gfx10"], 3218 "map": {"at": 47264, "to": "mm"}, 3219 "name": "COMPUTE_PGM_RSRC3", 3220 "type_ref": "COMPUTE_PGM_RSRC3" 3221 }, 3222 { 3223 "chips": ["gfx10"], 3224 "map": {"at": 47268, "to": "mm"}, 3225 "name": "COMPUTE_DDID_INDEX", 3226 "type_ref": "COMPUTE_DDID_INDEX" 3227 }, 3228 { 3229 "chips": ["gfx10"], 3230 "map": {"at": 47272, "to": "mm"}, 3231 "name": "COMPUTE_SHADER_CHKSUM" 3232 }, 3233 { 3234 "chips": ["gfx10"], 3235 "map": {"at": 47276, "to": "mm"}, 3236 "name": "COMPUTE_RELAUNCH", 3237 "type_ref": "COMPUTE_RELAUNCH" 3238 }, 3239 { 3240 "chips": ["gfx10"], 3241 "map": {"at": 47280, "to": "mm"}, 3242 "name": "COMPUTE_WAVE_RESTORE_ADDR_LO" 3243 }, 3244 { 3245 "chips": ["gfx10"], 3246 "map": {"at": 47284, "to": "mm"}, 3247 "name": "COMPUTE_WAVE_RESTORE_ADDR_HI", 3248 "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI" 3249 }, 3250 { 3251 "chips": ["gfx10"], 3252 "map": {"at": 47288, "to": "mm"}, 3253 "name": "COMPUTE_RELAUNCH2", 3254 "type_ref": "COMPUTE_RELAUNCH" 3255 }, 3256 { 3257 "chips": ["gfx10"], 3258 "map": {"at": 47360, "to": "mm"}, 3259 "name": "COMPUTE_USER_DATA_0" 3260 }, 3261 { 3262 "chips": ["gfx10"], 3263 "map": {"at": 47364, "to": "mm"}, 3264 "name": "COMPUTE_USER_DATA_1" 3265 }, 3266 { 3267 "chips": ["gfx10"], 3268 "map": {"at": 47368, "to": "mm"}, 3269 "name": "COMPUTE_USER_DATA_2" 3270 }, 3271 { 3272 "chips": ["gfx10"], 3273 "map": {"at": 47372, "to": "mm"}, 3274 "name": "COMPUTE_USER_DATA_3" 3275 }, 3276 { 3277 "chips": ["gfx10"], 3278 "map": {"at": 47376, "to": "mm"}, 3279 "name": "COMPUTE_USER_DATA_4" 3280 }, 3281 { 3282 "chips": ["gfx10"], 3283 "map": {"at": 47380, "to": "mm"}, 3284 "name": "COMPUTE_USER_DATA_5" 3285 }, 3286 { 3287 "chips": ["gfx10"], 3288 "map": {"at": 47384, "to": "mm"}, 3289 "name": "COMPUTE_USER_DATA_6" 3290 }, 3291 { 3292 "chips": ["gfx10"], 3293 "map": {"at": 47388, "to": "mm"}, 3294 "name": "COMPUTE_USER_DATA_7" 3295 }, 3296 { 3297 "chips": ["gfx10"], 3298 "map": {"at": 47392, "to": "mm"}, 3299 "name": "COMPUTE_USER_DATA_8" 3300 }, 3301 { 3302 "chips": ["gfx10"], 3303 "map": {"at": 47396, "to": "mm"}, 3304 "name": "COMPUTE_USER_DATA_9" 3305 }, 3306 { 3307 "chips": ["gfx10"], 3308 "map": {"at": 47400, "to": "mm"}, 3309 "name": "COMPUTE_USER_DATA_10" 3310 }, 3311 { 3312 "chips": ["gfx10"], 3313 "map": {"at": 47404, "to": "mm"}, 3314 "name": "COMPUTE_USER_DATA_11" 3315 }, 3316 { 3317 "chips": ["gfx10"], 3318 "map": {"at": 47408, "to": "mm"}, 3319 "name": "COMPUTE_USER_DATA_12" 3320 }, 3321 { 3322 "chips": ["gfx10"], 3323 "map": {"at": 47412, "to": "mm"}, 3324 "name": "COMPUTE_USER_DATA_13" 3325 }, 3326 { 3327 "chips": ["gfx10"], 3328 "map": {"at": 47416, "to": "mm"}, 3329 "name": "COMPUTE_USER_DATA_14" 3330 }, 3331 { 3332 "chips": ["gfx10"], 3333 "map": {"at": 47420, "to": "mm"}, 3334 "name": "COMPUTE_USER_DATA_15" 3335 }, 3336 { 3337 "chips": ["gfx10"], 3338 "map": {"at": 47604, "to": "mm"}, 3339 "name": "COMPUTE_DISPATCH_TUNNEL", 3340 "type_ref": "COMPUTE_DISPATCH_TUNNEL" 3341 }, 3342 { 3343 "chips": ["gfx10"], 3344 "map": {"at": 47608, "to": "mm"}, 3345 "name": "COMPUTE_DISPATCH_END" 3346 }, 3347 { 3348 "chips": ["gfx10"], 3349 "map": {"at": 47612, "to": "mm"}, 3350 "name": "COMPUTE_NOWHERE" 3351 }, 3352 { 3353 "chips": ["gfx10"], 3354 "map": {"at": 163840, "to": "mm"}, 3355 "name": "DB_RENDER_CONTROL", 3356 "type_ref": "DB_RENDER_CONTROL" 3357 }, 3358 { 3359 "chips": ["gfx10"], 3360 "map": {"at": 163844, "to": "mm"}, 3361 "name": "DB_COUNT_CONTROL", 3362 "type_ref": "DB_COUNT_CONTROL" 3363 }, 3364 { 3365 "chips": ["gfx10"], 3366 "map": {"at": 163848, "to": "mm"}, 3367 "name": "DB_DEPTH_VIEW", 3368 "type_ref": "DB_DEPTH_VIEW" 3369 }, 3370 { 3371 "chips": ["gfx10"], 3372 "map": {"at": 163852, "to": "mm"}, 3373 "name": "DB_RENDER_OVERRIDE", 3374 "type_ref": "DB_RENDER_OVERRIDE" 3375 }, 3376 { 3377 "chips": ["gfx10"], 3378 "map": {"at": 163856, "to": "mm"}, 3379 "name": "DB_RENDER_OVERRIDE2", 3380 "type_ref": "DB_RENDER_OVERRIDE2" 3381 }, 3382 { 3383 "chips": ["gfx10"], 3384 "map": {"at": 163860, "to": "mm"}, 3385 "name": "DB_HTILE_DATA_BASE" 3386 }, 3387 { 3388 "chips": ["gfx10"], 3389 "map": {"at": 163868, "to": "mm"}, 3390 "name": "DB_DEPTH_SIZE_XY", 3391 "type_ref": "DB_DEPTH_SIZE_XY" 3392 }, 3393 { 3394 "chips": ["gfx10"], 3395 "map": {"at": 163872, "to": "mm"}, 3396 "name": "DB_DEPTH_BOUNDS_MIN" 3397 }, 3398 { 3399 "chips": ["gfx10"], 3400 "map": {"at": 163876, "to": "mm"}, 3401 "name": "DB_DEPTH_BOUNDS_MAX" 3402 }, 3403 { 3404 "chips": ["gfx10"], 3405 "map": {"at": 163880, "to": "mm"}, 3406 "name": "DB_STENCIL_CLEAR", 3407 "type_ref": "DB_STENCIL_CLEAR" 3408 }, 3409 { 3410 "chips": ["gfx10"], 3411 "map": {"at": 163884, "to": "mm"}, 3412 "name": "DB_DEPTH_CLEAR" 3413 }, 3414 { 3415 "chips": ["gfx10"], 3416 "map": {"at": 163888, "to": "mm"}, 3417 "name": "PA_SC_SCREEN_SCISSOR_TL", 3418 "type_ref": "PA_SC_SCREEN_SCISSOR_TL" 3419 }, 3420 { 3421 "chips": ["gfx10"], 3422 "map": {"at": 163892, "to": "mm"}, 3423 "name": "PA_SC_SCREEN_SCISSOR_BR", 3424 "type_ref": "PA_SC_SCREEN_SCISSOR_BR" 3425 }, 3426 { 3427 "chips": ["gfx10"], 3428 "map": {"at": 163896, "to": "mm"}, 3429 "name": "DB_DFSM_CONTROL", 3430 "type_ref": "DB_DFSM_CONTROL" 3431 }, 3432 { 3433 "chips": ["gfx10"], 3434 "map": {"at": 163900, "to": "mm"}, 3435 "name": "DB_RESERVED_REG_2", 3436 "type_ref": "DB_RESERVED_REG_2" 3437 }, 3438 { 3439 "chips": ["gfx10"], 3440 "map": {"at": 163904, "to": "mm"}, 3441 "name": "DB_Z_INFO", 3442 "type_ref": "DB_Z_INFO" 3443 }, 3444 { 3445 "chips": ["gfx10"], 3446 "map": {"at": 163908, "to": "mm"}, 3447 "name": "DB_STENCIL_INFO", 3448 "type_ref": "DB_STENCIL_INFO" 3449 }, 3450 { 3451 "chips": ["gfx10"], 3452 "map": {"at": 163912, "to": "mm"}, 3453 "name": "DB_Z_READ_BASE" 3454 }, 3455 { 3456 "chips": ["gfx10"], 3457 "map": {"at": 163916, "to": "mm"}, 3458 "name": "DB_STENCIL_READ_BASE" 3459 }, 3460 { 3461 "chips": ["gfx10"], 3462 "map": {"at": 163920, "to": "mm"}, 3463 "name": "DB_Z_WRITE_BASE" 3464 }, 3465 { 3466 "chips": ["gfx10"], 3467 "map": {"at": 163924, "to": "mm"}, 3468 "name": "DB_STENCIL_WRITE_BASE" 3469 }, 3470 { 3471 "chips": ["gfx10"], 3472 "map": {"at": 163928, "to": "mm"}, 3473 "name": "DB_RESERVED_REG_1", 3474 "type_ref": "DB_RESERVED_REG_1" 3475 }, 3476 { 3477 "chips": ["gfx10"], 3478 "map": {"at": 163932, "to": "mm"}, 3479 "name": "DB_RESERVED_REG_3", 3480 "type_ref": "DB_RESERVED_REG_3" 3481 }, 3482 { 3483 "chips": ["gfx10"], 3484 "map": {"at": 163944, "to": "mm"}, 3485 "name": "DB_Z_READ_BASE_HI", 3486 "type_ref": "DB_Z_READ_BASE_HI" 3487 }, 3488 { 3489 "chips": ["gfx10"], 3490 "map": {"at": 163948, "to": "mm"}, 3491 "name": "DB_STENCIL_READ_BASE_HI", 3492 "type_ref": "DB_Z_READ_BASE_HI" 3493 }, 3494 { 3495 "chips": ["gfx10"], 3496 "map": {"at": 163952, "to": "mm"}, 3497 "name": "DB_Z_WRITE_BASE_HI", 3498 "type_ref": "DB_Z_READ_BASE_HI" 3499 }, 3500 { 3501 "chips": ["gfx10"], 3502 "map": {"at": 163956, "to": "mm"}, 3503 "name": "DB_STENCIL_WRITE_BASE_HI", 3504 "type_ref": "DB_Z_READ_BASE_HI" 3505 }, 3506 { 3507 "chips": ["gfx10"], 3508 "map": {"at": 163960, "to": "mm"}, 3509 "name": "DB_HTILE_DATA_BASE_HI", 3510 "type_ref": "DB_Z_READ_BASE_HI" 3511 }, 3512 { 3513 "chips": ["gfx10"], 3514 "map": {"at": 163964, "to": "mm"}, 3515 "name": "DB_RMI_L2_CACHE_CONTROL", 3516 "type_ref": "DB_RMI_L2_CACHE_CONTROL" 3517 }, 3518 { 3519 "chips": ["gfx10"], 3520 "map": {"at": 163968, "to": "mm"}, 3521 "name": "TA_BC_BASE_ADDR" 3522 }, 3523 { 3524 "chips": ["gfx10"], 3525 "map": {"at": 163972, "to": "mm"}, 3526 "name": "TA_BC_BASE_ADDR_HI", 3527 "type_ref": "TA_BC_BASE_ADDR_HI" 3528 }, 3529 { 3530 "chips": ["gfx10"], 3531 "map": {"at": 164328, "to": "mm"}, 3532 "name": "COHER_DEST_BASE_HI_0", 3533 "type_ref": "COHER_DEST_BASE_HI_0" 3534 }, 3535 { 3536 "chips": ["gfx10"], 3537 "map": {"at": 164332, "to": "mm"}, 3538 "name": "COHER_DEST_BASE_HI_1", 3539 "type_ref": "COHER_DEST_BASE_HI_0" 3540 }, 3541 { 3542 "chips": ["gfx10"], 3543 "map": {"at": 164336, "to": "mm"}, 3544 "name": "COHER_DEST_BASE_HI_2", 3545 "type_ref": "COHER_DEST_BASE_HI_0" 3546 }, 3547 { 3548 "chips": ["gfx10"], 3549 "map": {"at": 164340, "to": "mm"}, 3550 "name": "COHER_DEST_BASE_HI_3", 3551 "type_ref": "COHER_DEST_BASE_HI_0" 3552 }, 3553 { 3554 "chips": ["gfx10"], 3555 "map": {"at": 164344, "to": "mm"}, 3556 "name": "COHER_DEST_BASE_2" 3557 }, 3558 { 3559 "chips": ["gfx10"], 3560 "map": {"at": 164348, "to": "mm"}, 3561 "name": "COHER_DEST_BASE_3" 3562 }, 3563 { 3564 "chips": ["gfx10"], 3565 "map": {"at": 164352, "to": "mm"}, 3566 "name": "PA_SC_WINDOW_OFFSET", 3567 "type_ref": "PA_SC_WINDOW_OFFSET" 3568 }, 3569 { 3570 "chips": ["gfx10"], 3571 "map": {"at": 164356, "to": "mm"}, 3572 "name": "PA_SC_WINDOW_SCISSOR_TL", 3573 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3574 }, 3575 { 3576 "chips": ["gfx10"], 3577 "map": {"at": 164360, "to": "mm"}, 3578 "name": "PA_SC_WINDOW_SCISSOR_BR", 3579 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3580 }, 3581 { 3582 "chips": ["gfx10"], 3583 "map": {"at": 164364, "to": "mm"}, 3584 "name": "PA_SC_CLIPRECT_RULE", 3585 "type_ref": "PA_SC_CLIPRECT_RULE" 3586 }, 3587 { 3588 "chips": ["gfx10"], 3589 "map": {"at": 164368, "to": "mm"}, 3590 "name": "PA_SC_CLIPRECT_0_TL", 3591 "type_ref": "PA_SC_CLIPRECT_0_TL" 3592 }, 3593 { 3594 "chips": ["gfx10"], 3595 "map": {"at": 164372, "to": "mm"}, 3596 "name": "PA_SC_CLIPRECT_0_BR", 3597 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3598 }, 3599 { 3600 "chips": ["gfx10"], 3601 "map": {"at": 164376, "to": "mm"}, 3602 "name": "PA_SC_CLIPRECT_1_TL", 3603 "type_ref": "PA_SC_CLIPRECT_0_TL" 3604 }, 3605 { 3606 "chips": ["gfx10"], 3607 "map": {"at": 164380, "to": "mm"}, 3608 "name": "PA_SC_CLIPRECT_1_BR", 3609 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3610 }, 3611 { 3612 "chips": ["gfx10"], 3613 "map": {"at": 164384, "to": "mm"}, 3614 "name": "PA_SC_CLIPRECT_2_TL", 3615 "type_ref": "PA_SC_CLIPRECT_0_TL" 3616 }, 3617 { 3618 "chips": ["gfx10"], 3619 "map": {"at": 164388, "to": "mm"}, 3620 "name": "PA_SC_CLIPRECT_2_BR", 3621 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3622 }, 3623 { 3624 "chips": ["gfx10"], 3625 "map": {"at": 164392, "to": "mm"}, 3626 "name": "PA_SC_CLIPRECT_3_TL", 3627 "type_ref": "PA_SC_CLIPRECT_0_TL" 3628 }, 3629 { 3630 "chips": ["gfx10"], 3631 "map": {"at": 164396, "to": "mm"}, 3632 "name": "PA_SC_CLIPRECT_3_BR", 3633 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3634 }, 3635 { 3636 "chips": ["gfx10"], 3637 "map": {"at": 164400, "to": "mm"}, 3638 "name": "PA_SC_EDGERULE", 3639 "type_ref": "PA_SC_EDGERULE" 3640 }, 3641 { 3642 "chips": ["gfx10"], 3643 "map": {"at": 164404, "to": "mm"}, 3644 "name": "PA_SU_HARDWARE_SCREEN_OFFSET", 3645 "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET" 3646 }, 3647 { 3648 "chips": ["gfx10"], 3649 "map": {"at": 164408, "to": "mm"}, 3650 "name": "CB_TARGET_MASK", 3651 "type_ref": "CB_TARGET_MASK" 3652 }, 3653 { 3654 "chips": ["gfx10"], 3655 "map": {"at": 164412, "to": "mm"}, 3656 "name": "CB_SHADER_MASK", 3657 "type_ref": "CB_SHADER_MASK" 3658 }, 3659 { 3660 "chips": ["gfx10"], 3661 "map": {"at": 164416, "to": "mm"}, 3662 "name": "PA_SC_GENERIC_SCISSOR_TL", 3663 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3664 }, 3665 { 3666 "chips": ["gfx10"], 3667 "map": {"at": 164420, "to": "mm"}, 3668 "name": "PA_SC_GENERIC_SCISSOR_BR", 3669 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3670 }, 3671 { 3672 "chips": ["gfx10"], 3673 "map": {"at": 164424, "to": "mm"}, 3674 "name": "COHER_DEST_BASE_0" 3675 }, 3676 { 3677 "chips": ["gfx10"], 3678 "map": {"at": 164428, "to": "mm"}, 3679 "name": "COHER_DEST_BASE_1" 3680 }, 3681 { 3682 "chips": ["gfx10"], 3683 "map": {"at": 164432, "to": "mm"}, 3684 "name": "PA_SC_VPORT_SCISSOR_0_TL", 3685 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3686 }, 3687 { 3688 "chips": ["gfx10"], 3689 "map": {"at": 164436, "to": "mm"}, 3690 "name": "PA_SC_VPORT_SCISSOR_0_BR", 3691 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3692 }, 3693 { 3694 "chips": ["gfx10"], 3695 "map": {"at": 164440, "to": "mm"}, 3696 "name": "PA_SC_VPORT_SCISSOR_1_TL", 3697 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3698 }, 3699 { 3700 "chips": ["gfx10"], 3701 "map": {"at": 164444, "to": "mm"}, 3702 "name": "PA_SC_VPORT_SCISSOR_1_BR", 3703 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3704 }, 3705 { 3706 "chips": ["gfx10"], 3707 "map": {"at": 164448, "to": "mm"}, 3708 "name": "PA_SC_VPORT_SCISSOR_2_TL", 3709 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3710 }, 3711 { 3712 "chips": ["gfx10"], 3713 "map": {"at": 164452, "to": "mm"}, 3714 "name": "PA_SC_VPORT_SCISSOR_2_BR", 3715 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3716 }, 3717 { 3718 "chips": ["gfx10"], 3719 "map": {"at": 164456, "to": "mm"}, 3720 "name": "PA_SC_VPORT_SCISSOR_3_TL", 3721 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3722 }, 3723 { 3724 "chips": ["gfx10"], 3725 "map": {"at": 164460, "to": "mm"}, 3726 "name": "PA_SC_VPORT_SCISSOR_3_BR", 3727 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3728 }, 3729 { 3730 "chips": ["gfx10"], 3731 "map": {"at": 164464, "to": "mm"}, 3732 "name": "PA_SC_VPORT_SCISSOR_4_TL", 3733 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3734 }, 3735 { 3736 "chips": ["gfx10"], 3737 "map": {"at": 164468, "to": "mm"}, 3738 "name": "PA_SC_VPORT_SCISSOR_4_BR", 3739 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3740 }, 3741 { 3742 "chips": ["gfx10"], 3743 "map": {"at": 164472, "to": "mm"}, 3744 "name": "PA_SC_VPORT_SCISSOR_5_TL", 3745 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3746 }, 3747 { 3748 "chips": ["gfx10"], 3749 "map": {"at": 164476, "to": "mm"}, 3750 "name": "PA_SC_VPORT_SCISSOR_5_BR", 3751 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3752 }, 3753 { 3754 "chips": ["gfx10"], 3755 "map": {"at": 164480, "to": "mm"}, 3756 "name": "PA_SC_VPORT_SCISSOR_6_TL", 3757 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3758 }, 3759 { 3760 "chips": ["gfx10"], 3761 "map": {"at": 164484, "to": "mm"}, 3762 "name": "PA_SC_VPORT_SCISSOR_6_BR", 3763 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3764 }, 3765 { 3766 "chips": ["gfx10"], 3767 "map": {"at": 164488, "to": "mm"}, 3768 "name": "PA_SC_VPORT_SCISSOR_7_TL", 3769 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3770 }, 3771 { 3772 "chips": ["gfx10"], 3773 "map": {"at": 164492, "to": "mm"}, 3774 "name": "PA_SC_VPORT_SCISSOR_7_BR", 3775 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3776 }, 3777 { 3778 "chips": ["gfx10"], 3779 "map": {"at": 164496, "to": "mm"}, 3780 "name": "PA_SC_VPORT_SCISSOR_8_TL", 3781 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3782 }, 3783 { 3784 "chips": ["gfx10"], 3785 "map": {"at": 164500, "to": "mm"}, 3786 "name": "PA_SC_VPORT_SCISSOR_8_BR", 3787 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3788 }, 3789 { 3790 "chips": ["gfx10"], 3791 "map": {"at": 164504, "to": "mm"}, 3792 "name": "PA_SC_VPORT_SCISSOR_9_TL", 3793 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3794 }, 3795 { 3796 "chips": ["gfx10"], 3797 "map": {"at": 164508, "to": "mm"}, 3798 "name": "PA_SC_VPORT_SCISSOR_9_BR", 3799 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3800 }, 3801 { 3802 "chips": ["gfx10"], 3803 "map": {"at": 164512, "to": "mm"}, 3804 "name": "PA_SC_VPORT_SCISSOR_10_TL", 3805 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3806 }, 3807 { 3808 "chips": ["gfx10"], 3809 "map": {"at": 164516, "to": "mm"}, 3810 "name": "PA_SC_VPORT_SCISSOR_10_BR", 3811 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3812 }, 3813 { 3814 "chips": ["gfx10"], 3815 "map": {"at": 164520, "to": "mm"}, 3816 "name": "PA_SC_VPORT_SCISSOR_11_TL", 3817 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3818 }, 3819 { 3820 "chips": ["gfx10"], 3821 "map": {"at": 164524, "to": "mm"}, 3822 "name": "PA_SC_VPORT_SCISSOR_11_BR", 3823 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3824 }, 3825 { 3826 "chips": ["gfx10"], 3827 "map": {"at": 164528, "to": "mm"}, 3828 "name": "PA_SC_VPORT_SCISSOR_12_TL", 3829 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3830 }, 3831 { 3832 "chips": ["gfx10"], 3833 "map": {"at": 164532, "to": "mm"}, 3834 "name": "PA_SC_VPORT_SCISSOR_12_BR", 3835 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3836 }, 3837 { 3838 "chips": ["gfx10"], 3839 "map": {"at": 164536, "to": "mm"}, 3840 "name": "PA_SC_VPORT_SCISSOR_13_TL", 3841 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3842 }, 3843 { 3844 "chips": ["gfx10"], 3845 "map": {"at": 164540, "to": "mm"}, 3846 "name": "PA_SC_VPORT_SCISSOR_13_BR", 3847 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3848 }, 3849 { 3850 "chips": ["gfx10"], 3851 "map": {"at": 164544, "to": "mm"}, 3852 "name": "PA_SC_VPORT_SCISSOR_14_TL", 3853 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3854 }, 3855 { 3856 "chips": ["gfx10"], 3857 "map": {"at": 164548, "to": "mm"}, 3858 "name": "PA_SC_VPORT_SCISSOR_14_BR", 3859 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3860 }, 3861 { 3862 "chips": ["gfx10"], 3863 "map": {"at": 164552, "to": "mm"}, 3864 "name": "PA_SC_VPORT_SCISSOR_15_TL", 3865 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3866 }, 3867 { 3868 "chips": ["gfx10"], 3869 "map": {"at": 164556, "to": "mm"}, 3870 "name": "PA_SC_VPORT_SCISSOR_15_BR", 3871 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3872 }, 3873 { 3874 "chips": ["gfx10"], 3875 "map": {"at": 164560, "to": "mm"}, 3876 "name": "PA_SC_VPORT_ZMIN_0" 3877 }, 3878 { 3879 "chips": ["gfx10"], 3880 "map": {"at": 164564, "to": "mm"}, 3881 "name": "PA_SC_VPORT_ZMAX_0" 3882 }, 3883 { 3884 "chips": ["gfx10"], 3885 "map": {"at": 164568, "to": "mm"}, 3886 "name": "PA_SC_VPORT_ZMIN_1" 3887 }, 3888 { 3889 "chips": ["gfx10"], 3890 "map": {"at": 164572, "to": "mm"}, 3891 "name": "PA_SC_VPORT_ZMAX_1" 3892 }, 3893 { 3894 "chips": ["gfx10"], 3895 "map": {"at": 164576, "to": "mm"}, 3896 "name": "PA_SC_VPORT_ZMIN_2" 3897 }, 3898 { 3899 "chips": ["gfx10"], 3900 "map": {"at": 164580, "to": "mm"}, 3901 "name": "PA_SC_VPORT_ZMAX_2" 3902 }, 3903 { 3904 "chips": ["gfx10"], 3905 "map": {"at": 164584, "to": "mm"}, 3906 "name": "PA_SC_VPORT_ZMIN_3" 3907 }, 3908 { 3909 "chips": ["gfx10"], 3910 "map": {"at": 164588, "to": "mm"}, 3911 "name": "PA_SC_VPORT_ZMAX_3" 3912 }, 3913 { 3914 "chips": ["gfx10"], 3915 "map": {"at": 164592, "to": "mm"}, 3916 "name": "PA_SC_VPORT_ZMIN_4" 3917 }, 3918 { 3919 "chips": ["gfx10"], 3920 "map": {"at": 164596, "to": "mm"}, 3921 "name": "PA_SC_VPORT_ZMAX_4" 3922 }, 3923 { 3924 "chips": ["gfx10"], 3925 "map": {"at": 164600, "to": "mm"}, 3926 "name": "PA_SC_VPORT_ZMIN_5" 3927 }, 3928 { 3929 "chips": ["gfx10"], 3930 "map": {"at": 164604, "to": "mm"}, 3931 "name": "PA_SC_VPORT_ZMAX_5" 3932 }, 3933 { 3934 "chips": ["gfx10"], 3935 "map": {"at": 164608, "to": "mm"}, 3936 "name": "PA_SC_VPORT_ZMIN_6" 3937 }, 3938 { 3939 "chips": ["gfx10"], 3940 "map": {"at": 164612, "to": "mm"}, 3941 "name": "PA_SC_VPORT_ZMAX_6" 3942 }, 3943 { 3944 "chips": ["gfx10"], 3945 "map": {"at": 164616, "to": "mm"}, 3946 "name": "PA_SC_VPORT_ZMIN_7" 3947 }, 3948 { 3949 "chips": ["gfx10"], 3950 "map": {"at": 164620, "to": "mm"}, 3951 "name": "PA_SC_VPORT_ZMAX_7" 3952 }, 3953 { 3954 "chips": ["gfx10"], 3955 "map": {"at": 164624, "to": "mm"}, 3956 "name": "PA_SC_VPORT_ZMIN_8" 3957 }, 3958 { 3959 "chips": ["gfx10"], 3960 "map": {"at": 164628, "to": "mm"}, 3961 "name": "PA_SC_VPORT_ZMAX_8" 3962 }, 3963 { 3964 "chips": ["gfx10"], 3965 "map": {"at": 164632, "to": "mm"}, 3966 "name": "PA_SC_VPORT_ZMIN_9" 3967 }, 3968 { 3969 "chips": ["gfx10"], 3970 "map": {"at": 164636, "to": "mm"}, 3971 "name": "PA_SC_VPORT_ZMAX_9" 3972 }, 3973 { 3974 "chips": ["gfx10"], 3975 "map": {"at": 164640, "to": "mm"}, 3976 "name": "PA_SC_VPORT_ZMIN_10" 3977 }, 3978 { 3979 "chips": ["gfx10"], 3980 "map": {"at": 164644, "to": "mm"}, 3981 "name": "PA_SC_VPORT_ZMAX_10" 3982 }, 3983 { 3984 "chips": ["gfx10"], 3985 "map": {"at": 164648, "to": "mm"}, 3986 "name": "PA_SC_VPORT_ZMIN_11" 3987 }, 3988 { 3989 "chips": ["gfx10"], 3990 "map": {"at": 164652, "to": "mm"}, 3991 "name": "PA_SC_VPORT_ZMAX_11" 3992 }, 3993 { 3994 "chips": ["gfx10"], 3995 "map": {"at": 164656, "to": "mm"}, 3996 "name": "PA_SC_VPORT_ZMIN_12" 3997 }, 3998 { 3999 "chips": ["gfx10"], 4000 "map": {"at": 164660, "to": "mm"}, 4001 "name": "PA_SC_VPORT_ZMAX_12" 4002 }, 4003 { 4004 "chips": ["gfx10"], 4005 "map": {"at": 164664, "to": "mm"}, 4006 "name": "PA_SC_VPORT_ZMIN_13" 4007 }, 4008 { 4009 "chips": ["gfx10"], 4010 "map": {"at": 164668, "to": "mm"}, 4011 "name": "PA_SC_VPORT_ZMAX_13" 4012 }, 4013 { 4014 "chips": ["gfx10"], 4015 "map": {"at": 164672, "to": "mm"}, 4016 "name": "PA_SC_VPORT_ZMIN_14" 4017 }, 4018 { 4019 "chips": ["gfx10"], 4020 "map": {"at": 164676, "to": "mm"}, 4021 "name": "PA_SC_VPORT_ZMAX_14" 4022 }, 4023 { 4024 "chips": ["gfx10"], 4025 "map": {"at": 164680, "to": "mm"}, 4026 "name": "PA_SC_VPORT_ZMIN_15" 4027 }, 4028 { 4029 "chips": ["gfx10"], 4030 "map": {"at": 164684, "to": "mm"}, 4031 "name": "PA_SC_VPORT_ZMAX_15" 4032 }, 4033 { 4034 "chips": ["gfx10"], 4035 "map": {"at": 164688, "to": "mm"}, 4036 "name": "PA_SC_RASTER_CONFIG", 4037 "type_ref": "PA_SC_RASTER_CONFIG" 4038 }, 4039 { 4040 "chips": ["gfx10"], 4041 "map": {"at": 164692, "to": "mm"}, 4042 "name": "PA_SC_RASTER_CONFIG_1", 4043 "type_ref": "PA_SC_RASTER_CONFIG_1" 4044 }, 4045 { 4046 "chips": ["gfx10"], 4047 "map": {"at": 164696, "to": "mm"}, 4048 "name": "PA_SC_SCREEN_EXTENT_CONTROL", 4049 "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL" 4050 }, 4051 { 4052 "chips": ["gfx10"], 4053 "map": {"at": 164700, "to": "mm"}, 4054 "name": "PA_SC_TILE_STEERING_OVERRIDE", 4055 "type_ref": "PA_SC_TILE_STEERING_OVERRIDE" 4056 }, 4057 { 4058 "chips": ["gfx10"], 4059 "map": {"at": 164704, "to": "mm"}, 4060 "name": "CP_PERFMON_CNTX_CNTL", 4061 "type_ref": "CP_PERFMON_CNTX_CNTL" 4062 }, 4063 { 4064 "chips": ["gfx10"], 4065 "map": {"at": 164708, "to": "mm"}, 4066 "name": "CP_PIPEID", 4067 "type_ref": "CP_PIPEID" 4068 }, 4069 { 4070 "chips": ["gfx10"], 4071 "map": {"at": 164712, "to": "mm"}, 4072 "name": "CP_VMID", 4073 "type_ref": "CP_VMID" 4074 }, 4075 { 4076 "chips": ["gfx10"], 4077 "map": {"at": 164768, "to": "mm"}, 4078 "name": "PA_SC_RIGHT_VERT_GRID", 4079 "type_ref": "PA_SC_RIGHT_VERT_GRID" 4080 }, 4081 { 4082 "chips": ["gfx10"], 4083 "map": {"at": 164772, "to": "mm"}, 4084 "name": "PA_SC_LEFT_VERT_GRID", 4085 "type_ref": "PA_SC_RIGHT_VERT_GRID" 4086 }, 4087 { 4088 "chips": ["gfx10"], 4089 "map": {"at": 164776, "to": "mm"}, 4090 "name": "PA_SC_HORIZ_GRID", 4091 "type_ref": "PA_SC_HORIZ_GRID" 4092 }, 4093 { 4094 "chips": ["gfx10"], 4095 "map": {"at": 164864, "to": "mm"}, 4096 "name": "VGT_MAX_VTX_INDX" 4097 }, 4098 { 4099 "chips": ["gfx10"], 4100 "map": {"at": 164868, "to": "mm"}, 4101 "name": "VGT_MIN_VTX_INDX" 4102 }, 4103 { 4104 "chips": ["gfx10"], 4105 "map": {"at": 164872, "to": "mm"}, 4106 "name": "VGT_INDX_OFFSET" 4107 }, 4108 { 4109 "chips": ["gfx10"], 4110 "map": {"at": 164876, "to": "mm"}, 4111 "name": "VGT_MULTI_PRIM_IB_RESET_INDX" 4112 }, 4113 { 4114 "chips": ["gfx10"], 4115 "map": {"at": 164880, "to": "mm"}, 4116 "name": "CB_RMI_GL2_CACHE_CONTROL", 4117 "type_ref": "CB_RMI_GL2_CACHE_CONTROL" 4118 }, 4119 { 4120 "chips": ["gfx10"], 4121 "map": {"at": 164884, "to": "mm"}, 4122 "name": "CB_BLEND_RED" 4123 }, 4124 { 4125 "chips": ["gfx10"], 4126 "map": {"at": 164888, "to": "mm"}, 4127 "name": "CB_BLEND_GREEN" 4128 }, 4129 { 4130 "chips": ["gfx10"], 4131 "map": {"at": 164892, "to": "mm"}, 4132 "name": "CB_BLEND_BLUE" 4133 }, 4134 { 4135 "chips": ["gfx10"], 4136 "map": {"at": 164896, "to": "mm"}, 4137 "name": "CB_BLEND_ALPHA" 4138 }, 4139 { 4140 "chips": ["gfx10"], 4141 "map": {"at": 164900, "to": "mm"}, 4142 "name": "CB_DCC_CONTROL", 4143 "type_ref": "CB_DCC_CONTROL" 4144 }, 4145 { 4146 "chips": ["gfx10"], 4147 "map": {"at": 164904, "to": "mm"}, 4148 "name": "CB_COVERAGE_OUT_CONTROL", 4149 "type_ref": "CB_COVERAGE_OUT_CONTROL" 4150 }, 4151 { 4152 "chips": ["gfx10"], 4153 "map": {"at": 164908, "to": "mm"}, 4154 "name": "DB_STENCIL_CONTROL", 4155 "type_ref": "DB_STENCIL_CONTROL" 4156 }, 4157 { 4158 "chips": ["gfx10"], 4159 "map": {"at": 164912, "to": "mm"}, 4160 "name": "DB_STENCILREFMASK", 4161 "type_ref": "DB_STENCILREFMASK" 4162 }, 4163 { 4164 "chips": ["gfx10"], 4165 "map": {"at": 164916, "to": "mm"}, 4166 "name": "DB_STENCILREFMASK_BF", 4167 "type_ref": "DB_STENCILREFMASK_BF" 4168 }, 4169 { 4170 "chips": ["gfx10"], 4171 "map": {"at": 164924, "to": "mm"}, 4172 "name": "PA_CL_VPORT_XSCALE" 4173 }, 4174 { 4175 "chips": ["gfx10"], 4176 "map": {"at": 164928, "to": "mm"}, 4177 "name": "PA_CL_VPORT_XOFFSET" 4178 }, 4179 { 4180 "chips": ["gfx10"], 4181 "map": {"at": 164932, "to": "mm"}, 4182 "name": "PA_CL_VPORT_YSCALE" 4183 }, 4184 { 4185 "chips": ["gfx10"], 4186 "map": {"at": 164936, "to": "mm"}, 4187 "name": "PA_CL_VPORT_YOFFSET" 4188 }, 4189 { 4190 "chips": ["gfx10"], 4191 "map": {"at": 164940, "to": "mm"}, 4192 "name": "PA_CL_VPORT_ZSCALE" 4193 }, 4194 { 4195 "chips": ["gfx10"], 4196 "map": {"at": 164944, "to": "mm"}, 4197 "name": "PA_CL_VPORT_ZOFFSET" 4198 }, 4199 { 4200 "chips": ["gfx10"], 4201 "map": {"at": 164948, "to": "mm"}, 4202 "name": "PA_CL_VPORT_XSCALE_1" 4203 }, 4204 { 4205 "chips": ["gfx10"], 4206 "map": {"at": 164952, "to": "mm"}, 4207 "name": "PA_CL_VPORT_XOFFSET_1" 4208 }, 4209 { 4210 "chips": ["gfx10"], 4211 "map": {"at": 164956, "to": "mm"}, 4212 "name": "PA_CL_VPORT_YSCALE_1" 4213 }, 4214 { 4215 "chips": ["gfx10"], 4216 "map": {"at": 164960, "to": "mm"}, 4217 "name": "PA_CL_VPORT_YOFFSET_1" 4218 }, 4219 { 4220 "chips": ["gfx10"], 4221 "map": {"at": 164964, "to": "mm"}, 4222 "name": "PA_CL_VPORT_ZSCALE_1" 4223 }, 4224 { 4225 "chips": ["gfx10"], 4226 "map": {"at": 164968, "to": "mm"}, 4227 "name": "PA_CL_VPORT_ZOFFSET_1" 4228 }, 4229 { 4230 "chips": ["gfx10"], 4231 "map": {"at": 164972, "to": "mm"}, 4232 "name": "PA_CL_VPORT_XSCALE_2" 4233 }, 4234 { 4235 "chips": ["gfx10"], 4236 "map": {"at": 164976, "to": "mm"}, 4237 "name": "PA_CL_VPORT_XOFFSET_2" 4238 }, 4239 { 4240 "chips": ["gfx10"], 4241 "map": {"at": 164980, "to": "mm"}, 4242 "name": "PA_CL_VPORT_YSCALE_2" 4243 }, 4244 { 4245 "chips": ["gfx10"], 4246 "map": {"at": 164984, "to": "mm"}, 4247 "name": "PA_CL_VPORT_YOFFSET_2" 4248 }, 4249 { 4250 "chips": ["gfx10"], 4251 "map": {"at": 164988, "to": "mm"}, 4252 "name": "PA_CL_VPORT_ZSCALE_2" 4253 }, 4254 { 4255 "chips": ["gfx10"], 4256 "map": {"at": 164992, "to": "mm"}, 4257 "name": "PA_CL_VPORT_ZOFFSET_2" 4258 }, 4259 { 4260 "chips": ["gfx10"], 4261 "map": {"at": 164996, "to": "mm"}, 4262 "name": "PA_CL_VPORT_XSCALE_3" 4263 }, 4264 { 4265 "chips": ["gfx10"], 4266 "map": {"at": 165000, "to": "mm"}, 4267 "name": "PA_CL_VPORT_XOFFSET_3" 4268 }, 4269 { 4270 "chips": ["gfx10"], 4271 "map": {"at": 165004, "to": "mm"}, 4272 "name": "PA_CL_VPORT_YSCALE_3" 4273 }, 4274 { 4275 "chips": ["gfx10"], 4276 "map": {"at": 165008, "to": "mm"}, 4277 "name": "PA_CL_VPORT_YOFFSET_3" 4278 }, 4279 { 4280 "chips": ["gfx10"], 4281 "map": {"at": 165012, "to": "mm"}, 4282 "name": "PA_CL_VPORT_ZSCALE_3" 4283 }, 4284 { 4285 "chips": ["gfx10"], 4286 "map": {"at": 165016, "to": "mm"}, 4287 "name": "PA_CL_VPORT_ZOFFSET_3" 4288 }, 4289 { 4290 "chips": ["gfx10"], 4291 "map": {"at": 165020, "to": "mm"}, 4292 "name": "PA_CL_VPORT_XSCALE_4" 4293 }, 4294 { 4295 "chips": ["gfx10"], 4296 "map": {"at": 165024, "to": "mm"}, 4297 "name": "PA_CL_VPORT_XOFFSET_4" 4298 }, 4299 { 4300 "chips": ["gfx10"], 4301 "map": {"at": 165028, "to": "mm"}, 4302 "name": "PA_CL_VPORT_YSCALE_4" 4303 }, 4304 { 4305 "chips": ["gfx10"], 4306 "map": {"at": 165032, "to": "mm"}, 4307 "name": "PA_CL_VPORT_YOFFSET_4" 4308 }, 4309 { 4310 "chips": ["gfx10"], 4311 "map": {"at": 165036, "to": "mm"}, 4312 "name": "PA_CL_VPORT_ZSCALE_4" 4313 }, 4314 { 4315 "chips": ["gfx10"], 4316 "map": {"at": 165040, "to": "mm"}, 4317 "name": "PA_CL_VPORT_ZOFFSET_4" 4318 }, 4319 { 4320 "chips": ["gfx10"], 4321 "map": {"at": 165044, "to": "mm"}, 4322 "name": "PA_CL_VPORT_XSCALE_5" 4323 }, 4324 { 4325 "chips": ["gfx10"], 4326 "map": {"at": 165048, "to": "mm"}, 4327 "name": "PA_CL_VPORT_XOFFSET_5" 4328 }, 4329 { 4330 "chips": ["gfx10"], 4331 "map": {"at": 165052, "to": "mm"}, 4332 "name": "PA_CL_VPORT_YSCALE_5" 4333 }, 4334 { 4335 "chips": ["gfx10"], 4336 "map": {"at": 165056, "to": "mm"}, 4337 "name": "PA_CL_VPORT_YOFFSET_5" 4338 }, 4339 { 4340 "chips": ["gfx10"], 4341 "map": {"at": 165060, "to": "mm"}, 4342 "name": "PA_CL_VPORT_ZSCALE_5" 4343 }, 4344 { 4345 "chips": ["gfx10"], 4346 "map": {"at": 165064, "to": "mm"}, 4347 "name": "PA_CL_VPORT_ZOFFSET_5" 4348 }, 4349 { 4350 "chips": ["gfx10"], 4351 "map": {"at": 165068, "to": "mm"}, 4352 "name": "PA_CL_VPORT_XSCALE_6" 4353 }, 4354 { 4355 "chips": ["gfx10"], 4356 "map": {"at": 165072, "to": "mm"}, 4357 "name": "PA_CL_VPORT_XOFFSET_6" 4358 }, 4359 { 4360 "chips": ["gfx10"], 4361 "map": {"at": 165076, "to": "mm"}, 4362 "name": "PA_CL_VPORT_YSCALE_6" 4363 }, 4364 { 4365 "chips": ["gfx10"], 4366 "map": {"at": 165080, "to": "mm"}, 4367 "name": "PA_CL_VPORT_YOFFSET_6" 4368 }, 4369 { 4370 "chips": ["gfx10"], 4371 "map": {"at": 165084, "to": "mm"}, 4372 "name": "PA_CL_VPORT_ZSCALE_6" 4373 }, 4374 { 4375 "chips": ["gfx10"], 4376 "map": {"at": 165088, "to": "mm"}, 4377 "name": "PA_CL_VPORT_ZOFFSET_6" 4378 }, 4379 { 4380 "chips": ["gfx10"], 4381 "map": {"at": 165092, "to": "mm"}, 4382 "name": "PA_CL_VPORT_XSCALE_7" 4383 }, 4384 { 4385 "chips": ["gfx10"], 4386 "map": {"at": 165096, "to": "mm"}, 4387 "name": "PA_CL_VPORT_XOFFSET_7" 4388 }, 4389 { 4390 "chips": ["gfx10"], 4391 "map": {"at": 165100, "to": "mm"}, 4392 "name": "PA_CL_VPORT_YSCALE_7" 4393 }, 4394 { 4395 "chips": ["gfx10"], 4396 "map": {"at": 165104, "to": "mm"}, 4397 "name": "PA_CL_VPORT_YOFFSET_7" 4398 }, 4399 { 4400 "chips": ["gfx10"], 4401 "map": {"at": 165108, "to": "mm"}, 4402 "name": "PA_CL_VPORT_ZSCALE_7" 4403 }, 4404 { 4405 "chips": ["gfx10"], 4406 "map": {"at": 165112, "to": "mm"}, 4407 "name": "PA_CL_VPORT_ZOFFSET_7" 4408 }, 4409 { 4410 "chips": ["gfx10"], 4411 "map": {"at": 165116, "to": "mm"}, 4412 "name": "PA_CL_VPORT_XSCALE_8" 4413 }, 4414 { 4415 "chips": ["gfx10"], 4416 "map": {"at": 165120, "to": "mm"}, 4417 "name": "PA_CL_VPORT_XOFFSET_8" 4418 }, 4419 { 4420 "chips": ["gfx10"], 4421 "map": {"at": 165124, "to": "mm"}, 4422 "name": "PA_CL_VPORT_YSCALE_8" 4423 }, 4424 { 4425 "chips": ["gfx10"], 4426 "map": {"at": 165128, "to": "mm"}, 4427 "name": "PA_CL_VPORT_YOFFSET_8" 4428 }, 4429 { 4430 "chips": ["gfx10"], 4431 "map": {"at": 165132, "to": "mm"}, 4432 "name": "PA_CL_VPORT_ZSCALE_8" 4433 }, 4434 { 4435 "chips": ["gfx10"], 4436 "map": {"at": 165136, "to": "mm"}, 4437 "name": "PA_CL_VPORT_ZOFFSET_8" 4438 }, 4439 { 4440 "chips": ["gfx10"], 4441 "map": {"at": 165140, "to": "mm"}, 4442 "name": "PA_CL_VPORT_XSCALE_9" 4443 }, 4444 { 4445 "chips": ["gfx10"], 4446 "map": {"at": 165144, "to": "mm"}, 4447 "name": "PA_CL_VPORT_XOFFSET_9" 4448 }, 4449 { 4450 "chips": ["gfx10"], 4451 "map": {"at": 165148, "to": "mm"}, 4452 "name": "PA_CL_VPORT_YSCALE_9" 4453 }, 4454 { 4455 "chips": ["gfx10"], 4456 "map": {"at": 165152, "to": "mm"}, 4457 "name": "PA_CL_VPORT_YOFFSET_9" 4458 }, 4459 { 4460 "chips": ["gfx10"], 4461 "map": {"at": 165156, "to": "mm"}, 4462 "name": "PA_CL_VPORT_ZSCALE_9" 4463 }, 4464 { 4465 "chips": ["gfx10"], 4466 "map": {"at": 165160, "to": "mm"}, 4467 "name": "PA_CL_VPORT_ZOFFSET_9" 4468 }, 4469 { 4470 "chips": ["gfx10"], 4471 "map": {"at": 165164, "to": "mm"}, 4472 "name": "PA_CL_VPORT_XSCALE_10" 4473 }, 4474 { 4475 "chips": ["gfx10"], 4476 "map": {"at": 165168, "to": "mm"}, 4477 "name": "PA_CL_VPORT_XOFFSET_10" 4478 }, 4479 { 4480 "chips": ["gfx10"], 4481 "map": {"at": 165172, "to": "mm"}, 4482 "name": "PA_CL_VPORT_YSCALE_10" 4483 }, 4484 { 4485 "chips": ["gfx10"], 4486 "map": {"at": 165176, "to": "mm"}, 4487 "name": "PA_CL_VPORT_YOFFSET_10" 4488 }, 4489 { 4490 "chips": ["gfx10"], 4491 "map": {"at": 165180, "to": "mm"}, 4492 "name": "PA_CL_VPORT_ZSCALE_10" 4493 }, 4494 { 4495 "chips": ["gfx10"], 4496 "map": {"at": 165184, "to": "mm"}, 4497 "name": "PA_CL_VPORT_ZOFFSET_10" 4498 }, 4499 { 4500 "chips": ["gfx10"], 4501 "map": {"at": 165188, "to": "mm"}, 4502 "name": "PA_CL_VPORT_XSCALE_11" 4503 }, 4504 { 4505 "chips": ["gfx10"], 4506 "map": {"at": 165192, "to": "mm"}, 4507 "name": "PA_CL_VPORT_XOFFSET_11" 4508 }, 4509 { 4510 "chips": ["gfx10"], 4511 "map": {"at": 165196, "to": "mm"}, 4512 "name": "PA_CL_VPORT_YSCALE_11" 4513 }, 4514 { 4515 "chips": ["gfx10"], 4516 "map": {"at": 165200, "to": "mm"}, 4517 "name": "PA_CL_VPORT_YOFFSET_11" 4518 }, 4519 { 4520 "chips": ["gfx10"], 4521 "map": {"at": 165204, "to": "mm"}, 4522 "name": "PA_CL_VPORT_ZSCALE_11" 4523 }, 4524 { 4525 "chips": ["gfx10"], 4526 "map": {"at": 165208, "to": "mm"}, 4527 "name": "PA_CL_VPORT_ZOFFSET_11" 4528 }, 4529 { 4530 "chips": ["gfx10"], 4531 "map": {"at": 165212, "to": "mm"}, 4532 "name": "PA_CL_VPORT_XSCALE_12" 4533 }, 4534 { 4535 "chips": ["gfx10"], 4536 "map": {"at": 165216, "to": "mm"}, 4537 "name": "PA_CL_VPORT_XOFFSET_12" 4538 }, 4539 { 4540 "chips": ["gfx10"], 4541 "map": {"at": 165220, "to": "mm"}, 4542 "name": "PA_CL_VPORT_YSCALE_12" 4543 }, 4544 { 4545 "chips": ["gfx10"], 4546 "map": {"at": 165224, "to": "mm"}, 4547 "name": "PA_CL_VPORT_YOFFSET_12" 4548 }, 4549 { 4550 "chips": ["gfx10"], 4551 "map": {"at": 165228, "to": "mm"}, 4552 "name": "PA_CL_VPORT_ZSCALE_12" 4553 }, 4554 { 4555 "chips": ["gfx10"], 4556 "map": {"at": 165232, "to": "mm"}, 4557 "name": "PA_CL_VPORT_ZOFFSET_12" 4558 }, 4559 { 4560 "chips": ["gfx10"], 4561 "map": {"at": 165236, "to": "mm"}, 4562 "name": "PA_CL_VPORT_XSCALE_13" 4563 }, 4564 { 4565 "chips": ["gfx10"], 4566 "map": {"at": 165240, "to": "mm"}, 4567 "name": "PA_CL_VPORT_XOFFSET_13" 4568 }, 4569 { 4570 "chips": ["gfx10"], 4571 "map": {"at": 165244, "to": "mm"}, 4572 "name": "PA_CL_VPORT_YSCALE_13" 4573 }, 4574 { 4575 "chips": ["gfx10"], 4576 "map": {"at": 165248, "to": "mm"}, 4577 "name": "PA_CL_VPORT_YOFFSET_13" 4578 }, 4579 { 4580 "chips": ["gfx10"], 4581 "map": {"at": 165252, "to": "mm"}, 4582 "name": "PA_CL_VPORT_ZSCALE_13" 4583 }, 4584 { 4585 "chips": ["gfx10"], 4586 "map": {"at": 165256, "to": "mm"}, 4587 "name": "PA_CL_VPORT_ZOFFSET_13" 4588 }, 4589 { 4590 "chips": ["gfx10"], 4591 "map": {"at": 165260, "to": "mm"}, 4592 "name": "PA_CL_VPORT_XSCALE_14" 4593 }, 4594 { 4595 "chips": ["gfx10"], 4596 "map": {"at": 165264, "to": "mm"}, 4597 "name": "PA_CL_VPORT_XOFFSET_14" 4598 }, 4599 { 4600 "chips": ["gfx10"], 4601 "map": {"at": 165268, "to": "mm"}, 4602 "name": "PA_CL_VPORT_YSCALE_14" 4603 }, 4604 { 4605 "chips": ["gfx10"], 4606 "map": {"at": 165272, "to": "mm"}, 4607 "name": "PA_CL_VPORT_YOFFSET_14" 4608 }, 4609 { 4610 "chips": ["gfx10"], 4611 "map": {"at": 165276, "to": "mm"}, 4612 "name": "PA_CL_VPORT_ZSCALE_14" 4613 }, 4614 { 4615 "chips": ["gfx10"], 4616 "map": {"at": 165280, "to": "mm"}, 4617 "name": "PA_CL_VPORT_ZOFFSET_14" 4618 }, 4619 { 4620 "chips": ["gfx10"], 4621 "map": {"at": 165284, "to": "mm"}, 4622 "name": "PA_CL_VPORT_XSCALE_15" 4623 }, 4624 { 4625 "chips": ["gfx10"], 4626 "map": {"at": 165288, "to": "mm"}, 4627 "name": "PA_CL_VPORT_XOFFSET_15" 4628 }, 4629 { 4630 "chips": ["gfx10"], 4631 "map": {"at": 165292, "to": "mm"}, 4632 "name": "PA_CL_VPORT_YSCALE_15" 4633 }, 4634 { 4635 "chips": ["gfx10"], 4636 "map": {"at": 165296, "to": "mm"}, 4637 "name": "PA_CL_VPORT_YOFFSET_15" 4638 }, 4639 { 4640 "chips": ["gfx10"], 4641 "map": {"at": 165300, "to": "mm"}, 4642 "name": "PA_CL_VPORT_ZSCALE_15" 4643 }, 4644 { 4645 "chips": ["gfx10"], 4646 "map": {"at": 165304, "to": "mm"}, 4647 "name": "PA_CL_VPORT_ZOFFSET_15" 4648 }, 4649 { 4650 "chips": ["gfx10"], 4651 "map": {"at": 165308, "to": "mm"}, 4652 "name": "PA_CL_UCP_0_X" 4653 }, 4654 { 4655 "chips": ["gfx10"], 4656 "map": {"at": 165312, "to": "mm"}, 4657 "name": "PA_CL_UCP_0_Y" 4658 }, 4659 { 4660 "chips": ["gfx10"], 4661 "map": {"at": 165316, "to": "mm"}, 4662 "name": "PA_CL_UCP_0_Z" 4663 }, 4664 { 4665 "chips": ["gfx10"], 4666 "map": {"at": 165320, "to": "mm"}, 4667 "name": "PA_CL_UCP_0_W" 4668 }, 4669 { 4670 "chips": ["gfx10"], 4671 "map": {"at": 165324, "to": "mm"}, 4672 "name": "PA_CL_UCP_1_X" 4673 }, 4674 { 4675 "chips": ["gfx10"], 4676 "map": {"at": 165328, "to": "mm"}, 4677 "name": "PA_CL_UCP_1_Y" 4678 }, 4679 { 4680 "chips": ["gfx10"], 4681 "map": {"at": 165332, "to": "mm"}, 4682 "name": "PA_CL_UCP_1_Z" 4683 }, 4684 { 4685 "chips": ["gfx10"], 4686 "map": {"at": 165336, "to": "mm"}, 4687 "name": "PA_CL_UCP_1_W" 4688 }, 4689 { 4690 "chips": ["gfx10"], 4691 "map": {"at": 165340, "to": "mm"}, 4692 "name": "PA_CL_UCP_2_X" 4693 }, 4694 { 4695 "chips": ["gfx10"], 4696 "map": {"at": 165344, "to": "mm"}, 4697 "name": "PA_CL_UCP_2_Y" 4698 }, 4699 { 4700 "chips": ["gfx10"], 4701 "map": {"at": 165348, "to": "mm"}, 4702 "name": "PA_CL_UCP_2_Z" 4703 }, 4704 { 4705 "chips": ["gfx10"], 4706 "map": {"at": 165352, "to": "mm"}, 4707 "name": "PA_CL_UCP_2_W" 4708 }, 4709 { 4710 "chips": ["gfx10"], 4711 "map": {"at": 165356, "to": "mm"}, 4712 "name": "PA_CL_UCP_3_X" 4713 }, 4714 { 4715 "chips": ["gfx10"], 4716 "map": {"at": 165360, "to": "mm"}, 4717 "name": "PA_CL_UCP_3_Y" 4718 }, 4719 { 4720 "chips": ["gfx10"], 4721 "map": {"at": 165364, "to": "mm"}, 4722 "name": "PA_CL_UCP_3_Z" 4723 }, 4724 { 4725 "chips": ["gfx10"], 4726 "map": {"at": 165368, "to": "mm"}, 4727 "name": "PA_CL_UCP_3_W" 4728 }, 4729 { 4730 "chips": ["gfx10"], 4731 "map": {"at": 165372, "to": "mm"}, 4732 "name": "PA_CL_UCP_4_X" 4733 }, 4734 { 4735 "chips": ["gfx10"], 4736 "map": {"at": 165376, "to": "mm"}, 4737 "name": "PA_CL_UCP_4_Y" 4738 }, 4739 { 4740 "chips": ["gfx10"], 4741 "map": {"at": 165380, "to": "mm"}, 4742 "name": "PA_CL_UCP_4_Z" 4743 }, 4744 { 4745 "chips": ["gfx10"], 4746 "map": {"at": 165384, "to": "mm"}, 4747 "name": "PA_CL_UCP_4_W" 4748 }, 4749 { 4750 "chips": ["gfx10"], 4751 "map": {"at": 165388, "to": "mm"}, 4752 "name": "PA_CL_UCP_5_X" 4753 }, 4754 { 4755 "chips": ["gfx10"], 4756 "map": {"at": 165392, "to": "mm"}, 4757 "name": "PA_CL_UCP_5_Y" 4758 }, 4759 { 4760 "chips": ["gfx10"], 4761 "map": {"at": 165396, "to": "mm"}, 4762 "name": "PA_CL_UCP_5_Z" 4763 }, 4764 { 4765 "chips": ["gfx10"], 4766 "map": {"at": 165400, "to": "mm"}, 4767 "name": "PA_CL_UCP_5_W" 4768 }, 4769 { 4770 "chips": ["gfx10"], 4771 "map": {"at": 165404, "to": "mm"}, 4772 "name": "PA_CL_PROG_NEAR_CLIP_Z" 4773 }, 4774 { 4775 "chips": ["gfx10"], 4776 "map": {"at": 165444, "to": "mm"}, 4777 "name": "SPI_PS_INPUT_CNTL_0", 4778 "type_ref": "SPI_PS_INPUT_CNTL_0" 4779 }, 4780 { 4781 "chips": ["gfx10"], 4782 "map": {"at": 165448, "to": "mm"}, 4783 "name": "SPI_PS_INPUT_CNTL_1", 4784 "type_ref": "SPI_PS_INPUT_CNTL_0" 4785 }, 4786 { 4787 "chips": ["gfx10"], 4788 "map": {"at": 165452, "to": "mm"}, 4789 "name": "SPI_PS_INPUT_CNTL_2", 4790 "type_ref": "SPI_PS_INPUT_CNTL_0" 4791 }, 4792 { 4793 "chips": ["gfx10"], 4794 "map": {"at": 165456, "to": "mm"}, 4795 "name": "SPI_PS_INPUT_CNTL_3", 4796 "type_ref": "SPI_PS_INPUT_CNTL_0" 4797 }, 4798 { 4799 "chips": ["gfx10"], 4800 "map": {"at": 165460, "to": "mm"}, 4801 "name": "SPI_PS_INPUT_CNTL_4", 4802 "type_ref": "SPI_PS_INPUT_CNTL_0" 4803 }, 4804 { 4805 "chips": ["gfx10"], 4806 "map": {"at": 165464, "to": "mm"}, 4807 "name": "SPI_PS_INPUT_CNTL_5", 4808 "type_ref": "SPI_PS_INPUT_CNTL_0" 4809 }, 4810 { 4811 "chips": ["gfx10"], 4812 "map": {"at": 165468, "to": "mm"}, 4813 "name": "SPI_PS_INPUT_CNTL_6", 4814 "type_ref": "SPI_PS_INPUT_CNTL_0" 4815 }, 4816 { 4817 "chips": ["gfx10"], 4818 "map": {"at": 165472, "to": "mm"}, 4819 "name": "SPI_PS_INPUT_CNTL_7", 4820 "type_ref": "SPI_PS_INPUT_CNTL_0" 4821 }, 4822 { 4823 "chips": ["gfx10"], 4824 "map": {"at": 165476, "to": "mm"}, 4825 "name": "SPI_PS_INPUT_CNTL_8", 4826 "type_ref": "SPI_PS_INPUT_CNTL_0" 4827 }, 4828 { 4829 "chips": ["gfx10"], 4830 "map": {"at": 165480, "to": "mm"}, 4831 "name": "SPI_PS_INPUT_CNTL_9", 4832 "type_ref": "SPI_PS_INPUT_CNTL_0" 4833 }, 4834 { 4835 "chips": ["gfx10"], 4836 "map": {"at": 165484, "to": "mm"}, 4837 "name": "SPI_PS_INPUT_CNTL_10", 4838 "type_ref": "SPI_PS_INPUT_CNTL_0" 4839 }, 4840 { 4841 "chips": ["gfx10"], 4842 "map": {"at": 165488, "to": "mm"}, 4843 "name": "SPI_PS_INPUT_CNTL_11", 4844 "type_ref": "SPI_PS_INPUT_CNTL_0" 4845 }, 4846 { 4847 "chips": ["gfx10"], 4848 "map": {"at": 165492, "to": "mm"}, 4849 "name": "SPI_PS_INPUT_CNTL_12", 4850 "type_ref": "SPI_PS_INPUT_CNTL_0" 4851 }, 4852 { 4853 "chips": ["gfx10"], 4854 "map": {"at": 165496, "to": "mm"}, 4855 "name": "SPI_PS_INPUT_CNTL_13", 4856 "type_ref": "SPI_PS_INPUT_CNTL_0" 4857 }, 4858 { 4859 "chips": ["gfx10"], 4860 "map": {"at": 165500, "to": "mm"}, 4861 "name": "SPI_PS_INPUT_CNTL_14", 4862 "type_ref": "SPI_PS_INPUT_CNTL_0" 4863 }, 4864 { 4865 "chips": ["gfx10"], 4866 "map": {"at": 165504, "to": "mm"}, 4867 "name": "SPI_PS_INPUT_CNTL_15", 4868 "type_ref": "SPI_PS_INPUT_CNTL_0" 4869 }, 4870 { 4871 "chips": ["gfx10"], 4872 "map": {"at": 165508, "to": "mm"}, 4873 "name": "SPI_PS_INPUT_CNTL_16", 4874 "type_ref": "SPI_PS_INPUT_CNTL_0" 4875 }, 4876 { 4877 "chips": ["gfx10"], 4878 "map": {"at": 165512, "to": "mm"}, 4879 "name": "SPI_PS_INPUT_CNTL_17", 4880 "type_ref": "SPI_PS_INPUT_CNTL_0" 4881 }, 4882 { 4883 "chips": ["gfx10"], 4884 "map": {"at": 165516, "to": "mm"}, 4885 "name": "SPI_PS_INPUT_CNTL_18", 4886 "type_ref": "SPI_PS_INPUT_CNTL_0" 4887 }, 4888 { 4889 "chips": ["gfx10"], 4890 "map": {"at": 165520, "to": "mm"}, 4891 "name": "SPI_PS_INPUT_CNTL_19", 4892 "type_ref": "SPI_PS_INPUT_CNTL_0" 4893 }, 4894 { 4895 "chips": ["gfx10"], 4896 "map": {"at": 165524, "to": "mm"}, 4897 "name": "SPI_PS_INPUT_CNTL_20", 4898 "type_ref": "SPI_PS_INPUT_CNTL_20" 4899 }, 4900 { 4901 "chips": ["gfx10"], 4902 "map": {"at": 165528, "to": "mm"}, 4903 "name": "SPI_PS_INPUT_CNTL_21", 4904 "type_ref": "SPI_PS_INPUT_CNTL_20" 4905 }, 4906 { 4907 "chips": ["gfx10"], 4908 "map": {"at": 165532, "to": "mm"}, 4909 "name": "SPI_PS_INPUT_CNTL_22", 4910 "type_ref": "SPI_PS_INPUT_CNTL_20" 4911 }, 4912 { 4913 "chips": ["gfx10"], 4914 "map": {"at": 165536, "to": "mm"}, 4915 "name": "SPI_PS_INPUT_CNTL_23", 4916 "type_ref": "SPI_PS_INPUT_CNTL_20" 4917 }, 4918 { 4919 "chips": ["gfx10"], 4920 "map": {"at": 165540, "to": "mm"}, 4921 "name": "SPI_PS_INPUT_CNTL_24", 4922 "type_ref": "SPI_PS_INPUT_CNTL_20" 4923 }, 4924 { 4925 "chips": ["gfx10"], 4926 "map": {"at": 165544, "to": "mm"}, 4927 "name": "SPI_PS_INPUT_CNTL_25", 4928 "type_ref": "SPI_PS_INPUT_CNTL_20" 4929 }, 4930 { 4931 "chips": ["gfx10"], 4932 "map": {"at": 165548, "to": "mm"}, 4933 "name": "SPI_PS_INPUT_CNTL_26", 4934 "type_ref": "SPI_PS_INPUT_CNTL_20" 4935 }, 4936 { 4937 "chips": ["gfx10"], 4938 "map": {"at": 165552, "to": "mm"}, 4939 "name": "SPI_PS_INPUT_CNTL_27", 4940 "type_ref": "SPI_PS_INPUT_CNTL_20" 4941 }, 4942 { 4943 "chips": ["gfx10"], 4944 "map": {"at": 165556, "to": "mm"}, 4945 "name": "SPI_PS_INPUT_CNTL_28", 4946 "type_ref": "SPI_PS_INPUT_CNTL_20" 4947 }, 4948 { 4949 "chips": ["gfx10"], 4950 "map": {"at": 165560, "to": "mm"}, 4951 "name": "SPI_PS_INPUT_CNTL_29", 4952 "type_ref": "SPI_PS_INPUT_CNTL_20" 4953 }, 4954 { 4955 "chips": ["gfx10"], 4956 "map": {"at": 165564, "to": "mm"}, 4957 "name": "SPI_PS_INPUT_CNTL_30", 4958 "type_ref": "SPI_PS_INPUT_CNTL_20" 4959 }, 4960 { 4961 "chips": ["gfx10"], 4962 "map": {"at": 165568, "to": "mm"}, 4963 "name": "SPI_PS_INPUT_CNTL_31", 4964 "type_ref": "SPI_PS_INPUT_CNTL_20" 4965 }, 4966 { 4967 "chips": ["gfx10"], 4968 "map": {"at": 165572, "to": "mm"}, 4969 "name": "SPI_VS_OUT_CONFIG", 4970 "type_ref": "SPI_VS_OUT_CONFIG" 4971 }, 4972 { 4973 "chips": ["gfx10"], 4974 "map": {"at": 165580, "to": "mm"}, 4975 "name": "SPI_PS_INPUT_ENA", 4976 "type_ref": "SPI_PS_INPUT_ENA" 4977 }, 4978 { 4979 "chips": ["gfx10"], 4980 "map": {"at": 165584, "to": "mm"}, 4981 "name": "SPI_PS_INPUT_ADDR", 4982 "type_ref": "SPI_PS_INPUT_ENA" 4983 }, 4984 { 4985 "chips": ["gfx10"], 4986 "map": {"at": 165588, "to": "mm"}, 4987 "name": "SPI_INTERP_CONTROL_0", 4988 "type_ref": "SPI_INTERP_CONTROL_0" 4989 }, 4990 { 4991 "chips": ["gfx10"], 4992 "map": {"at": 165592, "to": "mm"}, 4993 "name": "SPI_PS_IN_CONTROL", 4994 "type_ref": "SPI_PS_IN_CONTROL" 4995 }, 4996 { 4997 "chips": ["gfx10"], 4998 "map": {"at": 165600, "to": "mm"}, 4999 "name": "SPI_BARYC_CNTL", 5000 "type_ref": "SPI_BARYC_CNTL" 5001 }, 5002 { 5003 "chips": ["gfx10"], 5004 "map": {"at": 165608, "to": "mm"}, 5005 "name": "SPI_TMPRING_SIZE", 5006 "type_ref": "COMPUTE_TMPRING_SIZE" 5007 }, 5008 { 5009 "chips": ["gfx10"], 5010 "map": {"at": 165640, "to": "mm"}, 5011 "name": "SPI_SHADER_IDX_FORMAT", 5012 "type_ref": "SPI_SHADER_IDX_FORMAT" 5013 }, 5014 { 5015 "chips": ["gfx10"], 5016 "map": {"at": 165644, "to": "mm"}, 5017 "name": "SPI_SHADER_POS_FORMAT", 5018 "type_ref": "SPI_SHADER_POS_FORMAT" 5019 }, 5020 { 5021 "chips": ["gfx10"], 5022 "map": {"at": 165648, "to": "mm"}, 5023 "name": "SPI_SHADER_Z_FORMAT", 5024 "type_ref": "SPI_SHADER_Z_FORMAT" 5025 }, 5026 { 5027 "chips": ["gfx10"], 5028 "map": {"at": 165652, "to": "mm"}, 5029 "name": "SPI_SHADER_COL_FORMAT", 5030 "type_ref": "SPI_SHADER_COL_FORMAT" 5031 }, 5032 { 5033 "chips": ["gfx10"], 5034 "map": {"at": 165716, "to": "mm"}, 5035 "name": "SX_PS_DOWNCONVERT", 5036 "type_ref": "SX_PS_DOWNCONVERT" 5037 }, 5038 { 5039 "chips": ["gfx10"], 5040 "map": {"at": 165720, "to": "mm"}, 5041 "name": "SX_BLEND_OPT_EPSILON", 5042 "type_ref": "SX_BLEND_OPT_EPSILON" 5043 }, 5044 { 5045 "chips": ["gfx10"], 5046 "map": {"at": 165724, "to": "mm"}, 5047 "name": "SX_BLEND_OPT_CONTROL", 5048 "type_ref": "SX_BLEND_OPT_CONTROL" 5049 }, 5050 { 5051 "chips": ["gfx10"], 5052 "map": {"at": 165728, "to": "mm"}, 5053 "name": "SX_MRT0_BLEND_OPT", 5054 "type_ref": "SX_MRT0_BLEND_OPT" 5055 }, 5056 { 5057 "chips": ["gfx10"], 5058 "map": {"at": 165732, "to": "mm"}, 5059 "name": "SX_MRT1_BLEND_OPT", 5060 "type_ref": "SX_MRT0_BLEND_OPT" 5061 }, 5062 { 5063 "chips": ["gfx10"], 5064 "map": {"at": 165736, "to": "mm"}, 5065 "name": "SX_MRT2_BLEND_OPT", 5066 "type_ref": "SX_MRT0_BLEND_OPT" 5067 }, 5068 { 5069 "chips": ["gfx10"], 5070 "map": {"at": 165740, "to": "mm"}, 5071 "name": "SX_MRT3_BLEND_OPT", 5072 "type_ref": "SX_MRT0_BLEND_OPT" 5073 }, 5074 { 5075 "chips": ["gfx10"], 5076 "map": {"at": 165744, "to": "mm"}, 5077 "name": "SX_MRT4_BLEND_OPT", 5078 "type_ref": "SX_MRT0_BLEND_OPT" 5079 }, 5080 { 5081 "chips": ["gfx10"], 5082 "map": {"at": 165748, "to": "mm"}, 5083 "name": "SX_MRT5_BLEND_OPT", 5084 "type_ref": "SX_MRT0_BLEND_OPT" 5085 }, 5086 { 5087 "chips": ["gfx10"], 5088 "map": {"at": 165752, "to": "mm"}, 5089 "name": "SX_MRT6_BLEND_OPT", 5090 "type_ref": "SX_MRT0_BLEND_OPT" 5091 }, 5092 { 5093 "chips": ["gfx10"], 5094 "map": {"at": 165756, "to": "mm"}, 5095 "name": "SX_MRT7_BLEND_OPT", 5096 "type_ref": "SX_MRT0_BLEND_OPT" 5097 }, 5098 { 5099 "chips": ["gfx10"], 5100 "map": {"at": 165760, "to": "mm"}, 5101 "name": "CB_BLEND0_CONTROL", 5102 "type_ref": "CB_BLEND0_CONTROL" 5103 }, 5104 { 5105 "chips": ["gfx10"], 5106 "map": {"at": 165764, "to": "mm"}, 5107 "name": "CB_BLEND1_CONTROL", 5108 "type_ref": "CB_BLEND0_CONTROL" 5109 }, 5110 { 5111 "chips": ["gfx10"], 5112 "map": {"at": 165768, "to": "mm"}, 5113 "name": "CB_BLEND2_CONTROL", 5114 "type_ref": "CB_BLEND0_CONTROL" 5115 }, 5116 { 5117 "chips": ["gfx10"], 5118 "map": {"at": 165772, "to": "mm"}, 5119 "name": "CB_BLEND3_CONTROL", 5120 "type_ref": "CB_BLEND0_CONTROL" 5121 }, 5122 { 5123 "chips": ["gfx10"], 5124 "map": {"at": 165776, "to": "mm"}, 5125 "name": "CB_BLEND4_CONTROL", 5126 "type_ref": "CB_BLEND0_CONTROL" 5127 }, 5128 { 5129 "chips": ["gfx10"], 5130 "map": {"at": 165780, "to": "mm"}, 5131 "name": "CB_BLEND5_CONTROL", 5132 "type_ref": "CB_BLEND0_CONTROL" 5133 }, 5134 { 5135 "chips": ["gfx10"], 5136 "map": {"at": 165784, "to": "mm"}, 5137 "name": "CB_BLEND6_CONTROL", 5138 "type_ref": "CB_BLEND0_CONTROL" 5139 }, 5140 { 5141 "chips": ["gfx10"], 5142 "map": {"at": 165788, "to": "mm"}, 5143 "name": "CB_BLEND7_CONTROL", 5144 "type_ref": "CB_BLEND0_CONTROL" 5145 }, 5146 { 5147 "chips": ["gfx10"], 5148 "map": {"at": 165836, "to": "mm"}, 5149 "name": "CS_COPY_STATE", 5150 "type_ref": "CS_COPY_STATE" 5151 }, 5152 { 5153 "chips": ["gfx10"], 5154 "map": {"at": 165840, "to": "mm"}, 5155 "name": "GFX_COPY_STATE", 5156 "type_ref": "CS_COPY_STATE" 5157 }, 5158 { 5159 "chips": ["gfx10"], 5160 "map": {"at": 165844, "to": "mm"}, 5161 "name": "PA_CL_POINT_X_RAD" 5162 }, 5163 { 5164 "chips": ["gfx10"], 5165 "map": {"at": 165848, "to": "mm"}, 5166 "name": "PA_CL_POINT_Y_RAD" 5167 }, 5168 { 5169 "chips": ["gfx10"], 5170 "map": {"at": 165852, "to": "mm"}, 5171 "name": "PA_CL_POINT_SIZE" 5172 }, 5173 { 5174 "chips": ["gfx10"], 5175 "map": {"at": 165856, "to": "mm"}, 5176 "name": "PA_CL_POINT_CULL_RAD" 5177 }, 5178 { 5179 "chips": ["gfx10"], 5180 "map": {"at": 165860, "to": "mm"}, 5181 "name": "VGT_DMA_BASE_HI", 5182 "type_ref": "VGT_DMA_BASE_HI" 5183 }, 5184 { 5185 "chips": ["gfx10"], 5186 "map": {"at": 165864, "to": "mm"}, 5187 "name": "VGT_DMA_BASE" 5188 }, 5189 { 5190 "chips": ["gfx10"], 5191 "map": {"at": 165872, "to": "mm"}, 5192 "name": "VGT_DRAW_INITIATOR", 5193 "type_ref": "VGT_DRAW_INITIATOR" 5194 }, 5195 { 5196 "chips": ["gfx10"], 5197 "map": {"at": 165876, "to": "mm"}, 5198 "name": "VGT_IMMED_DATA" 5199 }, 5200 { 5201 "chips": ["gfx10"], 5202 "map": {"at": 165880, "to": "mm"}, 5203 "name": "VGT_EVENT_ADDRESS_REG", 5204 "type_ref": "VGT_EVENT_ADDRESS_REG" 5205 }, 5206 { 5207 "chips": ["gfx10"], 5208 "map": {"at": 165884, "to": "mm"}, 5209 "name": "GE_MAX_OUTPUT_PER_SUBGROUP", 5210 "type_ref": "GE_MAX_OUTPUT_PER_SUBGROUP" 5211 }, 5212 { 5213 "chips": ["gfx10"], 5214 "map": {"at": 165888, "to": "mm"}, 5215 "name": "DB_DEPTH_CONTROL", 5216 "type_ref": "DB_DEPTH_CONTROL" 5217 }, 5218 { 5219 "chips": ["gfx10"], 5220 "map": {"at": 165892, "to": "mm"}, 5221 "name": "DB_EQAA", 5222 "type_ref": "DB_EQAA" 5223 }, 5224 { 5225 "chips": ["gfx10"], 5226 "map": {"at": 165896, "to": "mm"}, 5227 "name": "CB_COLOR_CONTROL", 5228 "type_ref": "CB_COLOR_CONTROL" 5229 }, 5230 { 5231 "chips": ["gfx10"], 5232 "map": {"at": 165900, "to": "mm"}, 5233 "name": "DB_SHADER_CONTROL", 5234 "type_ref": "DB_SHADER_CONTROL" 5235 }, 5236 { 5237 "chips": ["gfx10"], 5238 "map": {"at": 165904, "to": "mm"}, 5239 "name": "PA_CL_CLIP_CNTL", 5240 "type_ref": "PA_CL_CLIP_CNTL" 5241 }, 5242 { 5243 "chips": ["gfx10"], 5244 "map": {"at": 165908, "to": "mm"}, 5245 "name": "PA_SU_SC_MODE_CNTL", 5246 "type_ref": "PA_SU_SC_MODE_CNTL" 5247 }, 5248 { 5249 "chips": ["gfx10"], 5250 "map": {"at": 165912, "to": "mm"}, 5251 "name": "PA_CL_VTE_CNTL", 5252 "type_ref": "PA_CL_VTE_CNTL" 5253 }, 5254 { 5255 "chips": ["gfx10"], 5256 "map": {"at": 165916, "to": "mm"}, 5257 "name": "PA_CL_VS_OUT_CNTL", 5258 "type_ref": "PA_CL_VS_OUT_CNTL" 5259 }, 5260 { 5261 "chips": ["gfx10"], 5262 "map": {"at": 165920, "to": "mm"}, 5263 "name": "PA_CL_NANINF_CNTL", 5264 "type_ref": "PA_CL_NANINF_CNTL" 5265 }, 5266 { 5267 "chips": ["gfx10"], 5268 "map": {"at": 165924, "to": "mm"}, 5269 "name": "PA_SU_LINE_STIPPLE_CNTL", 5270 "type_ref": "PA_SU_LINE_STIPPLE_CNTL" 5271 }, 5272 { 5273 "chips": ["gfx10"], 5274 "map": {"at": 165928, "to": "mm"}, 5275 "name": "PA_SU_LINE_STIPPLE_SCALE" 5276 }, 5277 { 5278 "chips": ["gfx10"], 5279 "map": {"at": 165932, "to": "mm"}, 5280 "name": "PA_SU_PRIM_FILTER_CNTL", 5281 "type_ref": "PA_SU_PRIM_FILTER_CNTL" 5282 }, 5283 { 5284 "chips": ["gfx10"], 5285 "map": {"at": 165936, "to": "mm"}, 5286 "name": "PA_SU_SMALL_PRIM_FILTER_CNTL", 5287 "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL" 5288 }, 5289 { 5290 "chips": ["gfx10"], 5291 "map": {"at": 165940, "to": "mm"}, 5292 "name": "PA_CL_OBJPRIM_ID_CNTL", 5293 "type_ref": "PA_CL_OBJPRIM_ID_CNTL" 5294 }, 5295 { 5296 "chips": ["gfx10"], 5297 "map": {"at": 165944, "to": "mm"}, 5298 "name": "PA_CL_NGG_CNTL", 5299 "type_ref": "PA_CL_NGG_CNTL" 5300 }, 5301 { 5302 "chips": ["gfx10"], 5303 "map": {"at": 165948, "to": "mm"}, 5304 "name": "PA_SU_OVER_RASTERIZATION_CNTL", 5305 "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL" 5306 }, 5307 { 5308 "chips": ["gfx10"], 5309 "map": {"at": 165952, "to": "mm"}, 5310 "name": "PA_STEREO_CNTL", 5311 "type_ref": "PA_STEREO_CNTL" 5312 }, 5313 { 5314 "chips": ["gfx10"], 5315 "map": {"at": 165956, "to": "mm"}, 5316 "name": "PA_STATE_STEREO_X" 5317 }, 5318 { 5319 "chips": ["gfx10"], 5320 "map": {"at": 166400, "to": "mm"}, 5321 "name": "PA_SU_POINT_SIZE", 5322 "type_ref": "PA_SU_POINT_SIZE" 5323 }, 5324 { 5325 "chips": ["gfx10"], 5326 "map": {"at": 166404, "to": "mm"}, 5327 "name": "PA_SU_POINT_MINMAX", 5328 "type_ref": "PA_SU_POINT_MINMAX" 5329 }, 5330 { 5331 "chips": ["gfx10"], 5332 "map": {"at": 166408, "to": "mm"}, 5333 "name": "PA_SU_LINE_CNTL", 5334 "type_ref": "PA_SU_LINE_CNTL" 5335 }, 5336 { 5337 "chips": ["gfx10"], 5338 "map": {"at": 166412, "to": "mm"}, 5339 "name": "PA_SC_LINE_STIPPLE", 5340 "type_ref": "PA_SC_LINE_STIPPLE" 5341 }, 5342 { 5343 "chips": ["gfx10"], 5344 "map": {"at": 166416, "to": "mm"}, 5345 "name": "VGT_OUTPUT_PATH_CNTL", 5346 "type_ref": "VGT_OUTPUT_PATH_CNTL" 5347 }, 5348 { 5349 "chips": ["gfx10"], 5350 "map": {"at": 166420, "to": "mm"}, 5351 "name": "VGT_HOS_CNTL", 5352 "type_ref": "VGT_HOS_CNTL" 5353 }, 5354 { 5355 "chips": ["gfx10"], 5356 "map": {"at": 166424, "to": "mm"}, 5357 "name": "VGT_HOS_MAX_TESS_LEVEL" 5358 }, 5359 { 5360 "chips": ["gfx10"], 5361 "map": {"at": 166428, "to": "mm"}, 5362 "name": "VGT_HOS_MIN_TESS_LEVEL" 5363 }, 5364 { 5365 "chips": ["gfx10"], 5366 "map": {"at": 166432, "to": "mm"}, 5367 "name": "VGT_HOS_REUSE_DEPTH", 5368 "type_ref": "VGT_HOS_REUSE_DEPTH" 5369 }, 5370 { 5371 "chips": ["gfx10"], 5372 "map": {"at": 166436, "to": "mm"}, 5373 "name": "VGT_GROUP_PRIM_TYPE", 5374 "type_ref": "VGT_GROUP_PRIM_TYPE" 5375 }, 5376 { 5377 "chips": ["gfx10"], 5378 "map": {"at": 166440, "to": "mm"}, 5379 "name": "VGT_GROUP_FIRST_DECR", 5380 "type_ref": "VGT_GROUP_FIRST_DECR" 5381 }, 5382 { 5383 "chips": ["gfx10"], 5384 "map": {"at": 166444, "to": "mm"}, 5385 "name": "VGT_GROUP_DECR", 5386 "type_ref": "VGT_GROUP_DECR" 5387 }, 5388 { 5389 "chips": ["gfx10"], 5390 "map": {"at": 166448, "to": "mm"}, 5391 "name": "VGT_GROUP_VECT_0_CNTL", 5392 "type_ref": "VGT_GROUP_VECT_0_CNTL" 5393 }, 5394 { 5395 "chips": ["gfx10"], 5396 "map": {"at": 166452, "to": "mm"}, 5397 "name": "VGT_GROUP_VECT_1_CNTL", 5398 "type_ref": "VGT_GROUP_VECT_0_CNTL" 5399 }, 5400 { 5401 "chips": ["gfx10"], 5402 "map": {"at": 166456, "to": "mm"}, 5403 "name": "VGT_GROUP_VECT_0_FMT_CNTL", 5404 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 5405 }, 5406 { 5407 "chips": ["gfx10"], 5408 "map": {"at": 166460, "to": "mm"}, 5409 "name": "VGT_GROUP_VECT_1_FMT_CNTL", 5410 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 5411 }, 5412 { 5413 "chips": ["gfx10"], 5414 "map": {"at": 166464, "to": "mm"}, 5415 "name": "VGT_GS_MODE", 5416 "type_ref": "VGT_GS_MODE" 5417 }, 5418 { 5419 "chips": ["gfx10"], 5420 "map": {"at": 166468, "to": "mm"}, 5421 "name": "VGT_GS_ONCHIP_CNTL", 5422 "type_ref": "VGT_GS_ONCHIP_CNTL" 5423 }, 5424 { 5425 "chips": ["gfx10"], 5426 "map": {"at": 166472, "to": "mm"}, 5427 "name": "PA_SC_MODE_CNTL_0", 5428 "type_ref": "PA_SC_MODE_CNTL_0" 5429 }, 5430 { 5431 "chips": ["gfx10"], 5432 "map": {"at": 166476, "to": "mm"}, 5433 "name": "PA_SC_MODE_CNTL_1", 5434 "type_ref": "PA_SC_MODE_CNTL_1" 5435 }, 5436 { 5437 "chips": ["gfx10"], 5438 "map": {"at": 166480, "to": "mm"}, 5439 "name": "VGT_ENHANCE" 5440 }, 5441 { 5442 "chips": ["gfx10"], 5443 "map": {"at": 166484, "to": "mm"}, 5444 "name": "VGT_GS_PER_ES", 5445 "type_ref": "VGT_GS_PER_ES" 5446 }, 5447 { 5448 "chips": ["gfx10"], 5449 "map": {"at": 166488, "to": "mm"}, 5450 "name": "VGT_ES_PER_GS", 5451 "type_ref": "VGT_ES_PER_GS" 5452 }, 5453 { 5454 "chips": ["gfx10"], 5455 "map": {"at": 166492, "to": "mm"}, 5456 "name": "VGT_GS_PER_VS", 5457 "type_ref": "VGT_GS_PER_VS" 5458 }, 5459 { 5460 "chips": ["gfx10"], 5461 "map": {"at": 166496, "to": "mm"}, 5462 "name": "VGT_GSVS_RING_OFFSET_1", 5463 "type_ref": "VGT_GSVS_RING_OFFSET_1" 5464 }, 5465 { 5466 "chips": ["gfx10"], 5467 "map": {"at": 166500, "to": "mm"}, 5468 "name": "VGT_GSVS_RING_OFFSET_2", 5469 "type_ref": "VGT_GSVS_RING_OFFSET_1" 5470 }, 5471 { 5472 "chips": ["gfx10"], 5473 "map": {"at": 166504, "to": "mm"}, 5474 "name": "VGT_GSVS_RING_OFFSET_3", 5475 "type_ref": "VGT_GSVS_RING_OFFSET_1" 5476 }, 5477 { 5478 "chips": ["gfx10"], 5479 "map": {"at": 166508, "to": "mm"}, 5480 "name": "VGT_GS_OUT_PRIM_TYPE", 5481 "type_ref": "VGT_GS_OUT_PRIM_TYPE" 5482 }, 5483 { 5484 "chips": ["gfx10"], 5485 "map": {"at": 166512, "to": "mm"}, 5486 "name": "IA_ENHANCE" 5487 }, 5488 { 5489 "chips": ["gfx10"], 5490 "map": {"at": 166516, "to": "mm"}, 5491 "name": "VGT_DMA_SIZE" 5492 }, 5493 { 5494 "chips": ["gfx10"], 5495 "map": {"at": 166520, "to": "mm"}, 5496 "name": "VGT_DMA_MAX_SIZE" 5497 }, 5498 { 5499 "chips": ["gfx10"], 5500 "map": {"at": 166524, "to": "mm"}, 5501 "name": "VGT_DMA_INDEX_TYPE", 5502 "type_ref": "VGT_DMA_INDEX_TYPE" 5503 }, 5504 { 5505 "chips": ["gfx10"], 5506 "map": {"at": 166528, "to": "mm"}, 5507 "name": "WD_ENHANCE" 5508 }, 5509 { 5510 "chips": ["gfx10"], 5511 "map": {"at": 166532, "to": "mm"}, 5512 "name": "VGT_PRIMITIVEID_EN", 5513 "type_ref": "VGT_PRIMITIVEID_EN" 5514 }, 5515 { 5516 "chips": ["gfx10"], 5517 "map": {"at": 166536, "to": "mm"}, 5518 "name": "VGT_DMA_NUM_INSTANCES" 5519 }, 5520 { 5521 "chips": ["gfx10"], 5522 "map": {"at": 166540, "to": "mm"}, 5523 "name": "VGT_PRIMITIVEID_RESET" 5524 }, 5525 { 5526 "chips": ["gfx10"], 5527 "map": {"at": 166544, "to": "mm"}, 5528 "name": "VGT_EVENT_INITIATOR", 5529 "type_ref": "VGT_EVENT_INITIATOR" 5530 }, 5531 { 5532 "chips": ["gfx10"], 5533 "map": {"at": 166548, "to": "mm"}, 5534 "name": "VGT_MULTI_PRIM_IB_RESET_EN", 5535 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN" 5536 }, 5537 { 5538 "chips": ["gfx10"], 5539 "map": {"at": 166552, "to": "mm"}, 5540 "name": "VGT_DRAW_PAYLOAD_CNTL", 5541 "type_ref": "VGT_DRAW_PAYLOAD_CNTL" 5542 }, 5543 { 5544 "chips": ["gfx10"], 5545 "map": {"at": 166560, "to": "mm"}, 5546 "name": "VGT_INSTANCE_STEP_RATE_0" 5547 }, 5548 { 5549 "chips": ["gfx10"], 5550 "map": {"at": 166564, "to": "mm"}, 5551 "name": "VGT_INSTANCE_STEP_RATE_1" 5552 }, 5553 { 5554 "chips": ["gfx10"], 5555 "map": {"at": 166568, "to": "mm"}, 5556 "name": "IA_MULTI_VGT_PARAM", 5557 "type_ref": "IA_MULTI_VGT_PARAM" 5558 }, 5559 { 5560 "chips": ["gfx10"], 5561 "map": {"at": 166572, "to": "mm"}, 5562 "name": "VGT_ESGS_RING_ITEMSIZE", 5563 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5564 }, 5565 { 5566 "chips": ["gfx10"], 5567 "map": {"at": 166576, "to": "mm"}, 5568 "name": "VGT_GSVS_RING_ITEMSIZE", 5569 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5570 }, 5571 { 5572 "chips": ["gfx10"], 5573 "map": {"at": 166580, "to": "mm"}, 5574 "name": "VGT_REUSE_OFF", 5575 "type_ref": "VGT_REUSE_OFF" 5576 }, 5577 { 5578 "chips": ["gfx10"], 5579 "map": {"at": 166584, "to": "mm"}, 5580 "name": "VGT_VTX_CNT_EN", 5581 "type_ref": "VGT_VTX_CNT_EN" 5582 }, 5583 { 5584 "chips": ["gfx10"], 5585 "map": {"at": 166588, "to": "mm"}, 5586 "name": "DB_HTILE_SURFACE", 5587 "type_ref": "DB_HTILE_SURFACE" 5588 }, 5589 { 5590 "chips": ["gfx10"], 5591 "map": {"at": 166592, "to": "mm"}, 5592 "name": "DB_SRESULTS_COMPARE_STATE0", 5593 "type_ref": "DB_SRESULTS_COMPARE_STATE0" 5594 }, 5595 { 5596 "chips": ["gfx10"], 5597 "map": {"at": 166596, "to": "mm"}, 5598 "name": "DB_SRESULTS_COMPARE_STATE1", 5599 "type_ref": "DB_SRESULTS_COMPARE_STATE1" 5600 }, 5601 { 5602 "chips": ["gfx10"], 5603 "map": {"at": 166600, "to": "mm"}, 5604 "name": "DB_PRELOAD_CONTROL", 5605 "type_ref": "DB_PRELOAD_CONTROL" 5606 }, 5607 { 5608 "chips": ["gfx10"], 5609 "map": {"at": 166608, "to": "mm"}, 5610 "name": "VGT_STRMOUT_BUFFER_SIZE_0" 5611 }, 5612 { 5613 "chips": ["gfx10"], 5614 "map": {"at": 166612, "to": "mm"}, 5615 "name": "VGT_STRMOUT_VTX_STRIDE_0", 5616 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 5617 }, 5618 { 5619 "chips": ["gfx10"], 5620 "map": {"at": 166620, "to": "mm"}, 5621 "name": "VGT_STRMOUT_BUFFER_OFFSET_0" 5622 }, 5623 { 5624 "chips": ["gfx10"], 5625 "map": {"at": 166624, "to": "mm"}, 5626 "name": "VGT_STRMOUT_BUFFER_SIZE_1" 5627 }, 5628 { 5629 "chips": ["gfx10"], 5630 "map": {"at": 166628, "to": "mm"}, 5631 "name": "VGT_STRMOUT_VTX_STRIDE_1", 5632 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 5633 }, 5634 { 5635 "chips": ["gfx10"], 5636 "map": {"at": 166636, "to": "mm"}, 5637 "name": "VGT_STRMOUT_BUFFER_OFFSET_1" 5638 }, 5639 { 5640 "chips": ["gfx10"], 5641 "map": {"at": 166640, "to": "mm"}, 5642 "name": "VGT_STRMOUT_BUFFER_SIZE_2" 5643 }, 5644 { 5645 "chips": ["gfx10"], 5646 "map": {"at": 166644, "to": "mm"}, 5647 "name": "VGT_STRMOUT_VTX_STRIDE_2", 5648 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 5649 }, 5650 { 5651 "chips": ["gfx10"], 5652 "map": {"at": 166652, "to": "mm"}, 5653 "name": "VGT_STRMOUT_BUFFER_OFFSET_2" 5654 }, 5655 { 5656 "chips": ["gfx10"], 5657 "map": {"at": 166656, "to": "mm"}, 5658 "name": "VGT_STRMOUT_BUFFER_SIZE_3" 5659 }, 5660 { 5661 "chips": ["gfx10"], 5662 "map": {"at": 166660, "to": "mm"}, 5663 "name": "VGT_STRMOUT_VTX_STRIDE_3", 5664 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 5665 }, 5666 { 5667 "chips": ["gfx10"], 5668 "map": {"at": 166668, "to": "mm"}, 5669 "name": "VGT_STRMOUT_BUFFER_OFFSET_3" 5670 }, 5671 { 5672 "chips": ["gfx10"], 5673 "map": {"at": 166696, "to": "mm"}, 5674 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET" 5675 }, 5676 { 5677 "chips": ["gfx10"], 5678 "map": {"at": 166700, "to": "mm"}, 5679 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE" 5680 }, 5681 { 5682 "chips": ["gfx10"], 5683 "map": {"at": 166704, "to": "mm"}, 5684 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", 5685 "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE" 5686 }, 5687 { 5688 "chips": ["gfx10"], 5689 "map": {"at": 166712, "to": "mm"}, 5690 "name": "VGT_GS_MAX_VERT_OUT", 5691 "type_ref": "VGT_GS_MAX_VERT_OUT" 5692 }, 5693 { 5694 "chips": ["gfx10"], 5695 "map": {"at": 166732, "to": "mm"}, 5696 "name": "GE_NGG_SUBGRP_CNTL", 5697 "type_ref": "GE_NGG_SUBGRP_CNTL" 5698 }, 5699 { 5700 "chips": ["gfx10"], 5701 "map": {"at": 166736, "to": "mm"}, 5702 "name": "VGT_TESS_DISTRIBUTION", 5703 "type_ref": "VGT_TESS_DISTRIBUTION" 5704 }, 5705 { 5706 "chips": ["gfx10"], 5707 "map": {"at": 166740, "to": "mm"}, 5708 "name": "VGT_SHADER_STAGES_EN", 5709 "type_ref": "VGT_SHADER_STAGES_EN" 5710 }, 5711 { 5712 "chips": ["gfx10"], 5713 "map": {"at": 166744, "to": "mm"}, 5714 "name": "VGT_LS_HS_CONFIG", 5715 "type_ref": "VGT_LS_HS_CONFIG" 5716 }, 5717 { 5718 "chips": ["gfx10"], 5719 "map": {"at": 166748, "to": "mm"}, 5720 "name": "VGT_GS_VERT_ITEMSIZE", 5721 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5722 }, 5723 { 5724 "chips": ["gfx10"], 5725 "map": {"at": 166752, "to": "mm"}, 5726 "name": "VGT_GS_VERT_ITEMSIZE_1", 5727 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5728 }, 5729 { 5730 "chips": ["gfx10"], 5731 "map": {"at": 166756, "to": "mm"}, 5732 "name": "VGT_GS_VERT_ITEMSIZE_2", 5733 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5734 }, 5735 { 5736 "chips": ["gfx10"], 5737 "map": {"at": 166760, "to": "mm"}, 5738 "name": "VGT_GS_VERT_ITEMSIZE_3", 5739 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5740 }, 5741 { 5742 "chips": ["gfx10"], 5743 "map": {"at": 166764, "to": "mm"}, 5744 "name": "VGT_TF_PARAM", 5745 "type_ref": "VGT_TF_PARAM" 5746 }, 5747 { 5748 "chips": ["gfx10"], 5749 "map": {"at": 166768, "to": "mm"}, 5750 "name": "DB_ALPHA_TO_MASK", 5751 "type_ref": "DB_ALPHA_TO_MASK" 5752 }, 5753 { 5754 "chips": ["gfx10"], 5755 "map": {"at": 166772, "to": "mm"}, 5756 "name": "VGT_DISPATCH_DRAW_INDEX" 5757 }, 5758 { 5759 "chips": ["gfx10"], 5760 "map": {"at": 166776, "to": "mm"}, 5761 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL", 5762 "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL" 5763 }, 5764 { 5765 "chips": ["gfx10"], 5766 "map": {"at": 166780, "to": "mm"}, 5767 "name": "PA_SU_POLY_OFFSET_CLAMP" 5768 }, 5769 { 5770 "chips": ["gfx10"], 5771 "map": {"at": 166784, "to": "mm"}, 5772 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE" 5773 }, 5774 { 5775 "chips": ["gfx10"], 5776 "map": {"at": 166788, "to": "mm"}, 5777 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET" 5778 }, 5779 { 5780 "chips": ["gfx10"], 5781 "map": {"at": 166792, "to": "mm"}, 5782 "name": "PA_SU_POLY_OFFSET_BACK_SCALE" 5783 }, 5784 { 5785 "chips": ["gfx10"], 5786 "map": {"at": 166796, "to": "mm"}, 5787 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET" 5788 }, 5789 { 5790 "chips": ["gfx10"], 5791 "map": {"at": 166800, "to": "mm"}, 5792 "name": "VGT_GS_INSTANCE_CNT", 5793 "type_ref": "VGT_GS_INSTANCE_CNT" 5794 }, 5795 { 5796 "chips": ["gfx10"], 5797 "map": {"at": 166804, "to": "mm"}, 5798 "name": "VGT_STRMOUT_CONFIG", 5799 "type_ref": "VGT_STRMOUT_CONFIG" 5800 }, 5801 { 5802 "chips": ["gfx10"], 5803 "map": {"at": 166808, "to": "mm"}, 5804 "name": "VGT_STRMOUT_BUFFER_CONFIG", 5805 "type_ref": "VGT_STRMOUT_BUFFER_CONFIG" 5806 }, 5807 { 5808 "chips": ["gfx10"], 5809 "map": {"at": 166812, "to": "mm"}, 5810 "name": "VGT_DMA_EVENT_INITIATOR", 5811 "type_ref": "VGT_EVENT_INITIATOR" 5812 }, 5813 { 5814 "chips": ["gfx10"], 5815 "map": {"at": 166868, "to": "mm"}, 5816 "name": "PA_SC_CENTROID_PRIORITY_0", 5817 "type_ref": "PA_SC_CENTROID_PRIORITY_0" 5818 }, 5819 { 5820 "chips": ["gfx10"], 5821 "map": {"at": 166872, "to": "mm"}, 5822 "name": "PA_SC_CENTROID_PRIORITY_1", 5823 "type_ref": "PA_SC_CENTROID_PRIORITY_1" 5824 }, 5825 { 5826 "chips": ["gfx10"], 5827 "map": {"at": 166876, "to": "mm"}, 5828 "name": "PA_SC_LINE_CNTL", 5829 "type_ref": "PA_SC_LINE_CNTL" 5830 }, 5831 { 5832 "chips": ["gfx10"], 5833 "map": {"at": 166880, "to": "mm"}, 5834 "name": "PA_SC_AA_CONFIG", 5835 "type_ref": "PA_SC_AA_CONFIG" 5836 }, 5837 { 5838 "chips": ["gfx10"], 5839 "map": {"at": 166884, "to": "mm"}, 5840 "name": "PA_SU_VTX_CNTL", 5841 "type_ref": "PA_SU_VTX_CNTL" 5842 }, 5843 { 5844 "chips": ["gfx10"], 5845 "map": {"at": 166888, "to": "mm"}, 5846 "name": "PA_CL_GB_VERT_CLIP_ADJ" 5847 }, 5848 { 5849 "chips": ["gfx10"], 5850 "map": {"at": 166892, "to": "mm"}, 5851 "name": "PA_CL_GB_VERT_DISC_ADJ" 5852 }, 5853 { 5854 "chips": ["gfx10"], 5855 "map": {"at": 166896, "to": "mm"}, 5856 "name": "PA_CL_GB_HORZ_CLIP_ADJ" 5857 }, 5858 { 5859 "chips": ["gfx10"], 5860 "map": {"at": 166900, "to": "mm"}, 5861 "name": "PA_CL_GB_HORZ_DISC_ADJ" 5862 }, 5863 { 5864 "chips": ["gfx10"], 5865 "map": {"at": 166904, "to": "mm"}, 5866 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", 5867 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 5868 }, 5869 { 5870 "chips": ["gfx10"], 5871 "map": {"at": 166908, "to": "mm"}, 5872 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", 5873 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 5874 }, 5875 { 5876 "chips": ["gfx10"], 5877 "map": {"at": 166912, "to": "mm"}, 5878 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", 5879 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 5880 }, 5881 { 5882 "chips": ["gfx10"], 5883 "map": {"at": 166916, "to": "mm"}, 5884 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", 5885 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 5886 }, 5887 { 5888 "chips": ["gfx10"], 5889 "map": {"at": 166920, "to": "mm"}, 5890 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", 5891 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 5892 }, 5893 { 5894 "chips": ["gfx10"], 5895 "map": {"at": 166924, "to": "mm"}, 5896 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", 5897 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 5898 }, 5899 { 5900 "chips": ["gfx10"], 5901 "map": {"at": 166928, "to": "mm"}, 5902 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", 5903 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 5904 }, 5905 { 5906 "chips": ["gfx10"], 5907 "map": {"at": 166932, "to": "mm"}, 5908 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", 5909 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 5910 }, 5911 { 5912 "chips": ["gfx10"], 5913 "map": {"at": 166936, "to": "mm"}, 5914 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", 5915 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 5916 }, 5917 { 5918 "chips": ["gfx10"], 5919 "map": {"at": 166940, "to": "mm"}, 5920 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", 5921 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 5922 }, 5923 { 5924 "chips": ["gfx10"], 5925 "map": {"at": 166944, "to": "mm"}, 5926 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", 5927 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 5928 }, 5929 { 5930 "chips": ["gfx10"], 5931 "map": {"at": 166948, "to": "mm"}, 5932 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", 5933 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 5934 }, 5935 { 5936 "chips": ["gfx10"], 5937 "map": {"at": 166952, "to": "mm"}, 5938 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", 5939 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 5940 }, 5941 { 5942 "chips": ["gfx10"], 5943 "map": {"at": 166956, "to": "mm"}, 5944 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", 5945 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 5946 }, 5947 { 5948 "chips": ["gfx10"], 5949 "map": {"at": 166960, "to": "mm"}, 5950 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", 5951 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 5952 }, 5953 { 5954 "chips": ["gfx10"], 5955 "map": {"at": 166964, "to": "mm"}, 5956 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", 5957 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 5958 }, 5959 { 5960 "chips": ["gfx10"], 5961 "map": {"at": 166968, "to": "mm"}, 5962 "name": "PA_SC_AA_MASK_X0Y0_X1Y0", 5963 "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0" 5964 }, 5965 { 5966 "chips": ["gfx10"], 5967 "map": {"at": 166972, "to": "mm"}, 5968 "name": "PA_SC_AA_MASK_X0Y1_X1Y1", 5969 "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1" 5970 }, 5971 { 5972 "chips": ["gfx10"], 5973 "map": {"at": 166976, "to": "mm"}, 5974 "name": "PA_SC_SHADER_CONTROL", 5975 "type_ref": "PA_SC_SHADER_CONTROL" 5976 }, 5977 { 5978 "chips": ["gfx10"], 5979 "map": {"at": 166980, "to": "mm"}, 5980 "name": "PA_SC_BINNER_CNTL_0", 5981 "type_ref": "PA_SC_BINNER_CNTL_0" 5982 }, 5983 { 5984 "chips": ["gfx10"], 5985 "map": {"at": 166984, "to": "mm"}, 5986 "name": "PA_SC_BINNER_CNTL_1", 5987 "type_ref": "PA_SC_BINNER_CNTL_1" 5988 }, 5989 { 5990 "chips": ["gfx10"], 5991 "map": {"at": 166988, "to": "mm"}, 5992 "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL", 5993 "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL" 5994 }, 5995 { 5996 "chips": ["gfx10"], 5997 "map": {"at": 166992, "to": "mm"}, 5998 "name": "PA_SC_NGG_MODE_CNTL", 5999 "type_ref": "PA_SC_NGG_MODE_CNTL" 6000 }, 6001 { 6002 "chips": ["gfx10"], 6003 "map": {"at": 167000, "to": "mm"}, 6004 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL", 6005 "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL" 6006 }, 6007 { 6008 "chips": ["gfx10"], 6009 "map": {"at": 167004, "to": "mm"}, 6010 "name": "VGT_OUT_DEALLOC_CNTL", 6011 "type_ref": "VGT_OUT_DEALLOC_CNTL" 6012 }, 6013 { 6014 "chips": ["gfx10"], 6015 "map": {"at": 167008, "to": "mm"}, 6016 "name": "CB_COLOR0_BASE" 6017 }, 6018 { 6019 "chips": ["gfx10"], 6020 "map": {"at": 167012, "to": "mm"}, 6021 "name": "CB_COLOR0_PITCH", 6022 "type_ref": "CB_COLOR0_PITCH" 6023 }, 6024 { 6025 "chips": ["gfx10"], 6026 "map": {"at": 167016, "to": "mm"}, 6027 "name": "CB_COLOR0_SLICE", 6028 "type_ref": "CB_COLOR0_SLICE" 6029 }, 6030 { 6031 "chips": ["gfx10"], 6032 "map": {"at": 167020, "to": "mm"}, 6033 "name": "CB_COLOR0_VIEW", 6034 "type_ref": "CB_COLOR0_VIEW" 6035 }, 6036 { 6037 "chips": ["gfx10"], 6038 "map": {"at": 167024, "to": "mm"}, 6039 "name": "CB_COLOR0_INFO", 6040 "type_ref": "CB_COLOR0_INFO" 6041 }, 6042 { 6043 "chips": ["gfx10"], 6044 "map": {"at": 167028, "to": "mm"}, 6045 "name": "CB_COLOR0_ATTRIB", 6046 "type_ref": "CB_COLOR0_ATTRIB" 6047 }, 6048 { 6049 "chips": ["gfx10"], 6050 "map": {"at": 167032, "to": "mm"}, 6051 "name": "CB_COLOR0_DCC_CONTROL", 6052 "type_ref": "CB_COLOR0_DCC_CONTROL" 6053 }, 6054 { 6055 "chips": ["gfx10"], 6056 "map": {"at": 167036, "to": "mm"}, 6057 "name": "CB_COLOR0_CMASK" 6058 }, 6059 { 6060 "chips": ["gfx10"], 6061 "map": {"at": 167040, "to": "mm"}, 6062 "name": "CB_COLOR0_CMASK_SLICE", 6063 "type_ref": "CB_COLOR0_CMASK_SLICE" 6064 }, 6065 { 6066 "chips": ["gfx10"], 6067 "map": {"at": 167044, "to": "mm"}, 6068 "name": "CB_COLOR0_FMASK" 6069 }, 6070 { 6071 "chips": ["gfx10"], 6072 "map": {"at": 167048, "to": "mm"}, 6073 "name": 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"chips": ["gfx10"], 7123 "map": {"at": 196760, "to": "mm"}, 7124 "name": "CP_VGT_DSINVOC_COUNT_LO" 7125 }, 7126 { 7127 "chips": ["gfx10"], 7128 "map": {"at": 196764, "to": "mm"}, 7129 "name": "CP_VGT_DSINVOC_COUNT_HI" 7130 }, 7131 { 7132 "chips": ["gfx10"], 7133 "map": {"at": 196768, "to": "mm"}, 7134 "name": "CP_PA_CINVOC_COUNT_LO" 7135 }, 7136 { 7137 "chips": ["gfx10"], 7138 "map": {"at": 196772, "to": "mm"}, 7139 "name": "CP_PA_CINVOC_COUNT_HI" 7140 }, 7141 { 7142 "chips": ["gfx10"], 7143 "map": {"at": 196776, "to": "mm"}, 7144 "name": "CP_PA_CPRIM_COUNT_LO" 7145 }, 7146 { 7147 "chips": ["gfx10"], 7148 "map": {"at": 196780, "to": "mm"}, 7149 "name": "CP_PA_CPRIM_COUNT_HI" 7150 }, 7151 { 7152 "chips": ["gfx10"], 7153 "map": {"at": 196784, "to": "mm"}, 7154 "name": "CP_SC_PSINVOC_COUNT0_LO" 7155 }, 7156 { 7157 "chips": ["gfx10"], 7158 "map": {"at": 196788, "to": "mm"}, 7159 "name": "CP_SC_PSINVOC_COUNT0_HI" 7160 }, 7161 { 7162 "chips": ["gfx10"], 7163 "map": {"at": 196792, "to": "mm"}, 7164 "name": "CP_SC_PSINVOC_COUNT1_LO" 7165 }, 7166 { 7167 "chips": ["gfx10"], 7168 "map": {"at": 196796, "to": "mm"}, 7169 "name": "CP_SC_PSINVOC_COUNT1_HI" 7170 }, 7171 { 7172 "chips": ["gfx10"], 7173 "map": {"at": 196800, "to": "mm"}, 7174 "name": "CP_VGT_CSINVOC_COUNT_LO" 7175 }, 7176 { 7177 "chips": ["gfx10"], 7178 "map": {"at": 196804, "to": "mm"}, 7179 "name": "CP_VGT_CSINVOC_COUNT_HI" 7180 }, 7181 { 7182 "chips": ["gfx10"], 7183 "map": {"at": 196808, "to": "mm"}, 7184 "name": "CP_EOP_DONE_DOORBELL", 7185 "type_ref": "CP_EOP_DONE_DOORBELL" 7186 }, 7187 { 7188 "chips": ["gfx10"], 7189 "map": {"at": 196812, "to": "mm"}, 7190 "name": "CP_STREAM_OUT_DOORBELL", 7191 "type_ref": "CP_EOP_DONE_DOORBELL" 7192 }, 7193 { 7194 "chips": ["gfx10"], 7195 "map": {"at": 196816, "to": "mm"}, 7196 "name": "CP_SEM_DOORBELL", 7197 "type_ref": "CP_EOP_DONE_DOORBELL" 7198 }, 7199 { 7200 "chips": ["gfx10"], 7201 "map": {"at": 196852, "to": "mm"}, 7202 "name": "CP_PIPE_STATS_CONTROL", 7203 "type_ref": "CP_PIPE_STATS_CONTROL" 7204 }, 7205 { 7206 "chips": ["gfx10"], 7207 "map": {"at": 196856, "to": "mm"}, 7208 "name": "CP_STREAM_OUT_CONTROL", 7209 "type_ref": "CP_PIPE_STATS_CONTROL" 7210 }, 7211 { 7212 "chips": ["gfx10"], 7213 "map": {"at": 196860, "to": "mm"}, 7214 "name": "CP_STRMOUT_CNTL", 7215 "type_ref": "CP_STRMOUT_CNTL" 7216 }, 7217 { 7218 "chips": ["gfx10"], 7219 "map": {"at": 196864, "to": "mm"}, 7220 "name": "SCRATCH_REG0" 7221 }, 7222 { 7223 "chips": ["gfx10"], 7224 "map": {"at": 196868, "to": "mm"}, 7225 "name": "SCRATCH_REG1" 7226 }, 7227 { 7228 "chips": ["gfx10"], 7229 "map": {"at": 196872, "to": "mm"}, 7230 "name": "SCRATCH_REG2" 7231 }, 7232 { 7233 "chips": ["gfx10"], 7234 "map": {"at": 196876, "to": "mm"}, 7235 "name": "SCRATCH_REG3" 7236 }, 7237 { 7238 "chips": ["gfx10"], 7239 "map": {"at": 196880, "to": "mm"}, 7240 "name": "SCRATCH_REG4" 7241 }, 7242 { 7243 "chips": ["gfx10"], 7244 "map": {"at": 196884, "to": "mm"}, 7245 "name": "SCRATCH_REG5" 7246 }, 7247 { 7248 "chips": ["gfx10"], 7249 "map": {"at": 196888, "to": "mm"}, 7250 "name": "SCRATCH_REG6" 7251 }, 7252 { 7253 "chips": ["gfx10"], 7254 "map": {"at": 196892, "to": "mm"}, 7255 "name": "SCRATCH_REG7" 7256 }, 7257 { 7258 "chips": ["gfx10"], 7259 "map": {"at": 196896, "to": "mm"}, 7260 "name": "CP_PIPE_STATS_DOORBELL", 7261 "type_ref": "CP_EOP_DONE_DOORBELL" 7262 }, 7263 { 7264 "chips": ["gfx10"], 7265 "map": {"at": 196908, "to": "mm"}, 7266 "name": "CP_APPEND_DDID_CNT", 7267 "type_ref": "COMPUTE_PGM_HI" 7268 }, 7269 { 7270 "chips": ["gfx10"], 7271 "map": {"at": 196912, "to": "mm"}, 7272 "name": "CP_APPEND_DATA_HI" 7273 }, 7274 { 7275 "chips": ["gfx10"], 7276 "map": {"at": 196916, "to": "mm"}, 7277 "name": "CP_APPEND_LAST_CS_FENCE_HI" 7278 }, 7279 { 7280 "chips": ["gfx10"], 7281 "map": {"at": 196920, "to": "mm"}, 7282 "name": "CP_APPEND_LAST_PS_FENCE_HI" 7283 }, 7284 { 7285 "chips": ["gfx10"], 7286 "map": {"at": 196928, "to": "mm"}, 7287 "name": "SCRATCH_UMSK", 7288 "type_ref": "SCRATCH_UMSK" 7289 }, 7290 { 7291 "chips": ["gfx10"], 7292 "map": {"at": 196932, "to": "mm"}, 7293 "name": "SCRATCH_ADDR" 7294 }, 7295 { 7296 "chips": ["gfx10"], 7297 "map": {"at": 196936, "to": "mm"}, 7298 "name": "CP_PFP_ATOMIC_PREOP_LO" 7299 }, 7300 { 7301 "chips": ["gfx10"], 7302 "map": {"at": 196940, "to": "mm"}, 7303 "name": "CP_PFP_ATOMIC_PREOP_HI" 7304 }, 7305 { 7306 "chips": ["gfx10"], 7307 "map": {"at": 196944, "to": "mm"}, 7308 "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO" 7309 }, 7310 { 7311 "chips": ["gfx10"], 7312 "map": {"at": 196948, "to": "mm"}, 7313 "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI" 7314 }, 7315 { 7316 "chips": ["gfx10"], 7317 "map": {"at": 196952, "to": "mm"}, 7318 "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO" 7319 }, 7320 { 7321 "chips": ["gfx10"], 7322 "map": {"at": 196956, "to": "mm"}, 7323 "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI" 7324 }, 7325 { 7326 "chips": ["gfx10"], 7327 "map": {"at": 196960, "to": "mm"}, 7328 "name": "CP_APPEND_ADDR_LO", 7329 "type_ref": "CP_APPEND_ADDR_LO" 7330 }, 7331 { 7332 "chips": ["gfx10"], 7333 "map": {"at": 196964, "to": "mm"}, 7334 "name": "CP_APPEND_ADDR_HI", 7335 "type_ref": "CP_APPEND_ADDR_HI" 7336 }, 7337 { 7338 "chips": ["gfx10"], 7339 "map": {"at": 196968, "to": "mm"}, 7340 "name": "CP_APPEND_DATA" 7341 }, 7342 { 7343 "chips": ["gfx10"], 7344 "map": {"at": 196972, "to": "mm"}, 7345 "name": "CP_APPEND_LAST_CS_FENCE" 7346 }, 7347 { 7348 "chips": ["gfx10"], 7349 "map": {"at": 196976, "to": "mm"}, 7350 "name": "CP_APPEND_LAST_PS_FENCE" 7351 }, 7352 { 7353 "chips": ["gfx10"], 7354 "map": {"at": 196980, "to": "mm"}, 7355 "name": "CP_ATOMIC_PREOP_LO" 7356 }, 7357 { 7358 "chips": ["gfx10"], 7359 "map": {"at": 196984, "to": "mm"}, 7360 "name": "CP_ATOMIC_PREOP_HI" 7361 }, 7362 { 7363 "chips": ["gfx10"], 7364 "map": {"at": 196988, "to": "mm"}, 7365 "name": "CP_GDS_ATOMIC0_PREOP_LO" 7366 }, 7367 { 7368 "chips": ["gfx10"], 7369 "map": {"at": 196992, "to": "mm"}, 7370 "name": "CP_GDS_ATOMIC0_PREOP_HI" 7371 }, 7372 { 7373 "chips": ["gfx10"], 7374 "map": {"at": 196996, "to": "mm"}, 7375 "name": "CP_GDS_ATOMIC1_PREOP_LO" 7376 }, 7377 { 7378 "chips": ["gfx10"], 7379 "map": {"at": 197000, "to": "mm"}, 7380 "name": "CP_GDS_ATOMIC1_PREOP_HI" 7381 }, 7382 { 7383 "chips": ["gfx10"], 7384 "map": {"at": 197028, "to": "mm"}, 7385 "name": "CP_ME_MC_WADDR_LO", 7386 "type_ref": "CP_ME_MC_WADDR_LO" 7387 }, 7388 { 7389 "chips": ["gfx10"], 7390 "map": {"at": 197032, "to": "mm"}, 7391 "name": "CP_ME_MC_WADDR_HI", 7392 "type_ref": "CP_ME_MC_WADDR_HI" 7393 }, 7394 { 7395 "chips": ["gfx10"], 7396 "map": {"at": 197036, "to": "mm"}, 7397 "name": "CP_ME_MC_WDATA_LO" 7398 }, 7399 { 7400 "chips": ["gfx10"], 7401 "map": {"at": 197040, "to": "mm"}, 7402 "name": "CP_ME_MC_WDATA_HI" 7403 }, 7404 { 7405 "chips": ["gfx10"], 7406 "map": {"at": 197044, "to": "mm"}, 7407 "name": "CP_ME_MC_RADDR_LO", 7408 "type_ref": "CP_ME_MC_RADDR_LO" 7409 }, 7410 { 7411 "chips": ["gfx10"], 7412 "map": {"at": 197048, "to": "mm"}, 7413 "name": "CP_ME_MC_RADDR_HI", 7414 "type_ref": "CP_ME_MC_RADDR_HI" 7415 }, 7416 { 7417 "chips": ["gfx10"], 7418 "map": {"at": 197052, "to": "mm"}, 7419 "name": "CP_SEM_WAIT_TIMER" 7420 }, 7421 { 7422 "chips": ["gfx10"], 7423 "map": {"at": 197056, "to": "mm"}, 7424 "name": "CP_SIG_SEM_ADDR_LO", 7425 "type_ref": "CP_SIG_SEM_ADDR_LO" 7426 }, 7427 { 7428 "chips": ["gfx10"], 7429 "map": {"at": 197060, "to": "mm"}, 7430 "name": "CP_SIG_SEM_ADDR_HI", 7431 "type_ref": "CP_SIG_SEM_ADDR_HI" 7432 }, 7433 { 7434 "chips": ["gfx10"], 7435 "map": {"at": 197072, "to": "mm"}, 7436 "name": "CP_WAIT_REG_MEM_TIMEOUT" 7437 }, 7438 { 7439 "chips": ["gfx10"], 7440 "map": {"at": 197076, "to": "mm"}, 7441 "name": "CP_WAIT_SEM_ADDR_LO", 7442 "type_ref": "CP_SIG_SEM_ADDR_LO" 7443 }, 7444 { 7445 "chips": ["gfx10"], 7446 "map": {"at": 197080, "to": "mm"}, 7447 "name": "CP_WAIT_SEM_ADDR_HI", 7448 "type_ref": "CP_SIG_SEM_ADDR_HI" 7449 }, 7450 { 7451 "chips": ["gfx10"], 7452 "map": {"at": 197084, "to": "mm"}, 7453 "name": "CP_DMA_PFP_CONTROL", 7454 "type_ref": "CP_DMA_PFP_CONTROL" 7455 }, 7456 { 7457 "chips": ["gfx10"], 7458 "map": {"at": 197088, "to": "mm"}, 7459 "name": "CP_DMA_ME_CONTROL", 7460 "type_ref": "CP_DMA_PFP_CONTROL" 7461 }, 7462 { 7463 "chips": ["gfx10"], 7464 "map": {"at": 197092, "to": "mm"}, 7465 "name": "CP_COHER_BASE_HI", 7466 "type_ref": "CP_COHER_BASE_HI" 7467 }, 7468 { 7469 "chips": ["gfx10"], 7470 "map": {"at": 197100, "to": "mm"}, 7471 "name": "CP_COHER_START_DELAY", 7472 "type_ref": "CP_COHER_START_DELAY" 7473 }, 7474 { 7475 "chips": ["gfx10"], 7476 "map": {"at": 197104, "to": "mm"}, 7477 "name": "CP_COHER_CNTL", 7478 "type_ref": "CP_COHER_CNTL" 7479 }, 7480 { 7481 "chips": ["gfx10"], 7482 "map": {"at": 197108, "to": "mm"}, 7483 "name": "CP_COHER_SIZE" 7484 }, 7485 { 7486 "chips": ["gfx10"], 7487 "map": {"at": 197112, "to": "mm"}, 7488 "name": "CP_COHER_BASE" 7489 }, 7490 { 7491 "chips": ["gfx10"], 7492 "map": {"at": 197116, "to": "mm"}, 7493 "name": "CP_COHER_STATUS", 7494 "type_ref": "CP_COHER_STATUS" 7495 }, 7496 { 7497 "chips": ["gfx10"], 7498 "map": {"at": 197120, "to": "mm"}, 7499 "name": "CP_DMA_ME_SRC_ADDR" 7500 }, 7501 { 7502 "chips": ["gfx10"], 7503 "map": {"at": 197124, "to": "mm"}, 7504 "name": "CP_DMA_ME_SRC_ADDR_HI", 7505 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 7506 }, 7507 { 7508 "chips": ["gfx10"], 7509 "map": {"at": 197128, "to": "mm"}, 7510 "name": "CP_DMA_ME_DST_ADDR" 7511 }, 7512 { 7513 "chips": ["gfx10"], 7514 "map": {"at": 197132, "to": "mm"}, 7515 "name": "CP_DMA_ME_DST_ADDR_HI", 7516 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 7517 }, 7518 { 7519 "chips": ["gfx10"], 7520 "map": {"at": 197136, "to": "mm"}, 7521 "name": "CP_DMA_ME_COMMAND", 7522 "type_ref": "CP_DMA_ME_COMMAND" 7523 }, 7524 { 7525 "chips": ["gfx10"], 7526 "map": {"at": 197140, "to": "mm"}, 7527 "name": "CP_DMA_PFP_SRC_ADDR" 7528 }, 7529 { 7530 "chips": ["gfx10"], 7531 "map": {"at": 197144, "to": "mm"}, 7532 "name": "CP_DMA_PFP_SRC_ADDR_HI", 7533 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 7534 }, 7535 { 7536 "chips": ["gfx10"], 7537 "map": {"at": 197148, "to": "mm"}, 7538 "name": "CP_DMA_PFP_DST_ADDR" 7539 }, 7540 { 7541 "chips": ["gfx10"], 7542 "map": {"at": 197152, "to": "mm"}, 7543 "name": "CP_DMA_PFP_DST_ADDR_HI", 7544 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 7545 }, 7546 { 7547 "chips": ["gfx10"], 7548 "map": {"at": 197156, "to": "mm"}, 7549 "name": "CP_DMA_PFP_COMMAND", 7550 "type_ref": "CP_DMA_ME_COMMAND" 7551 }, 7552 { 7553 "chips": ["gfx10"], 7554 "map": {"at": 197160, "to": "mm"}, 7555 "name": "CP_DMA_CNTL", 7556 "type_ref": "CP_DMA_CNTL" 7557 }, 7558 { 7559 "chips": ["gfx10"], 7560 "map": {"at": 197164, "to": "mm"}, 7561 "name": "CP_DMA_READ_TAGS", 7562 "type_ref": "CP_DMA_READ_TAGS" 7563 }, 7564 { 7565 "chips": ["gfx10"], 7566 "map": {"at": 197168, "to": "mm"}, 7567 "name": "CP_COHER_SIZE_HI", 7568 "type_ref": "CP_COHER_SIZE_HI" 7569 }, 7570 { 7571 "chips": ["gfx10"], 7572 "map": {"at": 197172, "to": "mm"}, 7573 "name": "CP_PFP_IB_CONTROL", 7574 "type_ref": "CP_PFP_IB_CONTROL" 7575 }, 7576 { 7577 "chips": ["gfx10"], 7578 "map": {"at": 197176, "to": "mm"}, 7579 "name": "CP_PFP_LOAD_CONTROL", 7580 "type_ref": "CP_PFP_LOAD_CONTROL" 7581 }, 7582 { 7583 "chips": ["gfx10"], 7584 "map": {"at": 197180, "to": "mm"}, 7585 "name": "CP_SCRATCH_INDEX", 7586 "type_ref": "CP_SCRATCH_INDEX" 7587 }, 7588 { 7589 "chips": ["gfx10"], 7590 "map": {"at": 197184, "to": "mm"}, 7591 "name": "CP_SCRATCH_DATA" 7592 }, 7593 { 7594 "chips": ["gfx10"], 7595 "map": {"at": 197188, "to": "mm"}, 7596 "name": "CP_RB_OFFSET", 7597 "type_ref": "CP_RB_OFFSET" 7598 }, 7599 { 7600 "chips": ["gfx10"], 7601 "map": {"at": 197192, "to": "mm"}, 7602 "name": "CP_IB1_OFFSET", 7603 "type_ref": "CP_IB1_OFFSET" 7604 }, 7605 { 7606 "chips": ["gfx10"], 7607 "map": {"at": 197196, "to": "mm"}, 7608 "name": "CP_IB2_OFFSET", 7609 "type_ref": "CP_IB2_OFFSET" 7610 }, 7611 { 7612 "chips": ["gfx10"], 7613 "map": {"at": 197200, "to": "mm"}, 7614 "name": "CP_IB1_PREAMBLE_BEGIN", 7615 "type_ref": "CP_IB1_PREAMBLE_BEGIN" 7616 }, 7617 { 7618 "chips": ["gfx10"], 7619 "map": {"at": 197204, "to": "mm"}, 7620 "name": "CP_IB1_PREAMBLE_END", 7621 "type_ref": "CP_IB1_PREAMBLE_END" 7622 }, 7623 { 7624 "chips": ["gfx10"], 7625 "map": {"at": 197208, "to": "mm"}, 7626 "name": "CP_IB2_PREAMBLE_BEGIN", 7627 "type_ref": "CP_IB2_PREAMBLE_BEGIN" 7628 }, 7629 { 7630 "chips": ["gfx10"], 7631 "map": {"at": 197212, "to": "mm"}, 7632 "name": "CP_IB2_PREAMBLE_END", 7633 "type_ref": "CP_IB2_PREAMBLE_END" 7634 }, 7635 { 7636 "chips": ["gfx10"], 7637 "map": {"at": 197216, "to": "mm"}, 7638 "name": "CP_CE_IB1_OFFSET", 7639 "type_ref": "CP_IB1_OFFSET" 7640 }, 7641 { 7642 "chips": ["gfx10"], 7643 "map": {"at": 197220, "to": "mm"}, 7644 "name": "CP_CE_IB2_OFFSET", 7645 "type_ref": "CP_IB2_OFFSET" 7646 }, 7647 { 7648 "chips": ["gfx10"], 7649 "map": {"at": 197224, "to": "mm"}, 7650 "name": "CP_CE_COUNTER" 7651 }, 7652 { 7653 "chips": ["gfx10"], 7654 "map": {"at": 197232, "to": "mm"}, 7655 "name": "CP_DMA_ME_CMD_ADDR_LO", 7656 "type_ref": "CP_DMA_ME_CMD_ADDR_LO" 7657 }, 7658 { 7659 "chips": ["gfx10"], 7660 "map": {"at": 197236, "to": "mm"}, 7661 "name": "CP_DMA_ME_CMD_ADDR_HI", 7662 "type_ref": "CP_DMA_ME_CMD_ADDR_HI" 7663 }, 7664 { 7665 "chips": ["gfx10"], 7666 "map": {"at": 197240, "to": "mm"}, 7667 "name": "CP_DMA_PFP_CMD_ADDR_LO", 7668 "type_ref": "CP_DMA_ME_CMD_ADDR_LO" 7669 }, 7670 { 7671 "chips": ["gfx10"], 7672 "map": {"at": 197244, "to": "mm"}, 7673 "name": "CP_DMA_PFP_CMD_ADDR_HI", 7674 "type_ref": "CP_DMA_ME_CMD_ADDR_HI" 7675 }, 7676 { 7677 "chips": ["gfx10"], 7678 "map": {"at": 197248, "to": "mm"}, 7679 "name": "CP_APPEND_CMD_ADDR_LO", 7680 "type_ref": "CP_DMA_ME_CMD_ADDR_LO" 7681 }, 7682 { 7683 "chips": ["gfx10"], 7684 "map": {"at": 197252, "to": "mm"}, 7685 "name": "CP_APPEND_CMD_ADDR_HI", 7686 "type_ref": "CP_DMA_ME_CMD_ADDR_HI" 7687 }, 7688 { 7689 "chips": ["gfx10"], 7690 "map": {"at": 197364, "to": "mm"}, 7691 "name": "CP_CE_INIT_CMD_BUFSZ", 7692 "type_ref": "CP_CE_INIT_CMD_BUFSZ" 7693 }, 7694 { 7695 "chips": ["gfx10"], 7696 "map": {"at": 197368, "to": "mm"}, 7697 "name": "CP_CE_IB1_CMD_BUFSZ", 7698 "type_ref": "CP_CE_IB1_CMD_BUFSZ" 7699 }, 7700 { 7701 "chips": ["gfx10"], 7702 "map": {"at": 197372, "to": "mm"}, 7703 "name": "CP_CE_IB2_CMD_BUFSZ", 7704 "type_ref": "CP_CE_IB2_CMD_BUFSZ" 7705 }, 7706 { 7707 "chips": ["gfx10"], 7708 "map": {"at": 197376, "to": "mm"}, 7709 "name": "CP_IB1_CMD_BUFSZ", 7710 "type_ref": "CP_CE_IB1_CMD_BUFSZ" 7711 }, 7712 { 7713 "chips": ["gfx10"], 7714 "map": {"at": 197380, "to": "mm"}, 7715 "name": "CP_IB2_CMD_BUFSZ", 7716 "type_ref": "CP_CE_IB2_CMD_BUFSZ" 7717 }, 7718 { 7719 "chips": ["gfx10"], 7720 "map": {"at": 197384, "to": "mm"}, 7721 "name": "CP_ST_CMD_BUFSZ", 7722 "type_ref": "CP_ST_CMD_BUFSZ" 7723 }, 7724 { 7725 "chips": ["gfx10"], 7726 "map": {"at": 197388, "to": "mm"}, 7727 "name": "CP_CE_INIT_BASE_LO", 7728 "type_ref": "CP_CE_INIT_BASE_LO" 7729 }, 7730 { 7731 "chips": ["gfx10"], 7732 "map": {"at": 197392, "to": "mm"}, 7733 "name": "CP_CE_INIT_BASE_HI", 7734 "type_ref": "CP_CE_INIT_BASE_HI" 7735 }, 7736 { 7737 "chips": ["gfx10"], 7738 "map": {"at": 197396, "to": "mm"}, 7739 "name": "CP_CE_INIT_BUFSZ", 7740 "type_ref": "CP_CE_INIT_BUFSZ" 7741 }, 7742 { 7743 "chips": ["gfx10"], 7744 "map": {"at": 197400, "to": "mm"}, 7745 "name": "CP_CE_IB1_BASE_LO", 7746 "type_ref": "CP_CE_IB1_BASE_LO" 7747 }, 7748 { 7749 "chips": ["gfx10"], 7750 "map": {"at": 197404, "to": "mm"}, 7751 "name": "CP_CE_IB1_BASE_HI", 7752 "type_ref": "CP_CE_IB1_BASE_HI" 7753 }, 7754 { 7755 "chips": ["gfx10"], 7756 "map": {"at": 197408, "to": "mm"}, 7757 "name": "CP_CE_IB1_BUFSZ", 7758 "type_ref": "CP_CE_IB1_BUFSZ" 7759 }, 7760 { 7761 "chips": ["gfx10"], 7762 "map": {"at": 197412, "to": "mm"}, 7763 "name": "CP_CE_IB2_BASE_LO", 7764 "type_ref": "CP_CE_IB2_BASE_LO" 7765 }, 7766 { 7767 "chips": ["gfx10"], 7768 "map": {"at": 197416, "to": "mm"}, 7769 "name": "CP_CE_IB2_BASE_HI", 7770 "type_ref": "CP_CE_IB2_BASE_HI" 7771 }, 7772 { 7773 "chips": ["gfx10"], 7774 "map": {"at": 197420, "to": "mm"}, 7775 "name": "CP_CE_IB2_BUFSZ", 7776 "type_ref": "CP_CE_IB2_BUFSZ" 7777 }, 7778 { 7779 "chips": ["gfx10"], 7780 "map": {"at": 197424, "to": "mm"}, 7781 "name": "CP_IB1_BASE_LO", 7782 "type_ref": "CP_CE_IB1_BASE_LO" 7783 }, 7784 { 7785 "chips": ["gfx10"], 7786 "map": {"at": 197428, "to": "mm"}, 7787 "name": "CP_IB1_BASE_HI", 7788 "type_ref": "CP_CE_IB1_BASE_HI" 7789 }, 7790 { 7791 "chips": ["gfx10"], 7792 "map": {"at": 197432, "to": "mm"}, 7793 "name": "CP_IB1_BUFSZ", 7794 "type_ref": "CP_CE_IB1_BUFSZ" 7795 }, 7796 { 7797 "chips": ["gfx10"], 7798 "map": {"at": 197436, "to": "mm"}, 7799 "name": "CP_IB2_BASE_LO", 7800 "type_ref": "CP_CE_IB2_BASE_LO" 7801 }, 7802 { 7803 "chips": ["gfx10"], 7804 "map": {"at": 197440, "to": "mm"}, 7805 "name": "CP_IB2_BASE_HI", 7806 "type_ref": "CP_CE_IB2_BASE_HI" 7807 }, 7808 { 7809 "chips": ["gfx10"], 7810 "map": {"at": 197444, "to": "mm"}, 7811 "name": "CP_IB2_BUFSZ", 7812 "type_ref": "CP_CE_IB2_BUFSZ" 7813 }, 7814 { 7815 "chips": ["gfx10"], 7816 "map": {"at": 197448, "to": "mm"}, 7817 "name": "CP_ST_BASE_LO", 7818 "type_ref": "CP_ST_BASE_LO" 7819 }, 7820 { 7821 "chips": ["gfx10"], 7822 "map": {"at": 197452, "to": "mm"}, 7823 "name": "CP_ST_BASE_HI", 7824 "type_ref": "CP_ST_BASE_HI" 7825 }, 7826 { 7827 "chips": ["gfx10"], 7828 "map": {"at": 197456, "to": "mm"}, 7829 "name": "CP_ST_BUFSZ", 7830 "type_ref": "CP_ST_BUFSZ" 7831 }, 7832 { 7833 "chips": ["gfx10"], 7834 "map": {"at": 197460, "to": "mm"}, 7835 "name": "CP_EOP_DONE_EVENT_CNTL", 7836 "type_ref": "CP_EOP_DONE_EVENT_CNTL" 7837 }, 7838 { 7839 "chips": ["gfx10"], 7840 "map": {"at": 197464, "to": "mm"}, 7841 "name": "CP_EOP_DONE_DATA_CNTL", 7842 "type_ref": "CP_EOP_DONE_DATA_CNTL" 7843 }, 7844 { 7845 "chips": ["gfx10"], 7846 "map": {"at": 197468, "to": "mm"}, 7847 "name": "CP_EOP_DONE_CNTX_ID" 7848 }, 7849 { 7850 "chips": ["gfx10"], 7851 "map": {"at": 197472, "to": "mm"}, 7852 "name": "CP_DB_BASE_LO", 7853 "type_ref": "CP_DB_BASE_LO" 7854 }, 7855 { 7856 "chips": ["gfx10"], 7857 "map": {"at": 197476, "to": "mm"}, 7858 "name": "CP_DB_BASE_HI", 7859 "type_ref": "CP_DB_BASE_HI" 7860 }, 7861 { 7862 "chips": ["gfx10"], 7863 "map": {"at": 197480, "to": "mm"}, 7864 "name": "CP_DB_BUFSZ", 7865 "type_ref": "CP_DB_BUFSZ" 7866 }, 7867 { 7868 "chips": ["gfx10"], 7869 "map": {"at": 197484, "to": "mm"}, 7870 "name": "CP_DB_CMD_BUFSZ", 7871 "type_ref": "CP_DB_CMD_BUFSZ" 7872 }, 7873 { 7874 "chips": ["gfx10"], 7875 "map": {"at": 197488, "to": "mm"}, 7876 "name": "CP_CE_DB_BASE_LO", 7877 "type_ref": "CP_DB_BASE_LO" 7878 }, 7879 { 7880 "chips": ["gfx10"], 7881 "map": {"at": 197492, "to": "mm"}, 7882 "name": "CP_CE_DB_BASE_HI", 7883 "type_ref": "CP_DB_BASE_HI" 7884 }, 7885 { 7886 "chips": ["gfx10"], 7887 "map": {"at": 197496, "to": "mm"}, 7888 "name": "CP_CE_DB_BUFSZ", 7889 "type_ref": "CP_DB_BUFSZ" 7890 }, 7891 { 7892 "chips": ["gfx10"], 7893 "map": {"at": 197500, "to": "mm"}, 7894 "name": "CP_CE_DB_CMD_BUFSZ", 7895 "type_ref": "CP_DB_CMD_BUFSZ" 7896 }, 7897 { 7898 "chips": ["gfx10"], 7899 "map": {"at": 197552, "to": "mm"}, 7900 "name": "CP_PFP_COMPLETION_STATUS", 7901 "type_ref": "CP_PFP_COMPLETION_STATUS" 7902 }, 7903 { 7904 "chips": ["gfx10"], 7905 "map": {"at": 197556, "to": "mm"}, 7906 "name": "CP_CE_COMPLETION_STATUS", 7907 "type_ref": "CP_PFP_COMPLETION_STATUS" 7908 }, 7909 { 7910 "chips": ["gfx10"], 7911 "map": {"at": 197560, "to": "mm"}, 7912 "name": "CP_PRED_NOT_VISIBLE", 7913 "type_ref": "CP_PRED_NOT_VISIBLE" 7914 }, 7915 { 7916 "chips": ["gfx10"], 7917 "map": {"at": 197568, "to": "mm"}, 7918 "name": "CP_PFP_METADATA_BASE_ADDR" 7919 }, 7920 { 7921 "chips": ["gfx10"], 7922 "map": {"at": 197572, "to": "mm"}, 7923 "name": "CP_PFP_METADATA_BASE_ADDR_HI", 7924 "type_ref": "CP_EOP_DONE_ADDR_HI" 7925 }, 7926 { 7927 "chips": ["gfx10"], 7928 "map": {"at": 197576, "to": "mm"}, 7929 "name": "CP_CE_METADATA_BASE_ADDR" 7930 }, 7931 { 7932 "chips": ["gfx10"], 7933 "map": {"at": 197580, "to": "mm"}, 7934 "name": "CP_CE_METADATA_BASE_ADDR_HI", 7935 "type_ref": "CP_EOP_DONE_ADDR_HI" 7936 }, 7937 { 7938 "chips": ["gfx10"], 7939 "map": {"at": 197584, "to": "mm"}, 7940 "name": "CP_DRAW_INDX_INDR_ADDR" 7941 }, 7942 { 7943 "chips": ["gfx10"], 7944 "map": {"at": 197588, "to": "mm"}, 7945 "name": "CP_DRAW_INDX_INDR_ADDR_HI", 7946 "type_ref": "CP_EOP_DONE_ADDR_HI" 7947 }, 7948 { 7949 "chips": ["gfx10"], 7950 "map": {"at": 197592, "to": "mm"}, 7951 "name": "CP_DISPATCH_INDR_ADDR" 7952 }, 7953 { 7954 "chips": ["gfx10"], 7955 "map": {"at": 197596, "to": "mm"}, 7956 "name": "CP_DISPATCH_INDR_ADDR_HI", 7957 "type_ref": "CP_EOP_DONE_ADDR_HI" 7958 }, 7959 { 7960 "chips": ["gfx10"], 7961 "map": {"at": 197600, "to": "mm"}, 7962 "name": "CP_INDEX_BASE_ADDR" 7963 }, 7964 { 7965 "chips": ["gfx10"], 7966 "map": {"at": 197604, "to": "mm"}, 7967 "name": "CP_INDEX_BASE_ADDR_HI", 7968 "type_ref": "CP_EOP_DONE_ADDR_HI" 7969 }, 7970 { 7971 "chips": ["gfx10"], 7972 "map": {"at": 197608, "to": "mm"}, 7973 "name": "CP_INDEX_TYPE", 7974 "type_ref": "CP_INDEX_TYPE" 7975 }, 7976 { 7977 "chips": ["gfx10"], 7978 "map": {"at": 197612, "to": "mm"}, 7979 "name": "CP_GDS_BKUP_ADDR" 7980 }, 7981 { 7982 "chips": ["gfx10"], 7983 "map": {"at": 197616, "to": "mm"}, 7984 "name": "CP_GDS_BKUP_ADDR_HI", 7985 "type_ref": "CP_EOP_DONE_ADDR_HI" 7986 }, 7987 { 7988 "chips": ["gfx10"], 7989 "map": {"at": 197620, "to": "mm"}, 7990 "name": "CP_SAMPLE_STATUS", 7991 "type_ref": "CP_SAMPLE_STATUS" 7992 }, 7993 { 7994 "chips": ["gfx10"], 7995 "map": {"at": 197624, "to": "mm"}, 7996 "name": "CP_ME_COHER_CNTL", 7997 "type_ref": "CP_ME_COHER_CNTL" 7998 }, 7999 { 8000 "chips": ["gfx10"], 8001 "map": {"at": 197628, "to": "mm"}, 8002 "name": "CP_ME_COHER_SIZE" 8003 }, 8004 { 8005 "chips": ["gfx10"], 8006 "map": {"at": 197632, "to": "mm"}, 8007 "name": "CP_ME_COHER_SIZE_HI", 8008 "type_ref": "CP_COHER_SIZE_HI" 8009 }, 8010 { 8011 "chips": ["gfx10"], 8012 "map": {"at": 197636, "to": "mm"}, 8013 "name": "CP_ME_COHER_BASE" 8014 }, 8015 { 8016 "chips": ["gfx10"], 8017 "map": {"at": 197640, "to": "mm"}, 8018 "name": "CP_ME_COHER_BASE_HI", 8019 "type_ref": "CP_COHER_BASE_HI" 8020 }, 8021 { 8022 "chips": ["gfx10"], 8023 "map": {"at": 197644, "to": "mm"}, 8024 "name": "CP_ME_COHER_STATUS", 8025 "type_ref": "CP_ME_COHER_STATUS" 8026 }, 8027 { 8028 "chips": ["gfx10"], 8029 "map": {"at": 197888, "to": "mm"}, 8030 "name": "RLC_GPM_PERF_COUNT_0", 8031 "type_ref": "RLC_GPM_PERF_COUNT_0" 8032 }, 8033 { 8034 "chips": ["gfx10"], 8035 "map": {"at": 197892, "to": "mm"}, 8036 "name": "RLC_GPM_PERF_COUNT_1", 8037 "type_ref": "RLC_GPM_PERF_COUNT_0" 8038 }, 8039 { 8040 "chips": ["gfx10"], 8041 "map": {"at": 198656, "to": "mm"}, 8042 "name": "GRBM_GFX_INDEX", 8043 "type_ref": "GRBM_GFX_INDEX" 8044 }, 8045 { 8046 "chips": ["gfx10"], 8047 "map": {"at": 198912, "to": "mm"}, 8048 "name": "VGT_ESGS_RING_SIZE_UMD" 8049 }, 8050 { 8051 "chips": ["gfx10"], 8052 "map": {"at": 198916, "to": "mm"}, 8053 "name": "VGT_GSVS_RING_SIZE_UMD" 8054 }, 8055 { 8056 "chips": ["gfx10"], 8057 "map": {"at": 198920, "to": "mm"}, 8058 "name": "VGT_PRIMITIVE_TYPE", 8059 "type_ref": "VGT_PRIMITIVE_TYPE" 8060 }, 8061 { 8062 "chips": ["gfx10"], 8063 "map": {"at": 198924, "to": "mm"}, 8064 "name": "VGT_INDEX_TYPE", 8065 "type_ref": "CP_INDEX_TYPE" 8066 }, 8067 { 8068 "chips": ["gfx10"], 8069 "map": {"at": 198928, "to": "mm"}, 8070 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0" 8071 }, 8072 { 8073 "chips": ["gfx10"], 8074 "map": {"at": 198932, "to": "mm"}, 8075 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1" 8076 }, 8077 { 8078 "chips": ["gfx10"], 8079 "map": {"at": 198936, "to": "mm"}, 8080 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2" 8081 }, 8082 { 8083 "chips": ["gfx10"], 8084 "map": {"at": 198940, "to": "mm"}, 8085 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3" 8086 }, 8087 { 8088 "chips": ["gfx10"], 8089 "map": {"at": 198948, "to": "mm"}, 8090 "name": "GE_MIN_VTX_INDX" 8091 }, 8092 { 8093 "chips": ["gfx10"], 8094 "map": {"at": 198952, "to": "mm"}, 8095 "name": "GE_INDX_OFFSET" 8096 }, 8097 { 8098 "chips": ["gfx10"], 8099 "map": {"at": 198956, "to": "mm"}, 8100 "name": "GE_MULTI_PRIM_IB_RESET_EN", 8101 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN" 8102 }, 8103 { 8104 "chips": ["gfx10"], 8105 "map": {"at": 198960, "to": "mm"}, 8106 "name": "VGT_NUM_INDICES" 8107 }, 8108 { 8109 "chips": ["gfx10"], 8110 "map": {"at": 198964, "to": "mm"}, 8111 "name": "VGT_NUM_INSTANCES" 8112 }, 8113 { 8114 "chips": ["gfx10"], 8115 "map": {"at": 198968, "to": "mm"}, 8116 "name": "VGT_TF_RING_SIZE_UMD", 8117 "type_ref": "VGT_TF_RING_SIZE_UMD" 8118 }, 8119 { 8120 "chips": ["gfx10"], 8121 "map": {"at": 198972, "to": "mm"}, 8122 "name": "VGT_HS_OFFCHIP_PARAM_UMD", 8123 "type_ref": "VGT_HS_OFFCHIP_PARAM_UMD" 8124 }, 8125 { 8126 "chips": ["gfx10"], 8127 "map": {"at": 198976, "to": "mm"}, 8128 "name": "VGT_TF_MEMORY_BASE_UMD" 8129 }, 8130 { 8131 "chips": ["gfx10"], 8132 "map": {"at": 198980, "to": "mm"}, 8133 "name": "GE_DMA_FIRST_INDEX" 8134 }, 8135 { 8136 "chips": ["gfx10"], 8137 "map": {"at": 198984, "to": "mm"}, 8138 "name": "WD_POS_BUF_BASE" 8139 }, 8140 { 8141 "chips": ["gfx10"], 8142 "map": {"at": 198988, "to": "mm"}, 8143 "name": "WD_POS_BUF_BASE_HI", 8144 "type_ref": "DB_Z_READ_BASE_HI" 8145 }, 8146 { 8147 "chips": ["gfx10"], 8148 "map": {"at": 198992, "to": "mm"}, 8149 "name": "WD_CNTL_SB_BUF_BASE" 8150 }, 8151 { 8152 "chips": ["gfx10"], 8153 "map": {"at": 198996, "to": "mm"}, 8154 "name": "WD_CNTL_SB_BUF_BASE_HI", 8155 "type_ref": "DB_Z_READ_BASE_HI" 8156 }, 8157 { 8158 "chips": ["gfx10"], 8159 "map": {"at": 199000, "to": "mm"}, 8160 "name": "WD_INDEX_BUF_BASE" 8161 }, 8162 { 8163 "chips": ["gfx10"], 8164 "map": {"at": 199004, "to": "mm"}, 8165 "name": "WD_INDEX_BUF_BASE_HI", 8166 "type_ref": "DB_Z_READ_BASE_HI" 8167 }, 8168 { 8169 "chips": ["gfx10"], 8170 "map": {"at": 199008, "to": "mm"}, 8171 "name": "IA_MULTI_VGT_PARAM_PIPED", 8172 "type_ref": "IA_MULTI_VGT_PARAM_PIPED" 8173 }, 8174 { 8175 "chips": ["gfx10"], 8176 "map": {"at": 199012, "to": "mm"}, 8177 "name": "GE_MAX_VTX_INDX" 8178 }, 8179 { 8180 "chips": ["gfx10"], 8181 "map": {"at": 199016, "to": "mm"}, 8182 "name": "VGT_INSTANCE_BASE_ID" 8183 }, 8184 { 8185 "chips": ["gfx10"], 8186 "map": {"at": 199020, "to": "mm"}, 8187 "name": "GE_CNTL", 8188 "type_ref": "GE_CNTL" 8189 }, 8190 { 8191 "chips": ["gfx10"], 8192 "map": {"at": 199024, "to": "mm"}, 8193 "name": "GE_USER_VGPR1" 8194 }, 8195 { 8196 "chips": ["gfx10"], 8197 "map": {"at": 199028, "to": "mm"}, 8198 "name": "GE_USER_VGPR2" 8199 }, 8200 { 8201 "chips": ["gfx10"], 8202 "map": {"at": 199032, "to": "mm"}, 8203 "name": "GE_USER_VGPR3" 8204 }, 8205 { 8206 "chips": ["gfx10"], 8207 "map": {"at": 199036, "to": "mm"}, 8208 "name": "GE_STEREO_CNTL", 8209 "type_ref": "GE_STEREO_CNTL" 8210 }, 8211 { 8212 "chips": ["gfx10"], 8213 "map": {"at": 199040, "to": "mm"}, 8214 "name": "GE_PC_ALLOC", 8215 "type_ref": "GE_PC_ALLOC" 8216 }, 8217 { 8218 "chips": ["gfx10"], 8219 "map": {"at": 199044, "to": "mm"}, 8220 "name": "VGT_TF_MEMORY_BASE_HI_UMD", 8221 "type_ref": "DB_Z_READ_BASE_HI" 8222 }, 8223 { 8224 "chips": ["gfx10"], 8225 "map": {"at": 199048, "to": "mm"}, 8226 "name": "GE_USER_VGPR_EN", 8227 "type_ref": "GE_USER_VGPR_EN" 8228 }, 8229 { 8230 "chips": ["gfx10"], 8231 "map": {"at": 199168, "to": "mm"}, 8232 "name": "PA_SU_LINE_STIPPLE_VALUE", 8233 "type_ref": "PA_SU_LINE_STIPPLE_VALUE" 8234 }, 8235 { 8236 "chips": ["gfx10"], 8237 "map": {"at": 199172, "to": "mm"}, 8238 "name": "PA_SC_LINE_STIPPLE_STATE", 8239 "type_ref": "PA_SC_LINE_STIPPLE_STATE" 8240 }, 8241 { 8242 "chips": ["gfx10"], 8243 "map": {"at": 199184, "to": "mm"}, 8244 "name": "PA_SC_SCREEN_EXTENT_MIN_0", 8245 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0" 8246 }, 8247 { 8248 "chips": ["gfx10"], 8249 "map": {"at": 199188, "to": "mm"}, 8250 "name": "PA_SC_SCREEN_EXTENT_MAX_0", 8251 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0" 8252 }, 8253 { 8254 "chips": ["gfx10"], 8255 "map": {"at": 199192, "to": "mm"}, 8256 "name": "PA_SC_SCREEN_EXTENT_MIN_1", 8257 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0" 8258 }, 8259 { 8260 "chips": ["gfx10"], 8261 "map": {"at": 199212, "to": "mm"}, 8262 "name": "PA_SC_SCREEN_EXTENT_MAX_1", 8263 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0" 8264 }, 8265 { 8266 "chips": ["gfx10"], 8267 "map": {"at": 199296, "to": "mm"}, 8268 "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN", 8269 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN" 8270 }, 8271 { 8272 "chips": ["gfx10"], 8273 "map": {"at": 199300, "to": "mm"}, 8274 "name": "PA_SC_P3D_TRAP_SCREEN_H", 8275 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H" 8276 }, 8277 { 8278 "chips": ["gfx10"], 8279 "map": {"at": 199304, "to": "mm"}, 8280 "name": "PA_SC_P3D_TRAP_SCREEN_V", 8281 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V" 8282 }, 8283 { 8284 "chips": ["gfx10"], 8285 "map": {"at": 199308, "to": "mm"}, 8286 "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE", 8287 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 8288 }, 8289 { 8290 "chips": ["gfx10"], 8291 "map": {"at": 199312, "to": "mm"}, 8292 "name": "PA_SC_P3D_TRAP_SCREEN_COUNT", 8293 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 8294 }, 8295 { 8296 "chips": ["gfx10"], 8297 "map": {"at": 199328, "to": "mm"}, 8298 "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN", 8299 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN" 8300 }, 8301 { 8302 "chips": ["gfx10"], 8303 "map": {"at": 199332, "to": "mm"}, 8304 "name": "PA_SC_HP3D_TRAP_SCREEN_H", 8305 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H" 8306 }, 8307 { 8308 "chips": ["gfx10"], 8309 "map": {"at": 199336, "to": "mm"}, 8310 "name": "PA_SC_HP3D_TRAP_SCREEN_V", 8311 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V" 8312 }, 8313 { 8314 "chips": ["gfx10"], 8315 "map": {"at": 199340, "to": "mm"}, 8316 "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE", 8317 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 8318 }, 8319 { 8320 "chips": ["gfx10"], 8321 "map": {"at": 199344, "to": "mm"}, 8322 "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT", 8323 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 8324 }, 8325 { 8326 "chips": ["gfx10"], 8327 "map": {"at": 199360, "to": "mm"}, 8328 "name": "PA_SC_TRAP_SCREEN_HV_EN", 8329 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN" 8330 }, 8331 { 8332 "chips": ["gfx10"], 8333 "map": {"at": 199364, "to": "mm"}, 8334 "name": "PA_SC_TRAP_SCREEN_H", 8335 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H" 8336 }, 8337 { 8338 "chips": ["gfx10"], 8339 "map": {"at": 199368, "to": "mm"}, 8340 "name": "PA_SC_TRAP_SCREEN_V", 8341 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V" 8342 }, 8343 { 8344 "chips": ["gfx10"], 8345 "map": {"at": 199372, "to": "mm"}, 8346 "name": "PA_SC_TRAP_SCREEN_OCCURRENCE", 8347 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 8348 }, 8349 { 8350 "chips": ["gfx10"], 8351 "map": {"at": 199376, "to": "mm"}, 8352 "name": "PA_SC_TRAP_SCREEN_COUNT", 8353 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 8354 }, 8355 { 8356 "chips": ["gfx10"], 8357 "map": {"at": 199936, "to": "mm"}, 8358 "name": "SQ_THREAD_TRACE_USERDATA_0" 8359 }, 8360 { 8361 "chips": ["gfx10"], 8362 "map": {"at": 199940, "to": "mm"}, 8363 "name": "SQ_THREAD_TRACE_USERDATA_1" 8364 }, 8365 { 8366 "chips": ["gfx10"], 8367 "map": {"at": 199944, "to": "mm"}, 8368 "name": "SQ_THREAD_TRACE_USERDATA_2" 8369 }, 8370 { 8371 "chips": ["gfx10"], 8372 "map": {"at": 199948, "to": "mm"}, 8373 "name": "SQ_THREAD_TRACE_USERDATA_3" 8374 }, 8375 { 8376 "chips": ["gfx10"], 8377 "map": {"at": 199952, "to": "mm"}, 8378 "name": "SQ_THREAD_TRACE_USERDATA_4" 8379 }, 8380 { 8381 "chips": ["gfx10"], 8382 "map": {"at": 199956, "to": "mm"}, 8383 "name": "SQ_THREAD_TRACE_USERDATA_5" 8384 }, 8385 { 8386 "chips": ["gfx10"], 8387 "map": {"at": 199960, "to": "mm"}, 8388 "name": "SQ_THREAD_TRACE_USERDATA_6" 8389 }, 8390 { 8391 "chips": ["gfx10"], 8392 "map": {"at": 199964, "to": "mm"}, 8393 "name": "SQ_THREAD_TRACE_USERDATA_7" 8394 }, 8395 { 8396 "chips": ["gfx10"], 8397 "map": {"at": 199968, "to": "mm"}, 8398 "name": "SQC_CACHES", 8399 "type_ref": "SQC_CACHES" 8400 }, 8401 { 8402 "chips": ["gfx10"], 8403 "map": {"at": 199972, "to": "mm"}, 8404 "name": "SQC_WRITEBACK", 8405 "type_ref": "SQC_WRITEBACK" 8406 }, 8407 { 8408 "chips": ["gfx10"], 8409 "map": {"at": 200192, "to": "mm"}, 8410 "name": "TA_CS_BC_BASE_ADDR" 8411 }, 8412 { 8413 "chips": ["gfx10"], 8414 "map": {"at": 200196, "to": "mm"}, 8415 "name": "TA_CS_BC_BASE_ADDR_HI", 8416 "type_ref": "TA_BC_BASE_ADDR_HI" 8417 }, 8418 { 8419 "chips": ["gfx10"], 8420 "map": {"at": 200448, "to": "mm"}, 8421 "name": "DB_OCCLUSION_COUNT0_LOW" 8422 }, 8423 { 8424 "chips": ["gfx10"], 8425 "map": {"at": 200452, "to": "mm"}, 8426 "name": "DB_OCCLUSION_COUNT0_HI", 8427 "type_ref": "DB_OCCLUSION_COUNT0_HI" 8428 }, 8429 { 8430 "chips": ["gfx10"], 8431 "map": {"at": 200456, "to": "mm"}, 8432 "name": "DB_OCCLUSION_COUNT1_LOW" 8433 }, 8434 { 8435 "chips": ["gfx10"], 8436 "map": {"at": 200460, "to": "mm"}, 8437 "name": "DB_OCCLUSION_COUNT1_HI", 8438 "type_ref": "DB_OCCLUSION_COUNT0_HI" 8439 }, 8440 { 8441 "chips": ["gfx10"], 8442 "map": {"at": 200464, "to": "mm"}, 8443 "name": "DB_OCCLUSION_COUNT2_LOW" 8444 }, 8445 { 8446 "chips": ["gfx10"], 8447 "map": {"at": 200468, "to": "mm"}, 8448 "name": "DB_OCCLUSION_COUNT2_HI", 8449 "type_ref": "DB_OCCLUSION_COUNT0_HI" 8450 }, 8451 { 8452 "chips": ["gfx10"], 8453 "map": {"at": 200472, "to": "mm"}, 8454 "name": "DB_OCCLUSION_COUNT3_LOW" 8455 }, 8456 { 8457 "chips": ["gfx10"], 8458 "map": {"at": 200476, "to": "mm"}, 8459 "name": "DB_OCCLUSION_COUNT3_HI", 8460 "type_ref": "DB_OCCLUSION_COUNT0_HI" 8461 }, 8462 { 8463 "chips": ["gfx10"], 8464 "map": {"at": 200696, "to": "mm"}, 8465 "name": "DB_ZPASS_COUNT_LOW" 8466 }, 8467 { 8468 "chips": ["gfx10"], 8469 "map": {"at": 200700, "to": "mm"}, 8470 "name": "DB_ZPASS_COUNT_HI", 8471 "type_ref": "DB_OCCLUSION_COUNT0_HI" 8472 }, 8473 { 8474 "chips": ["gfx10"], 8475 "map": {"at": 200704, "to": "mm"}, 8476 "name": "GDS_RD_ADDR" 8477 }, 8478 { 8479 "chips": ["gfx10"], 8480 "map": {"at": 200708, "to": "mm"}, 8481 "name": "GDS_RD_DATA" 8482 }, 8483 { 8484 "chips": ["gfx10"], 8485 "map": {"at": 200712, "to": "mm"}, 8486 "name": "GDS_RD_BURST_ADDR" 8487 }, 8488 { 8489 "chips": ["gfx10"], 8490 "map": {"at": 200716, "to": "mm"}, 8491 "name": "GDS_RD_BURST_COUNT" 8492 }, 8493 { 8494 "chips": ["gfx10"], 8495 "map": {"at": 200720, "to": "mm"}, 8496 "name": "GDS_RD_BURST_DATA" 8497 }, 8498 { 8499 "chips": ["gfx10"], 8500 "map": {"at": 200724, "to": "mm"}, 8501 "name": "GDS_WR_ADDR" 8502 }, 8503 { 8504 "chips": ["gfx10"], 8505 "map": {"at": 200728, "to": "mm"}, 8506 "name": "GDS_WR_DATA" 8507 }, 8508 { 8509 "chips": ["gfx10"], 8510 "map": {"at": 200732, "to": "mm"}, 8511 "name": "GDS_WR_BURST_ADDR" 8512 }, 8513 { 8514 "chips": ["gfx10"], 8515 "map": {"at": 200736, "to": "mm"}, 8516 "name": "GDS_WR_BURST_DATA" 8517 }, 8518 { 8519 "chips": ["gfx10"], 8520 "map": {"at": 200740, "to": "mm"}, 8521 "name": "GDS_WRITE_COMPLETE" 8522 }, 8523 { 8524 "chips": ["gfx10"], 8525 "map": {"at": 200744, "to": "mm"}, 8526 "name": "GDS_ATOM_CNTL", 8527 "type_ref": "GDS_ATOM_CNTL" 8528 }, 8529 { 8530 "chips": ["gfx10"], 8531 "map": {"at": 200748, "to": "mm"}, 8532 "name": "GDS_ATOM_COMPLETE", 8533 "type_ref": "GDS_ATOM_COMPLETE" 8534 }, 8535 { 8536 "chips": ["gfx10"], 8537 "map": {"at": 200752, "to": "mm"}, 8538 "name": "GDS_ATOM_BASE", 8539 "type_ref": "GDS_ATOM_BASE" 8540 }, 8541 { 8542 "chips": ["gfx10"], 8543 "map": {"at": 200756, "to": "mm"}, 8544 "name": "GDS_ATOM_SIZE", 8545 "type_ref": "GDS_ATOM_SIZE" 8546 }, 8547 { 8548 "chips": ["gfx10"], 8549 "map": {"at": 200760, "to": "mm"}, 8550 "name": "GDS_ATOM_OFFSET0", 8551 "type_ref": "GDS_ATOM_OFFSET0" 8552 }, 8553 { 8554 "chips": ["gfx10"], 8555 "map": {"at": 200764, "to": "mm"}, 8556 "name": "GDS_ATOM_OFFSET1", 8557 "type_ref": "GDS_ATOM_OFFSET1" 8558 }, 8559 { 8560 "chips": ["gfx10"], 8561 "map": {"at": 200768, "to": "mm"}, 8562 "name": "GDS_ATOM_DST" 8563 }, 8564 { 8565 "chips": ["gfx10"], 8566 "map": {"at": 200772, "to": "mm"}, 8567 "name": "GDS_ATOM_OP", 8568 "type_ref": "GDS_ATOM_OP" 8569 }, 8570 { 8571 "chips": ["gfx10"], 8572 "map": {"at": 200776, "to": "mm"}, 8573 "name": "GDS_ATOM_SRC0" 8574 }, 8575 { 8576 "chips": ["gfx10"], 8577 "map": {"at": 200780, "to": "mm"}, 8578 "name": "GDS_ATOM_SRC0_U" 8579 }, 8580 { 8581 "chips": ["gfx10"], 8582 "map": {"at": 200784, "to": "mm"}, 8583 "name": "GDS_ATOM_SRC1" 8584 }, 8585 { 8586 "chips": ["gfx10"], 8587 "map": {"at": 200788, "to": "mm"}, 8588 "name": "GDS_ATOM_SRC1_U" 8589 }, 8590 { 8591 "chips": ["gfx10"], 8592 "map": {"at": 200792, "to": "mm"}, 8593 "name": "GDS_ATOM_READ0" 8594 }, 8595 { 8596 "chips": ["gfx10"], 8597 "map": {"at": 200796, "to": "mm"}, 8598 "name": "GDS_ATOM_READ0_U" 8599 }, 8600 { 8601 "chips": ["gfx10"], 8602 "map": {"at": 200800, "to": "mm"}, 8603 "name": "GDS_ATOM_READ1" 8604 }, 8605 { 8606 "chips": ["gfx10"], 8607 "map": {"at": 200804, "to": "mm"}, 8608 "name": "GDS_ATOM_READ1_U" 8609 }, 8610 { 8611 "chips": ["gfx10"], 8612 "map": {"at": 200808, "to": "mm"}, 8613 "name": "GDS_GWS_RESOURCE_CNTL", 8614 "type_ref": "GDS_GWS_RESOURCE_CNTL" 8615 }, 8616 { 8617 "chips": ["gfx10"], 8618 "map": {"at": 200812, "to": "mm"}, 8619 "name": "GDS_GWS_RESOURCE", 8620 "type_ref": "GDS_GWS_RESOURCE" 8621 }, 8622 { 8623 "chips": ["gfx10"], 8624 "map": {"at": 200816, "to": "mm"}, 8625 "name": "GDS_GWS_RESOURCE_CNT", 8626 "type_ref": "GDS_GWS_RESOURCE_CNT" 8627 }, 8628 { 8629 "chips": ["gfx10"], 8630 "map": {"at": 200820, "to": "mm"}, 8631 "name": "GDS_OA_CNTL", 8632 "type_ref": "GDS_OA_CNTL" 8633 }, 8634 { 8635 "chips": ["gfx10"], 8636 "map": {"at": 200824, "to": "mm"}, 8637 "name": "GDS_OA_COUNTER" 8638 }, 8639 { 8640 "chips": ["gfx10"], 8641 "map": {"at": 200828, "to": "mm"}, 8642 "name": "GDS_OA_ADDRESS", 8643 "type_ref": "GDS_OA_ADDRESS" 8644 }, 8645 { 8646 "chips": ["gfx10"], 8647 "map": {"at": 200832, "to": "mm"}, 8648 "name": "GDS_OA_INCDEC", 8649 "type_ref": "GDS_OA_INCDEC" 8650 }, 8651 { 8652 "chips": ["gfx10"], 8653 "map": {"at": 200836, "to": "mm"}, 8654 "name": "GDS_OA_RING_SIZE" 8655 }, 8656 { 8657 "chips": ["gfx10"], 8658 "map": {"at": 200960, "to": "mm"}, 8659 "name": "SPI_CONFIG_CNTL_REMAP" 8660 }, 8661 { 8662 "chips": ["gfx10"], 8663 "map": {"at": 200964, "to": "mm"}, 8664 "name": "SPI_CONFIG_CNTL_1_REMAP" 8665 }, 8666 { 8667 "chips": ["gfx10"], 8668 "map": {"at": 200968, "to": "mm"}, 8669 "name": "SPI_CONFIG_CNTL_2_REMAP" 8670 }, 8671 { 8672 "chips": ["gfx10"], 8673 "map": {"at": 200972, "to": "mm"}, 8674 "name": "SPI_WAVE_LIMIT_CNTL_REMAP" 8675 }, 8676 { 8677 "chips": ["gfx10"], 8678 "map": {"at": 212992, "to": "mm"}, 8679 "name": "CPG_PERFCOUNTER1_LO" 8680 }, 8681 { 8682 "chips": ["gfx10"], 8683 "map": {"at": 212996, "to": "mm"}, 8684 "name": "CPG_PERFCOUNTER1_HI" 8685 }, 8686 { 8687 "chips": ["gfx10"], 8688 "map": {"at": 213000, "to": "mm"}, 8689 "name": "CPG_PERFCOUNTER0_LO" 8690 }, 8691 { 8692 "chips": ["gfx10"], 8693 "map": {"at": 213004, "to": "mm"}, 8694 "name": "CPG_PERFCOUNTER0_HI" 8695 }, 8696 { 8697 "chips": ["gfx10"], 8698 "map": {"at": 213008, "to": "mm"}, 8699 "name": "CPC_PERFCOUNTER1_LO" 8700 }, 8701 { 8702 "chips": ["gfx10"], 8703 "map": {"at": 213012, "to": "mm"}, 8704 "name": "CPC_PERFCOUNTER1_HI" 8705 }, 8706 { 8707 "chips": ["gfx10"], 8708 "map": {"at": 213016, "to": "mm"}, 8709 "name": "CPC_PERFCOUNTER0_LO" 8710 }, 8711 { 8712 "chips": ["gfx10"], 8713 "map": {"at": 213020, "to": "mm"}, 8714 "name": "CPC_PERFCOUNTER0_HI" 8715 }, 8716 { 8717 "chips": ["gfx10"], 8718 "map": {"at": 213024, "to": "mm"}, 8719 "name": "CPF_PERFCOUNTER1_LO" 8720 }, 8721 { 8722 "chips": ["gfx10"], 8723 "map": {"at": 213028, "to": "mm"}, 8724 "name": "CPF_PERFCOUNTER1_HI" 8725 }, 8726 { 8727 "chips": ["gfx10"], 8728 "map": {"at": 213032, "to": "mm"}, 8729 "name": "CPF_PERFCOUNTER0_LO" 8730 }, 8731 { 8732 "chips": ["gfx10"], 8733 "map": {"at": 213036, "to": "mm"}, 8734 "name": "CPF_PERFCOUNTER0_HI" 8735 }, 8736 { 8737 "chips": ["gfx10"], 8738 "map": {"at": 213040, "to": "mm"}, 8739 "name": "CPF_LATENCY_STATS_DATA" 8740 }, 8741 { 8742 "chips": ["gfx10"], 8743 "map": {"at": 213044, "to": "mm"}, 8744 "name": "CPG_LATENCY_STATS_DATA" 8745 }, 8746 { 8747 "chips": ["gfx10"], 8748 "map": {"at": 213048, "to": "mm"}, 8749 "name": "CPC_LATENCY_STATS_DATA" 8750 }, 8751 { 8752 "chips": ["gfx10"], 8753 "map": {"at": 213248, "to": "mm"}, 8754 "name": "GRBM_PERFCOUNTER0_LO" 8755 }, 8756 { 8757 "chips": ["gfx10"], 8758 "map": {"at": 213252, "to": "mm"}, 8759 "name": "GRBM_PERFCOUNTER0_HI" 8760 }, 8761 { 8762 "chips": ["gfx10"], 8763 "map": {"at": 213260, "to": "mm"}, 8764 "name": "GRBM_PERFCOUNTER1_LO" 8765 }, 8766 { 8767 "chips": ["gfx10"], 8768 "map": {"at": 213264, "to": "mm"}, 8769 "name": "GRBM_PERFCOUNTER1_HI" 8770 }, 8771 { 8772 "chips": ["gfx10"], 8773 "map": {"at": 213268, "to": "mm"}, 8774 "name": "GRBM_SE0_PERFCOUNTER_LO" 8775 }, 8776 { 8777 "chips": ["gfx10"], 8778 "map": {"at": 213272, "to": "mm"}, 8779 "name": "GRBM_SE0_PERFCOUNTER_HI" 8780 }, 8781 { 8782 "chips": ["gfx10"], 8783 "map": {"at": 213276, "to": "mm"}, 8784 "name": "GRBM_SE1_PERFCOUNTER_LO" 8785 }, 8786 { 8787 "chips": ["gfx10"], 8788 "map": {"at": 213280, "to": "mm"}, 8789 "name": "GRBM_SE1_PERFCOUNTER_HI" 8790 }, 8791 { 8792 "chips": ["gfx10"], 8793 "map": {"at": 213284, "to": "mm"}, 8794 "name": "GRBM_SE2_PERFCOUNTER_LO" 8795 }, 8796 { 8797 "chips": ["gfx10"], 8798 "map": {"at": 213288, "to": "mm"}, 8799 "name": "GRBM_SE2_PERFCOUNTER_HI" 8800 }, 8801 { 8802 "chips": ["gfx10"], 8803 "map": {"at": 213292, "to": "mm"}, 8804 "name": "GRBM_SE3_PERFCOUNTER_LO" 8805 }, 8806 { 8807 "chips": ["gfx10"], 8808 "map": {"at": 213296, "to": "mm"}, 8809 "name": "GRBM_SE3_PERFCOUNTER_HI" 8810 }, 8811 { 8812 "chips": ["gfx10"], 8813 "map": {"at": 213504, "to": "mm"}, 8814 "name": "GE_PERFCOUNTER0_LO" 8815 }, 8816 { 8817 "chips": ["gfx10"], 8818 "map": {"at": 213508, "to": "mm"}, 8819 "name": "GE_PERFCOUNTER0_HI" 8820 }, 8821 { 8822 "chips": ["gfx10"], 8823 "map": {"at": 213512, "to": "mm"}, 8824 "name": "GE_PERFCOUNTER1_LO" 8825 }, 8826 { 8827 "chips": ["gfx10"], 8828 "map": {"at": 213516, "to": "mm"}, 8829 "name": "GE_PERFCOUNTER1_HI" 8830 }, 8831 { 8832 "chips": ["gfx10"], 8833 "map": {"at": 213520, "to": "mm"}, 8834 "name": "GE_PERFCOUNTER2_LO" 8835 }, 8836 { 8837 "chips": ["gfx10"], 8838 "map": {"at": 213524, "to": "mm"}, 8839 "name": "GE_PERFCOUNTER2_HI" 8840 }, 8841 { 8842 "chips": ["gfx10"], 8843 "map": {"at": 213528, "to": "mm"}, 8844 "name": "GE_PERFCOUNTER3_LO" 8845 }, 8846 { 8847 "chips": ["gfx10"], 8848 "map": {"at": 213532, "to": "mm"}, 8849 "name": "GE_PERFCOUNTER3_HI" 8850 }, 8851 { 8852 "chips": ["gfx10"], 8853 "map": {"at": 213536, "to": "mm"}, 8854 "name": "GE_PERFCOUNTER4_LO" 8855 }, 8856 { 8857 "chips": ["gfx10"], 8858 "map": {"at": 213540, "to": "mm"}, 8859 "name": "GE_PERFCOUNTER4_HI" 8860 }, 8861 { 8862 "chips": ["gfx10"], 8863 "map": {"at": 213544, "to": "mm"}, 8864 "name": "GE_PERFCOUNTER5_LO" 8865 }, 8866 { 8867 "chips": ["gfx10"], 8868 "map": {"at": 213548, "to": "mm"}, 8869 "name": "GE_PERFCOUNTER5_HI" 8870 }, 8871 { 8872 "chips": ["gfx10"], 8873 "map": {"at": 213552, "to": "mm"}, 8874 "name": "GE_PERFCOUNTER6_LO" 8875 }, 8876 { 8877 "chips": ["gfx10"], 8878 "map": {"at": 213556, "to": "mm"}, 8879 "name": "GE_PERFCOUNTER6_HI" 8880 }, 8881 { 8882 "chips": ["gfx10"], 8883 "map": {"at": 213560, "to": "mm"}, 8884 "name": "GE_PERFCOUNTER7_LO" 8885 }, 8886 { 8887 "chips": ["gfx10"], 8888 "map": {"at": 213564, "to": "mm"}, 8889 "name": "GE_PERFCOUNTER7_HI" 8890 }, 8891 { 8892 "chips": ["gfx10"], 8893 "map": {"at": 213568, "to": "mm"}, 8894 "name": "GE_PERFCOUNTER8_LO" 8895 }, 8896 { 8897 "chips": ["gfx10"], 8898 "map": {"at": 213572, "to": "mm"}, 8899 "name": "GE_PERFCOUNTER8_HI" 8900 }, 8901 { 8902 "chips": ["gfx10"], 8903 "map": {"at": 213576, "to": "mm"}, 8904 "name": "GE_PERFCOUNTER9_LO" 8905 }, 8906 { 8907 "chips": ["gfx10"], 8908 "map": {"at": 213580, "to": "mm"}, 8909 "name": "GE_PERFCOUNTER9_HI" 8910 }, 8911 { 8912 "chips": ["gfx10"], 8913 "map": {"at": 213584, "to": "mm"}, 8914 "name": "GE_PERFCOUNTER10_LO" 8915 }, 8916 { 8917 "chips": ["gfx10"], 8918 "map": {"at": 213588, "to": "mm"}, 8919 "name": "GE_PERFCOUNTER10_HI" 8920 }, 8921 { 8922 "chips": ["gfx10"], 8923 "map": {"at": 213592, "to": "mm"}, 8924 "name": "GE_PERFCOUNTER11_LO" 8925 }, 8926 { 8927 "chips": ["gfx10"], 8928 "map": {"at": 213596, "to": "mm"}, 8929 "name": "GE_PERFCOUNTER11_HI" 8930 }, 8931 { 8932 "chips": ["gfx10"], 8933 "map": {"at": 214016, "to": "mm"}, 8934 "name": "PA_SU_PERFCOUNTER0_LO" 8935 }, 8936 { 8937 "chips": ["gfx10"], 8938 "map": {"at": 214020, "to": "mm"}, 8939 "name": "PA_SU_PERFCOUNTER0_HI", 8940 "type_ref": "PA_SU_PERFCOUNTER0_HI" 8941 }, 8942 { 8943 "chips": ["gfx10"], 8944 "map": {"at": 214024, "to": "mm"}, 8945 "name": "PA_SU_PERFCOUNTER1_LO" 8946 }, 8947 { 8948 "chips": ["gfx10"], 8949 "map": {"at": 214028, "to": "mm"}, 8950 "name": "PA_SU_PERFCOUNTER1_HI", 8951 "type_ref": "PA_SU_PERFCOUNTER0_HI" 8952 }, 8953 { 8954 "chips": ["gfx10"], 8955 "map": {"at": 214032, "to": "mm"}, 8956 "name": "PA_SU_PERFCOUNTER2_LO" 8957 }, 8958 { 8959 "chips": ["gfx10"], 8960 "map": {"at": 214036, "to": "mm"}, 8961 "name": "PA_SU_PERFCOUNTER2_HI", 8962 "type_ref": "PA_SU_PERFCOUNTER0_HI" 8963 }, 8964 { 8965 "chips": ["gfx10"], 8966 "map": {"at": 214040, "to": "mm"}, 8967 "name": "PA_SU_PERFCOUNTER3_LO" 8968 }, 8969 { 8970 "chips": ["gfx10"], 8971 "map": {"at": 214044, "to": "mm"}, 8972 "name": "PA_SU_PERFCOUNTER3_HI", 8973 "type_ref": "PA_SU_PERFCOUNTER0_HI" 8974 }, 8975 { 8976 "chips": ["gfx10"], 8977 "map": {"at": 214272, "to": "mm"}, 8978 "name": "PA_SC_PERFCOUNTER0_LO" 8979 }, 8980 { 8981 "chips": ["gfx10"], 8982 "map": {"at": 214276, "to": "mm"}, 8983 "name": "PA_SC_PERFCOUNTER0_HI" 8984 }, 8985 { 8986 "chips": ["gfx10"], 8987 "map": {"at": 214280, "to": "mm"}, 8988 "name": "PA_SC_PERFCOUNTER1_LO" 8989 }, 8990 { 8991 "chips": ["gfx10"], 8992 "map": {"at": 214284, "to": "mm"}, 8993 "name": "PA_SC_PERFCOUNTER1_HI" 8994 }, 8995 { 8996 "chips": ["gfx10"], 8997 "map": {"at": 214288, "to": "mm"}, 8998 "name": "PA_SC_PERFCOUNTER2_LO" 8999 }, 9000 { 9001 "chips": ["gfx10"], 9002 "map": {"at": 214292, "to": "mm"}, 9003 "name": "PA_SC_PERFCOUNTER2_HI" 9004 }, 9005 { 9006 "chips": ["gfx10"], 9007 "map": {"at": 214296, "to": "mm"}, 9008 "name": "PA_SC_PERFCOUNTER3_LO" 9009 }, 9010 { 9011 "chips": ["gfx10"], 9012 "map": {"at": 214300, "to": "mm"}, 9013 "name": "PA_SC_PERFCOUNTER3_HI" 9014 }, 9015 { 9016 "chips": ["gfx10"], 9017 "map": {"at": 214304, "to": "mm"}, 9018 "name": "PA_SC_PERFCOUNTER4_LO" 9019 }, 9020 { 9021 "chips": ["gfx10"], 9022 "map": {"at": 214308, "to": "mm"}, 9023 "name": "PA_SC_PERFCOUNTER4_HI" 9024 }, 9025 { 9026 "chips": ["gfx10"], 9027 "map": {"at": 214312, "to": "mm"}, 9028 "name": "PA_SC_PERFCOUNTER5_LO" 9029 }, 9030 { 9031 "chips": ["gfx10"], 9032 "map": {"at": 214316, "to": "mm"}, 9033 "name": "PA_SC_PERFCOUNTER5_HI" 9034 }, 9035 { 9036 "chips": ["gfx10"], 9037 "map": {"at": 214320, "to": "mm"}, 9038 "name": "PA_SC_PERFCOUNTER6_LO" 9039 }, 9040 { 9041 "chips": ["gfx10"], 9042 "map": {"at": 214324, "to": "mm"}, 9043 "name": "PA_SC_PERFCOUNTER6_HI" 9044 }, 9045 { 9046 "chips": ["gfx10"], 9047 "map": {"at": 214328, "to": "mm"}, 9048 "name": "PA_SC_PERFCOUNTER7_LO" 9049 }, 9050 { 9051 "chips": ["gfx10"], 9052 "map": {"at": 214332, "to": "mm"}, 9053 "name": "PA_SC_PERFCOUNTER7_HI" 9054 }, 9055 { 9056 "chips": ["gfx10"], 9057 "map": {"at": 214528, "to": "mm"}, 9058 "name": "SPI_PERFCOUNTER0_HI" 9059 }, 9060 { 9061 "chips": ["gfx10"], 9062 "map": {"at": 214532, "to": "mm"}, 9063 "name": "SPI_PERFCOUNTER0_LO" 9064 }, 9065 { 9066 "chips": ["gfx10"], 9067 "map": {"at": 214536, "to": "mm"}, 9068 "name": "SPI_PERFCOUNTER1_HI" 9069 }, 9070 { 9071 "chips": ["gfx10"], 9072 "map": {"at": 214540, "to": "mm"}, 9073 "name": "SPI_PERFCOUNTER1_LO" 9074 }, 9075 { 9076 "chips": ["gfx10"], 9077 "map": {"at": 214544, "to": "mm"}, 9078 "name": "SPI_PERFCOUNTER2_HI" 9079 }, 9080 { 9081 "chips": ["gfx10"], 9082 "map": {"at": 214548, "to": "mm"}, 9083 "name": "SPI_PERFCOUNTER2_LO" 9084 }, 9085 { 9086 "chips": ["gfx10"], 9087 "map": {"at": 214552, "to": "mm"}, 9088 "name": "SPI_PERFCOUNTER3_HI" 9089 }, 9090 { 9091 "chips": ["gfx10"], 9092 "map": {"at": 214556, "to": "mm"}, 9093 "name": "SPI_PERFCOUNTER3_LO" 9094 }, 9095 { 9096 "chips": ["gfx10"], 9097 "map": {"at": 214560, "to": "mm"}, 9098 "name": "SPI_PERFCOUNTER4_HI" 9099 }, 9100 { 9101 "chips": ["gfx10"], 9102 "map": {"at": 214564, "to": "mm"}, 9103 "name": "SPI_PERFCOUNTER4_LO" 9104 }, 9105 { 9106 "chips": ["gfx10"], 9107 "map": {"at": 214568, "to": "mm"}, 9108 "name": "SPI_PERFCOUNTER5_HI" 9109 }, 9110 { 9111 "chips": ["gfx10"], 9112 "map": {"at": 214572, "to": "mm"}, 9113 "name": "SPI_PERFCOUNTER5_LO" 9114 }, 9115 { 9116 "chips": ["gfx10"], 9117 "map": {"at": 214784, "to": "mm"}, 9118 "name": "SQ_PERFCOUNTER0_LO" 9119 }, 9120 { 9121 "chips": ["gfx10"], 9122 "map": {"at": 214788, "to": "mm"}, 9123 "name": "SQ_PERFCOUNTER0_HI" 9124 }, 9125 { 9126 "chips": ["gfx10"], 9127 "map": {"at": 214792, "to": "mm"}, 9128 "name": "SQ_PERFCOUNTER1_LO" 9129 }, 9130 { 9131 "chips": ["gfx10"], 9132 "map": {"at": 214796, "to": "mm"}, 9133 "name": "SQ_PERFCOUNTER1_HI" 9134 }, 9135 { 9136 "chips": ["gfx10"], 9137 "map": {"at": 214800, "to": "mm"}, 9138 "name": "SQ_PERFCOUNTER2_LO" 9139 }, 9140 { 9141 "chips": ["gfx10"], 9142 "map": {"at": 214804, "to": "mm"}, 9143 "name": "SQ_PERFCOUNTER2_HI" 9144 }, 9145 { 9146 "chips": ["gfx10"], 9147 "map": {"at": 214808, "to": "mm"}, 9148 "name": "SQ_PERFCOUNTER3_LO" 9149 }, 9150 { 9151 "chips": ["gfx10"], 9152 "map": {"at": 214812, "to": "mm"}, 9153 "name": "SQ_PERFCOUNTER3_HI" 9154 }, 9155 { 9156 "chips": ["gfx10"], 9157 "map": {"at": 214816, "to": "mm"}, 9158 "name": "SQ_PERFCOUNTER4_LO" 9159 }, 9160 { 9161 "chips": ["gfx10"], 9162 "map": {"at": 214820, "to": "mm"}, 9163 "name": "SQ_PERFCOUNTER4_HI" 9164 }, 9165 { 9166 "chips": ["gfx10"], 9167 "map": {"at": 214824, "to": "mm"}, 9168 "name": "SQ_PERFCOUNTER5_LO" 9169 }, 9170 { 9171 "chips": ["gfx10"], 9172 "map": {"at": 214828, "to": "mm"}, 9173 "name": "SQ_PERFCOUNTER5_HI" 9174 }, 9175 { 9176 "chips": ["gfx10"], 9177 "map": {"at": 214832, "to": "mm"}, 9178 "name": "SQ_PERFCOUNTER6_LO" 9179 }, 9180 { 9181 "chips": ["gfx10"], 9182 "map": {"at": 214836, "to": "mm"}, 9183 "name": "SQ_PERFCOUNTER6_HI" 9184 }, 9185 { 9186 "chips": ["gfx10"], 9187 "map": {"at": 214840, "to": "mm"}, 9188 "name": "SQ_PERFCOUNTER7_LO" 9189 }, 9190 { 9191 "chips": ["gfx10"], 9192 "map": {"at": 214844, "to": "mm"}, 9193 "name": "SQ_PERFCOUNTER7_HI" 9194 }, 9195 { 9196 "chips": ["gfx10"], 9197 "map": {"at": 214848, "to": "mm"}, 9198 "name": "SQ_PERFCOUNTER8_LO" 9199 }, 9200 { 9201 "chips": ["gfx10"], 9202 "map": {"at": 214852, "to": "mm"}, 9203 "name": "SQ_PERFCOUNTER8_HI" 9204 }, 9205 { 9206 "chips": ["gfx10"], 9207 "map": {"at": 214856, "to": "mm"}, 9208 "name": "SQ_PERFCOUNTER9_LO" 9209 }, 9210 { 9211 "chips": ["gfx10"], 9212 "map": {"at": 214860, "to": "mm"}, 9213 "name": "SQ_PERFCOUNTER9_HI" 9214 }, 9215 { 9216 "chips": ["gfx10"], 9217 "map": {"at": 214864, "to": "mm"}, 9218 "name": "SQ_PERFCOUNTER10_LO" 9219 }, 9220 { 9221 "chips": ["gfx10"], 9222 "map": {"at": 214868, "to": "mm"}, 9223 "name": "SQ_PERFCOUNTER10_HI" 9224 }, 9225 { 9226 "chips": ["gfx10"], 9227 "map": {"at": 214872, "to": "mm"}, 9228 "name": "SQ_PERFCOUNTER11_LO" 9229 }, 9230 { 9231 "chips": ["gfx10"], 9232 "map": {"at": 214876, "to": "mm"}, 9233 "name": "SQ_PERFCOUNTER11_HI" 9234 }, 9235 { 9236 "chips": ["gfx10"], 9237 "map": {"at": 214880, "to": "mm"}, 9238 "name": "SQ_PERFCOUNTER12_LO" 9239 }, 9240 { 9241 "chips": ["gfx10"], 9242 "map": {"at": 214884, "to": "mm"}, 9243 "name": "SQ_PERFCOUNTER12_HI" 9244 }, 9245 { 9246 "chips": ["gfx10"], 9247 "map": {"at": 214888, "to": "mm"}, 9248 "name": "SQ_PERFCOUNTER13_LO" 9249 }, 9250 { 9251 "chips": ["gfx10"], 9252 "map": {"at": 214892, "to": "mm"}, 9253 "name": "SQ_PERFCOUNTER13_HI" 9254 }, 9255 { 9256 "chips": ["gfx10"], 9257 "map": {"at": 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219160, "to": "mm"}, 10030 "name": "CHA_PERFCOUNTER3_LO" 10031 }, 10032 { 10033 "chips": ["gfx10"], 10034 "map": {"at": 219164, "to": "mm"}, 10035 "name": "CHA_PERFCOUNTER3_HI" 10036 }, 10037 { 10038 "chips": ["gfx10"], 10039 "map": {"at": 219392, "to": "mm"}, 10040 "name": "GUS_PERFCOUNTER2_LO" 10041 }, 10042 { 10043 "chips": ["gfx10"], 10044 "map": {"at": 219396, "to": "mm"}, 10045 "name": "GUS_PERFCOUNTER2_HI" 10046 }, 10047 { 10048 "chips": ["gfx10"], 10049 "map": {"at": 221184, "to": "mm"}, 10050 "name": "CPG_PERFCOUNTER1_SELECT", 10051 "type_ref": "CPG_PERFCOUNTER1_SELECT" 10052 }, 10053 { 10054 "chips": ["gfx10"], 10055 "map": {"at": 221188, "to": "mm"}, 10056 "name": "CPG_PERFCOUNTER0_SELECT1", 10057 "type_ref": "CPG_PERFCOUNTER0_SELECT1" 10058 }, 10059 { 10060 "chips": ["gfx10"], 10061 "map": {"at": 221192, "to": "mm"}, 10062 "name": "CPG_PERFCOUNTER0_SELECT", 10063 "type_ref": "CPG_PERFCOUNTER1_SELECT" 10064 }, 10065 { 10066 "chips": ["gfx10"], 10067 "map": {"at": 221196, "to": "mm"}, 10068 "name": "CPC_PERFCOUNTER1_SELECT", 10069 "type_ref": "CPG_PERFCOUNTER1_SELECT" 10070 }, 10071 { 10072 "chips": ["gfx10"], 10073 "map": {"at": 221200, "to": "mm"}, 10074 "name": "CPC_PERFCOUNTER0_SELECT1", 10075 "type_ref": "CPG_PERFCOUNTER0_SELECT1" 10076 }, 10077 { 10078 "chips": ["gfx10"], 10079 "map": {"at": 221204, "to": "mm"}, 10080 "name": "CPF_PERFCOUNTER1_SELECT", 10081 "type_ref": "CPG_PERFCOUNTER1_SELECT" 10082 }, 10083 { 10084 "chips": ["gfx10"], 10085 "map": {"at": 221208, "to": "mm"}, 10086 "name": "CPF_PERFCOUNTER0_SELECT1", 10087 "type_ref": "CPG_PERFCOUNTER0_SELECT1" 10088 }, 10089 { 10090 "chips": ["gfx10"], 10091 "map": {"at": 221212, "to": "mm"}, 10092 "name": "CPF_PERFCOUNTER0_SELECT", 10093 "type_ref": "CPG_PERFCOUNTER1_SELECT" 10094 }, 10095 { 10096 "chips": ["gfx10"], 10097 "map": {"at": 221216, "to": "mm"}, 10098 "name": "CP_PERFMON_CNTL", 10099 "type_ref": "CP_PERFMON_CNTL" 10100 }, 10101 { 10102 "chips": ["gfx10"], 10103 "map": {"at": 221220, "to": "mm"}, 10104 "name": "CPC_PERFCOUNTER0_SELECT", 10105 "type_ref": "CPG_PERFCOUNTER1_SELECT" 10106 }, 10107 { 10108 "chips": ["gfx10"], 10109 "map": {"at": 221224, "to": "mm"}, 10110 "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT", 10111 "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT" 10112 }, 10113 { 10114 "chips": ["gfx10"], 10115 "map": {"at": 221228, "to": "mm"}, 10116 "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT", 10117 "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT" 10118 }, 10119 { 10120 "chips": ["gfx10"], 10121 "map": {"at": 221232, "to": "mm"}, 10122 "name": "CPF_LATENCY_STATS_SELECT", 10123 "type_ref": "CPF_LATENCY_STATS_SELECT" 10124 }, 10125 { 10126 "chips": ["gfx10"], 10127 "map": {"at": 221236, "to": "mm"}, 10128 "name": "CPG_LATENCY_STATS_SELECT", 10129 "type_ref": "CPG_LATENCY_STATS_SELECT" 10130 }, 10131 { 10132 "chips": ["gfx10"], 10133 "map": {"at": 221240, "to": "mm"}, 10134 "name": "CPC_LATENCY_STATS_SELECT", 10135 "type_ref": "CPF_LATENCY_STATS_SELECT" 10136 }, 10137 { 10138 "chips": ["gfx10"], 10139 "map": {"at": 221248, "to": "mm"}, 10140 "name": "CP_DRAW_OBJECT" 10141 }, 10142 { 10143 "chips": ["gfx10"], 10144 "map": {"at": 221252, "to": "mm"}, 10145 "name": "CP_DRAW_OBJECT_COUNTER", 10146 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 10147 }, 10148 { 10149 "chips": ["gfx10"], 10150 "map": {"at": 221256, "to": "mm"}, 10151 "name": "CP_DRAW_WINDOW_MASK_HI" 10152 }, 10153 { 10154 "chips": ["gfx10"], 10155 "map": {"at": 221260, "to": "mm"}, 10156 "name": "CP_DRAW_WINDOW_HI" 10157 }, 10158 { 10159 "chips": ["gfx10"], 10160 "map": {"at": 221264, "to": "mm"}, 10161 "name": "CP_DRAW_WINDOW_LO", 10162 "type_ref": "CP_DRAW_WINDOW_LO" 10163 }, 10164 { 10165 "chips": ["gfx10"], 10166 "map": {"at": 221268, "to": "mm"}, 10167 "name": "CP_DRAW_WINDOW_CNTL", 10168 "type_ref": "CP_DRAW_WINDOW_CNTL" 10169 }, 10170 { 10171 "chips": ["gfx10"], 10172 "map": {"at": 221440, "to": "mm"}, 10173 "name": "GRBM_PERFCOUNTER0_SELECT", 10174 "type_ref": "GRBM_PERFCOUNTER0_SELECT" 10175 }, 10176 { 10177 "chips": ["gfx10"], 10178 "map": {"at": 221444, "to": "mm"}, 10179 "name": "GRBM_PERFCOUNTER1_SELECT", 10180 "type_ref": "GRBM_PERFCOUNTER0_SELECT" 10181 }, 10182 { 10183 "chips": ["gfx10"], 10184 "map": {"at": 221448, "to": "mm"}, 10185 "name": "GRBM_SE0_PERFCOUNTER_SELECT", 10186 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 10187 }, 10188 { 10189 "chips": ["gfx10"], 10190 "map": {"at": 221452, "to": "mm"}, 10191 "name": "GRBM_SE1_PERFCOUNTER_SELECT", 10192 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 10193 }, 10194 { 10195 "chips": ["gfx10"], 10196 "map": {"at": 221456, "to": "mm"}, 10197 "name": "GRBM_SE2_PERFCOUNTER_SELECT", 10198 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 10199 }, 10200 { 10201 "chips": ["gfx10"], 10202 "map": {"at": 221460, "to": "mm"}, 10203 "name": "GRBM_SE3_PERFCOUNTER_SELECT", 10204 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 10205 }, 10206 { 10207 "chips": ["gfx10"], 10208 "map": {"at": 221492, "to": "mm"}, 10209 "name": "GRBM_PERFCOUNTER0_SELECT_HI", 10210 "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI" 10211 }, 10212 { 10213 "chips": ["gfx10"], 10214 "map": {"at": 221496, "to": "mm"}, 10215 "name": "GRBM_PERFCOUNTER1_SELECT_HI", 10216 "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI" 10217 }, 10218 { 10219 "chips": ["gfx10"], 10220 "map": {"at": 221696, "to": "mm"}, 10221 "name": "GE_PERFCOUNTER0_SELECT", 10222 "type_ref": "GE_PERFCOUNTER0_SELECT" 10223 }, 10224 { 10225 "chips": ["gfx10"], 10226 "map": {"at": 221700, "to": "mm"}, 10227 "name": "GE_PERFCOUNTER0_SELECT1", 10228 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10229 }, 10230 { 10231 "chips": ["gfx10"], 10232 "map": {"at": 221704, "to": "mm"}, 10233 "name": "GE_PERFCOUNTER1_SELECT", 10234 "type_ref": "GE_PERFCOUNTER0_SELECT" 10235 }, 10236 { 10237 "chips": ["gfx10"], 10238 "map": {"at": 221708, "to": "mm"}, 10239 "name": "GE_PERFCOUNTER1_SELECT1", 10240 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10241 }, 10242 { 10243 "chips": ["gfx10"], 10244 "map": {"at": 221712, "to": "mm"}, 10245 "name": "GE_PERFCOUNTER2_SELECT", 10246 "type_ref": "GE_PERFCOUNTER0_SELECT" 10247 }, 10248 { 10249 "chips": ["gfx10"], 10250 "map": {"at": 221716, "to": "mm"}, 10251 "name": "GE_PERFCOUNTER2_SELECT1", 10252 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10253 }, 10254 { 10255 "chips": ["gfx10"], 10256 "map": {"at": 221720, "to": "mm"}, 10257 "name": "GE_PERFCOUNTER3_SELECT", 10258 "type_ref": "GE_PERFCOUNTER0_SELECT" 10259 }, 10260 { 10261 "chips": ["gfx10"], 10262 "map": {"at": 221724, "to": "mm"}, 10263 "name": "GE_PERFCOUNTER3_SELECT1", 10264 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10265 }, 10266 { 10267 "chips": ["gfx10"], 10268 "map": {"at": 221728, "to": "mm"}, 10269 "name": "GE_PERFCOUNTER4_SELECT", 10270 "type_ref": "GE_PERFCOUNTER4_SELECT" 10271 }, 10272 { 10273 "chips": ["gfx10"], 10274 "map": {"at": 221736, "to": "mm"}, 10275 "name": "GE_PERFCOUNTER5_SELECT", 10276 "type_ref": "GE_PERFCOUNTER4_SELECT" 10277 }, 10278 { 10279 "chips": ["gfx10"], 10280 "map": {"at": 221744, "to": "mm"}, 10281 "name": "GE_PERFCOUNTER6_SELECT", 10282 "type_ref": "GE_PERFCOUNTER4_SELECT" 10283 }, 10284 { 10285 "chips": ["gfx10"], 10286 "map": {"at": 221752, "to": "mm"}, 10287 "name": "GE_PERFCOUNTER7_SELECT", 10288 "type_ref": "GE_PERFCOUNTER4_SELECT" 10289 }, 10290 { 10291 "chips": ["gfx10"], 10292 "map": {"at": 221760, "to": "mm"}, 10293 "name": "GE_PERFCOUNTER8_SELECT", 10294 "type_ref": "GE_PERFCOUNTER4_SELECT" 10295 }, 10296 { 10297 "chips": ["gfx10"], 10298 "map": {"at": 221768, "to": "mm"}, 10299 "name": "GE_PERFCOUNTER9_SELECT", 10300 "type_ref": "GE_PERFCOUNTER4_SELECT" 10301 }, 10302 { 10303 "chips": ["gfx10"], 10304 "map": {"at": 221776, "to": "mm"}, 10305 "name": "GE_PERFCOUNTER10_SELECT", 10306 "type_ref": "GE_PERFCOUNTER4_SELECT" 10307 }, 10308 { 10309 "chips": ["gfx10"], 10310 "map": {"at": 221784, "to": "mm"}, 10311 "name": "GE_PERFCOUNTER11_SELECT", 10312 "type_ref": "GE_PERFCOUNTER4_SELECT" 10313 }, 10314 { 10315 "chips": ["gfx10"], 10316 "map": {"at": 222208, "to": "mm"}, 10317 "name": "PA_SU_PERFCOUNTER0_SELECT", 10318 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10319 }, 10320 { 10321 "chips": ["gfx10"], 10322 "map": {"at": 222212, "to": "mm"}, 10323 "name": "PA_SU_PERFCOUNTER0_SELECT1", 10324 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10325 }, 10326 { 10327 "chips": ["gfx10"], 10328 "map": {"at": 222216, "to": "mm"}, 10329 "name": "PA_SU_PERFCOUNTER1_SELECT", 10330 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10331 }, 10332 { 10333 "chips": ["gfx10"], 10334 "map": {"at": 222220, "to": "mm"}, 10335 "name": "PA_SU_PERFCOUNTER1_SELECT1", 10336 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10337 }, 10338 { 10339 "chips": ["gfx10"], 10340 "map": {"at": 222224, "to": "mm"}, 10341 "name": "PA_SU_PERFCOUNTER2_SELECT", 10342 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10343 }, 10344 { 10345 "chips": ["gfx10"], 10346 "map": {"at": 222228, "to": "mm"}, 10347 "name": "PA_SU_PERFCOUNTER2_SELECT1", 10348 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10349 }, 10350 { 10351 "chips": ["gfx10"], 10352 "map": {"at": 222232, "to": "mm"}, 10353 "name": "PA_SU_PERFCOUNTER3_SELECT", 10354 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10355 }, 10356 { 10357 "chips": ["gfx10"], 10358 "map": {"at": 222236, "to": "mm"}, 10359 "name": "PA_SU_PERFCOUNTER3_SELECT1", 10360 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10361 }, 10362 { 10363 "chips": ["gfx10"], 10364 "map": {"at": 222464, "to": "mm"}, 10365 "name": "PA_SC_PERFCOUNTER0_SELECT", 10366 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10367 }, 10368 { 10369 "chips": ["gfx10"], 10370 "map": {"at": 222468, "to": "mm"}, 10371 "name": "PA_SC_PERFCOUNTER0_SELECT1", 10372 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10373 }, 10374 { 10375 "chips": ["gfx10"], 10376 "map": {"at": 222472, "to": "mm"}, 10377 "name": "PA_SC_PERFCOUNTER1_SELECT", 10378 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10379 }, 10380 { 10381 "chips": ["gfx10"], 10382 "map": {"at": 222476, "to": "mm"}, 10383 "name": "PA_SC_PERFCOUNTER2_SELECT", 10384 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10385 }, 10386 { 10387 "chips": ["gfx10"], 10388 "map": {"at": 222480, "to": "mm"}, 10389 "name": "PA_SC_PERFCOUNTER3_SELECT", 10390 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10391 }, 10392 { 10393 "chips": ["gfx10"], 10394 "map": {"at": 222484, "to": "mm"}, 10395 "name": "PA_SC_PERFCOUNTER4_SELECT", 10396 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10397 }, 10398 { 10399 "chips": ["gfx10"], 10400 "map": {"at": 222488, "to": "mm"}, 10401 "name": "PA_SC_PERFCOUNTER5_SELECT", 10402 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10403 }, 10404 { 10405 "chips": ["gfx10"], 10406 "map": {"at": 222492, "to": "mm"}, 10407 "name": "PA_SC_PERFCOUNTER6_SELECT", 10408 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10409 }, 10410 { 10411 "chips": ["gfx10"], 10412 "map": {"at": 222496, "to": "mm"}, 10413 "name": "PA_SC_PERFCOUNTER7_SELECT", 10414 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10415 }, 10416 { 10417 "chips": ["gfx10"], 10418 "map": {"at": 222720, "to": "mm"}, 10419 "name": "SPI_PERFCOUNTER0_SELECT", 10420 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10421 }, 10422 { 10423 "chips": ["gfx10"], 10424 "map": {"at": 222724, "to": "mm"}, 10425 "name": "SPI_PERFCOUNTER1_SELECT", 10426 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10427 }, 10428 { 10429 "chips": ["gfx10"], 10430 "map": {"at": 222728, "to": "mm"}, 10431 "name": "SPI_PERFCOUNTER2_SELECT", 10432 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10433 }, 10434 { 10435 "chips": ["gfx10"], 10436 "map": {"at": 222732, "to": "mm"}, 10437 "name": "SPI_PERFCOUNTER3_SELECT", 10438 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10439 }, 10440 { 10441 "chips": ["gfx10"], 10442 "map": {"at": 222736, "to": "mm"}, 10443 "name": "SPI_PERFCOUNTER0_SELECT1", 10444 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10445 }, 10446 { 10447 "chips": ["gfx10"], 10448 "map": {"at": 222740, "to": "mm"}, 10449 "name": "SPI_PERFCOUNTER1_SELECT1", 10450 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10451 }, 10452 { 10453 "chips": ["gfx10"], 10454 "map": {"at": 222744, "to": "mm"}, 10455 "name": "SPI_PERFCOUNTER2_SELECT1", 10456 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10457 }, 10458 { 10459 "chips": ["gfx10"], 10460 "map": {"at": 222748, "to": "mm"}, 10461 "name": "SPI_PERFCOUNTER3_SELECT1", 10462 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10463 }, 10464 { 10465 "chips": ["gfx10"], 10466 "map": {"at": 222752, "to": "mm"}, 10467 "name": "SPI_PERFCOUNTER4_SELECT", 10468 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10469 }, 10470 { 10471 "chips": ["gfx10"], 10472 "map": {"at": 222756, "to": "mm"}, 10473 "name": "SPI_PERFCOUNTER5_SELECT", 10474 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 10475 }, 10476 { 10477 "chips": ["gfx10"], 10478 "map": {"at": 222760, "to": "mm"}, 10479 "name": "SPI_PERFCOUNTER_BINS", 10480 "type_ref": "SPI_PERFCOUNTER_BINS" 10481 }, 10482 { 10483 "chips": ["gfx10"], 10484 "map": {"at": 222976, "to": "mm"}, 10485 "name": "SQ_PERFCOUNTER0_SELECT", 10486 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10487 }, 10488 { 10489 "chips": ["gfx10"], 10490 "map": {"at": 222980, "to": "mm"}, 10491 "name": "SQ_PERFCOUNTER1_SELECT", 10492 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10493 }, 10494 { 10495 "chips": ["gfx10"], 10496 "map": {"at": 222984, "to": "mm"}, 10497 "name": "SQ_PERFCOUNTER2_SELECT", 10498 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10499 }, 10500 { 10501 "chips": ["gfx10"], 10502 "map": {"at": 222988, "to": "mm"}, 10503 "name": "SQ_PERFCOUNTER3_SELECT", 10504 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10505 }, 10506 { 10507 "chips": ["gfx10"], 10508 "map": {"at": 222992, "to": "mm"}, 10509 "name": "SQ_PERFCOUNTER4_SELECT", 10510 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10511 }, 10512 { 10513 "chips": ["gfx10"], 10514 "map": {"at": 222996, "to": "mm"}, 10515 "name": "SQ_PERFCOUNTER5_SELECT", 10516 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10517 }, 10518 { 10519 "chips": ["gfx10"], 10520 "map": {"at": 223000, "to": "mm"}, 10521 "name": "SQ_PERFCOUNTER6_SELECT", 10522 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10523 }, 10524 { 10525 "chips": ["gfx10"], 10526 "map": {"at": 223004, "to": "mm"}, 10527 "name": "SQ_PERFCOUNTER7_SELECT", 10528 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10529 }, 10530 { 10531 "chips": ["gfx10"], 10532 "map": {"at": 223008, "to": "mm"}, 10533 "name": "SQ_PERFCOUNTER8_SELECT", 10534 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10535 }, 10536 { 10537 "chips": ["gfx10"], 10538 "map": {"at": 223012, "to": "mm"}, 10539 "name": "SQ_PERFCOUNTER9_SELECT", 10540 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10541 }, 10542 { 10543 "chips": ["gfx10"], 10544 "map": {"at": 223016, "to": "mm"}, 10545 "name": "SQ_PERFCOUNTER10_SELECT", 10546 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10547 }, 10548 { 10549 "chips": ["gfx10"], 10550 "map": {"at": 223020, "to": "mm"}, 10551 "name": "SQ_PERFCOUNTER11_SELECT", 10552 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10553 }, 10554 { 10555 "chips": ["gfx10"], 10556 "map": {"at": 223024, "to": "mm"}, 10557 "name": "SQ_PERFCOUNTER12_SELECT", 10558 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10559 }, 10560 { 10561 "chips": ["gfx10"], 10562 "map": {"at": 223028, "to": "mm"}, 10563 "name": "SQ_PERFCOUNTER13_SELECT", 10564 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10565 }, 10566 { 10567 "chips": ["gfx10"], 10568 "map": {"at": 223032, "to": "mm"}, 10569 "name": "SQ_PERFCOUNTER14_SELECT", 10570 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10571 }, 10572 { 10573 "chips": ["gfx10"], 10574 "map": {"at": 223036, "to": "mm"}, 10575 "name": "SQ_PERFCOUNTER15_SELECT", 10576 "type_ref": "SQ_PERFCOUNTER0_SELECT" 10577 }, 10578 { 10579 "chips": ["gfx10"], 10580 "map": {"at": 223104, "to": "mm"}, 10581 "name": "SQ_PERFCOUNTER_CTRL", 10582 "type_ref": "SQ_PERFCOUNTER_CTRL" 10583 }, 10584 { 10585 "chips": ["gfx10"], 10586 "map": {"at": 223112, "to": "mm"}, 10587 "name": "SQ_PERFCOUNTER_CTRL2", 10588 "type_ref": "SQ_PERFCOUNTER_CTRL2" 10589 }, 10590 { 10591 "chips": ["gfx10"], 10592 "map": {"at": 223232, "to": "mm"}, 10593 "name": "GCEA_PERFCOUNTER2_SELECT", 10594 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10595 }, 10596 { 10597 "chips": ["gfx10"], 10598 "map": {"at": 223236, "to": "mm"}, 10599 "name": "GCEA_PERFCOUNTER2_SELECT1", 10600 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10601 }, 10602 { 10603 "chips": ["gfx10"], 10604 "map": {"at": 223240, "to": "mm"}, 10605 "name": "GCEA_PERFCOUNTER2_MODE", 10606 "type_ref": "GCEA_PERFCOUNTER2_MODE" 10607 }, 10608 { 10609 "chips": ["gfx10"], 10610 "map": {"at": 223488, "to": "mm"}, 10611 "name": "SX_PERFCOUNTER0_SELECT", 10612 "type_ref": "SX_PERFCOUNTER0_SELECT" 10613 }, 10614 { 10615 "chips": ["gfx10"], 10616 "map": {"at": 223492, "to": "mm"}, 10617 "name": "SX_PERFCOUNTER1_SELECT", 10618 "type_ref": "SX_PERFCOUNTER0_SELECT" 10619 }, 10620 { 10621 "chips": ["gfx10"], 10622 "map": {"at": 223496, "to": "mm"}, 10623 "name": "SX_PERFCOUNTER2_SELECT", 10624 "type_ref": "SX_PERFCOUNTER0_SELECT" 10625 }, 10626 { 10627 "chips": ["gfx10"], 10628 "map": {"at": 223500, "to": "mm"}, 10629 "name": "SX_PERFCOUNTER3_SELECT", 10630 "type_ref": "SX_PERFCOUNTER0_SELECT" 10631 }, 10632 { 10633 "chips": ["gfx10"], 10634 "map": {"at": 223504, "to": "mm"}, 10635 "name": "SX_PERFCOUNTER0_SELECT1", 10636 "type_ref": "SX_PERFCOUNTER0_SELECT1" 10637 }, 10638 { 10639 "chips": ["gfx10"], 10640 "map": {"at": 223508, "to": "mm"}, 10641 "name": "SX_PERFCOUNTER1_SELECT1", 10642 "type_ref": "SX_PERFCOUNTER0_SELECT1" 10643 }, 10644 { 10645 "chips": ["gfx10"], 10646 "map": {"at": 223744, "to": "mm"}, 10647 "name": "GDS_PERFCOUNTER0_SELECT", 10648 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10649 }, 10650 { 10651 "chips": ["gfx10"], 10652 "map": {"at": 223748, "to": "mm"}, 10653 "name": "GDS_PERFCOUNTER1_SELECT", 10654 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10655 }, 10656 { 10657 "chips": ["gfx10"], 10658 "map": {"at": 223752, "to": "mm"}, 10659 "name": "GDS_PERFCOUNTER2_SELECT", 10660 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10661 }, 10662 { 10663 "chips": ["gfx10"], 10664 "map": {"at": 223756, "to": "mm"}, 10665 "name": "GDS_PERFCOUNTER3_SELECT", 10666 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10667 }, 10668 { 10669 "chips": ["gfx10"], 10670 "map": {"at": 223760, "to": "mm"}, 10671 "name": "GDS_PERFCOUNTER0_SELECT1", 10672 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10673 }, 10674 { 10675 "chips": ["gfx10"], 10676 "map": {"at": 224000, "to": "mm"}, 10677 "name": "TA_PERFCOUNTER0_SELECT", 10678 "type_ref": "TA_PERFCOUNTER0_SELECT" 10679 }, 10680 { 10681 "chips": ["gfx10"], 10682 "map": {"at": 224004, "to": "mm"}, 10683 "name": "TA_PERFCOUNTER0_SELECT1", 10684 "type_ref": "TA_PERFCOUNTER0_SELECT1" 10685 }, 10686 { 10687 "chips": ["gfx10"], 10688 "map": {"at": 224008, "to": "mm"}, 10689 "name": "TA_PERFCOUNTER1_SELECT", 10690 "type_ref": "TA_PERFCOUNTER1_SELECT" 10691 }, 10692 { 10693 "chips": ["gfx10"], 10694 "map": {"at": 224256, "to": "mm"}, 10695 "name": "TD_PERFCOUNTER0_SELECT", 10696 "type_ref": "TA_PERFCOUNTER0_SELECT" 10697 }, 10698 { 10699 "chips": ["gfx10"], 10700 "map": {"at": 224260, "to": "mm"}, 10701 "name": "TD_PERFCOUNTER0_SELECT1", 10702 "type_ref": "TA_PERFCOUNTER0_SELECT1" 10703 }, 10704 { 10705 "chips": ["gfx10"], 10706 "map": {"at": 224264, "to": "mm"}, 10707 "name": "TD_PERFCOUNTER1_SELECT", 10708 "type_ref": "TA_PERFCOUNTER1_SELECT" 10709 }, 10710 { 10711 "chips": ["gfx10"], 10712 "map": {"at": 224512, "to": "mm"}, 10713 "name": "TCP_PERFCOUNTER0_SELECT", 10714 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10715 }, 10716 { 10717 "chips": ["gfx10"], 10718 "map": {"at": 224516, "to": "mm"}, 10719 "name": "TCP_PERFCOUNTER0_SELECT1", 10720 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10721 }, 10722 { 10723 "chips": ["gfx10"], 10724 "map": {"at": 224520, "to": "mm"}, 10725 "name": "TCP_PERFCOUNTER1_SELECT", 10726 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10727 }, 10728 { 10729 "chips": ["gfx10"], 10730 "map": {"at": 224524, "to": "mm"}, 10731 "name": "TCP_PERFCOUNTER1_SELECT1", 10732 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10733 }, 10734 { 10735 "chips": ["gfx10"], 10736 "map": {"at": 224528, "to": "mm"}, 10737 "name": "TCP_PERFCOUNTER2_SELECT", 10738 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10739 }, 10740 { 10741 "chips": ["gfx10"], 10742 "map": {"at": 224532, "to": "mm"}, 10743 "name": "TCP_PERFCOUNTER3_SELECT", 10744 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10745 }, 10746 { 10747 "chips": ["gfx10"], 10748 "map": {"at": 224768, "to": "mm"}, 10749 "name": "GL2C_PERFCOUNTER0_SELECT", 10750 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10751 }, 10752 { 10753 "chips": ["gfx10"], 10754 "map": {"at": 224772, "to": "mm"}, 10755 "name": "GL2C_PERFCOUNTER0_SELECT1", 10756 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10757 }, 10758 { 10759 "chips": ["gfx10"], 10760 "map": {"at": 224776, "to": "mm"}, 10761 "name": "GL2C_PERFCOUNTER1_SELECT", 10762 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10763 }, 10764 { 10765 "chips": ["gfx10"], 10766 "map": {"at": 224780, "to": "mm"}, 10767 "name": "GL2C_PERFCOUNTER1_SELECT1", 10768 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10769 }, 10770 { 10771 "chips": ["gfx10"], 10772 "map": {"at": 224784, "to": "mm"}, 10773 "name": "GL2C_PERFCOUNTER2_SELECT", 10774 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10775 }, 10776 { 10777 "chips": ["gfx10"], 10778 "map": {"at": 224788, "to": "mm"}, 10779 "name": "GL2C_PERFCOUNTER3_SELECT", 10780 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10781 }, 10782 { 10783 "chips": ["gfx10"], 10784 "map": {"at": 224832, "to": "mm"}, 10785 "name": "GL2A_PERFCOUNTER0_SELECT", 10786 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10787 }, 10788 { 10789 "chips": ["gfx10"], 10790 "map": {"at": 224836, "to": "mm"}, 10791 "name": "GL2A_PERFCOUNTER0_SELECT1", 10792 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10793 }, 10794 { 10795 "chips": ["gfx10"], 10796 "map": {"at": 224840, "to": "mm"}, 10797 "name": "GL2A_PERFCOUNTER1_SELECT", 10798 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10799 }, 10800 { 10801 "chips": ["gfx10"], 10802 "map": {"at": 224844, "to": "mm"}, 10803 "name": "GL2A_PERFCOUNTER1_SELECT1", 10804 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10805 }, 10806 { 10807 "chips": ["gfx10"], 10808 "map": {"at": 224848, "to": "mm"}, 10809 "name": "GL2A_PERFCOUNTER2_SELECT", 10810 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10811 }, 10812 { 10813 "chips": ["gfx10"], 10814 "map": {"at": 224852, "to": "mm"}, 10815 "name": "GL2A_PERFCOUNTER3_SELECT", 10816 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10817 }, 10818 { 10819 "chips": ["gfx10"], 10820 "map": {"at": 224896, "to": "mm"}, 10821 "name": "GL1C_PERFCOUNTER0_SELECT", 10822 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10823 }, 10824 { 10825 "chips": ["gfx10"], 10826 "map": {"at": 224900, "to": "mm"}, 10827 "name": "GL1C_PERFCOUNTER0_SELECT1", 10828 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10829 }, 10830 { 10831 "chips": ["gfx10"], 10832 "map": {"at": 224904, "to": "mm"}, 10833 "name": "GL1C_PERFCOUNTER1_SELECT", 10834 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10835 }, 10836 { 10837 "chips": ["gfx10"], 10838 "map": {"at": 224908, "to": "mm"}, 10839 "name": "GL1C_PERFCOUNTER2_SELECT", 10840 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10841 }, 10842 { 10843 "chips": ["gfx10"], 10844 "map": {"at": 224912, "to": "mm"}, 10845 "name": "GL1C_PERFCOUNTER3_SELECT", 10846 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10847 }, 10848 { 10849 "chips": ["gfx10"], 10850 "map": {"at": 225024, "to": "mm"}, 10851 "name": "CHC_PERFCOUNTER0_SELECT", 10852 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10853 }, 10854 { 10855 "chips": ["gfx10"], 10856 "map": {"at": 225028, "to": "mm"}, 10857 "name": "CHC_PERFCOUNTER0_SELECT1", 10858 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10859 }, 10860 { 10861 "chips": ["gfx10"], 10862 "map": {"at": 225032, "to": "mm"}, 10863 "name": "CHC_PERFCOUNTER1_SELECT", 10864 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10865 }, 10866 { 10867 "chips": ["gfx10"], 10868 "map": {"at": 225036, "to": "mm"}, 10869 "name": "CHC_PERFCOUNTER2_SELECT", 10870 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10871 }, 10872 { 10873 "chips": ["gfx10"], 10874 "map": {"at": 225040, "to": "mm"}, 10875 "name": "CHC_PERFCOUNTER3_SELECT", 10876 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10877 }, 10878 { 10879 "chips": ["gfx10"], 10880 "map": {"at": 225048, "to": "mm"}, 10881 "name": "CHCG_PERFCOUNTER0_SELECT", 10882 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10883 }, 10884 { 10885 "chips": ["gfx10"], 10886 "map": {"at": 225052, "to": "mm"}, 10887 "name": "CHCG_PERFCOUNTER0_SELECT1", 10888 "type_ref": "GE_PERFCOUNTER0_SELECT1" 10889 }, 10890 { 10891 "chips": ["gfx10"], 10892 "map": {"at": 225056, "to": "mm"}, 10893 "name": "CHCG_PERFCOUNTER1_SELECT", 10894 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10895 }, 10896 { 10897 "chips": ["gfx10"], 10898 "map": {"at": 225060, "to": "mm"}, 10899 "name": "CHCG_PERFCOUNTER2_SELECT", 10900 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10901 }, 10902 { 10903 "chips": ["gfx10"], 10904 "map": {"at": 225064, "to": "mm"}, 10905 "name": "CHCG_PERFCOUNTER3_SELECT", 10906 "type_ref": "TCP_PERFCOUNTER2_SELECT" 10907 }, 10908 { 10909 "chips": ["gfx10"], 10910 "map": {"at": 225280, "to": "mm"}, 10911 "name": "CB_PERFCOUNTER_FILTER", 10912 "type_ref": "CB_PERFCOUNTER_FILTER" 10913 }, 10914 { 10915 "chips": ["gfx10"], 10916 "map": {"at": 225284, "to": "mm"}, 10917 "name": "CB_PERFCOUNTER0_SELECT", 10918 "type_ref": "CB_PERFCOUNTER0_SELECT" 10919 }, 10920 { 10921 "chips": ["gfx10"], 10922 "map": {"at": 225288, "to": "mm"}, 10923 "name": "CB_PERFCOUNTER0_SELECT1", 10924 "type_ref": "CB_PERFCOUNTER0_SELECT1" 10925 }, 10926 { 10927 "chips": ["gfx10"], 10928 "map": {"at": 225292, "to": "mm"}, 10929 "name": "CB_PERFCOUNTER1_SELECT", 10930 "type_ref": "CB_PERFCOUNTER1_SELECT" 10931 }, 10932 { 10933 "chips": ["gfx10"], 10934 "map": {"at": 225296, "to": "mm"}, 10935 "name": "CB_PERFCOUNTER2_SELECT", 10936 "type_ref": "CB_PERFCOUNTER1_SELECT" 10937 }, 10938 { 10939 "chips": ["gfx10"], 10940 "map": {"at": 225300, "to": "mm"}, 10941 "name": "CB_PERFCOUNTER3_SELECT", 10942 "type_ref": "CB_PERFCOUNTER1_SELECT" 10943 }, 10944 { 10945 "chips": ["gfx10"], 10946 "map": {"at": 225536, "to": "mm"}, 10947 "name": "DB_PERFCOUNTER0_SELECT", 10948 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10949 }, 10950 { 10951 "chips": ["gfx10"], 10952 "map": {"at": 225540, "to": "mm"}, 10953 "name": "DB_PERFCOUNTER0_SELECT1", 10954 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10955 }, 10956 { 10957 "chips": ["gfx10"], 10958 "map": {"at": 225544, "to": "mm"}, 10959 "name": "DB_PERFCOUNTER1_SELECT", 10960 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10961 }, 10962 { 10963 "chips": ["gfx10"], 10964 "map": {"at": 225548, "to": "mm"}, 10965 "name": "DB_PERFCOUNTER1_SELECT1", 10966 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 10967 }, 10968 { 10969 "chips": ["gfx10"], 10970 "map": {"at": 225552, "to": "mm"}, 10971 "name": "DB_PERFCOUNTER2_SELECT", 10972 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10973 }, 10974 { 10975 "chips": ["gfx10"], 10976 "map": {"at": 225560, "to": "mm"}, 10977 "name": "DB_PERFCOUNTER3_SELECT", 10978 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 10979 }, 10980 { 10981 "chips": ["gfx10"], 10982 "map": {"at": 225792, "to": "mm"}, 10983 "name": "RLC_SPM_PERFMON_CNTL", 10984 "type_ref": "RLC_SPM_PERFMON_CNTL" 10985 }, 10986 { 10987 "chips": ["gfx10"], 10988 "map": {"at": 225796, "to": "mm"}, 10989 "name": "RLC_SPM_PERFMON_RING_BASE_LO" 10990 }, 10991 { 10992 "chips": ["gfx10"], 10993 "map": {"at": 225800, "to": "mm"}, 10994 "name": "RLC_SPM_PERFMON_RING_BASE_HI", 10995 "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI" 10996 }, 10997 { 10998 "chips": ["gfx10"], 10999 "map": {"at": 225804, "to": "mm"}, 11000 "name": "RLC_SPM_PERFMON_RING_SIZE" 11001 }, 11002 { 11003 "chips": ["gfx10"], 11004 "map": {"at": 225808, "to": "mm"}, 11005 "name": "RLC_SPM_PERFMON_SEGMENT_SIZE", 11006 "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE" 11007 }, 11008 { 11009 "chips": ["gfx10"], 11010 "map": {"at": 225812, "to": "mm"}, 11011 "name": "RLC_SPM_RING_RDPTR" 11012 }, 11013 { 11014 "chips": ["gfx10"], 11015 "map": {"at": 225816, "to": "mm"}, 11016 "name": "RLC_SPM_SEGMENT_THRESHOLD", 11017 "type_ref": "RLC_SPM_SEGMENT_THRESHOLD" 11018 }, 11019 { 11020 "chips": ["gfx10"], 11021 "map": {"at": 225820, "to": "mm"}, 11022 "name": "RLC_SPM_SE_MUXSEL_ADDR", 11023 "type_ref": "RLC_SPM_SE_MUXSEL_ADDR" 11024 }, 11025 { 11026 "chips": ["gfx10"], 11027 "map": {"at": 225824, "to": "mm"}, 11028 "name": "RLC_SPM_SE_MUXSEL_DATA" 11029 }, 11030 { 11031 "chips": ["gfx10"], 11032 "map": {"at": 225828, "to": "mm"}, 11033 "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR", 11034 "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR" 11035 }, 11036 { 11037 "chips": ["gfx10"], 11038 "map": {"at": 225832, "to": "mm"}, 11039 "name": "RLC_SPM_GLOBAL_MUXSEL_DATA" 11040 }, 11041 { 11042 "chips": ["gfx10"], 11043 "map": {"at": 225836, "to": "mm"}, 11044 "name": "RLC_SPM_DESER_START_SKEW", 11045 "type_ref": "RLC_SPM_DESER_START_SKEW" 11046 }, 11047 { 11048 "chips": ["gfx10"], 11049 "map": {"at": 225840, "to": "mm"}, 11050 "name": "RLC_SPM_GLOBALS_SAMPLE_SKEW", 11051 "type_ref": "RLC_SPM_GLOBALS_SAMPLE_SKEW" 11052 }, 11053 { 11054 "chips": ["gfx10"], 11055 "map": {"at": 225844, "to": "mm"}, 11056 "name": "RLC_SPM_GLOBALS_MUXSEL_SKEW", 11057 "type_ref": "RLC_SPM_GLOBALS_MUXSEL_SKEW" 11058 }, 11059 { 11060 "chips": ["gfx10"], 11061 "map": {"at": 225848, "to": "mm"}, 11062 "name": "RLC_SPM_SE_SAMPLE_SKEW", 11063 "type_ref": "RLC_SPM_SE_SAMPLE_SKEW" 11064 }, 11065 { 11066 "chips": ["gfx10"], 11067 "map": {"at": 225852, "to": "mm"}, 11068 "name": "RLC_SPM_SE_MUXSEL_SKEW", 11069 "type_ref": "RLC_SPM_SE_MUXSEL_SKEW" 11070 }, 11071 { 11072 "chips": ["gfx10"], 11073 "map": {"at": 225856, "to": "mm"}, 11074 "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR" 11075 }, 11076 { 11077 "chips": ["gfx10"], 11078 "map": {"at": 225860, "to": "mm"}, 11079 "name": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA", 11080 "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA" 11081 }, 11082 { 11083 "chips": ["gfx10"], 11084 "map": {"at": 225864, "to": "mm"}, 11085 "name": "RLC_SPM_SE_SAMPLEDELAY_IND_ADDR" 11086 }, 11087 { 11088 "chips": ["gfx10"], 11089 "map": {"at": 225868, "to": "mm"}, 11090 "name": "RLC_SPM_SE_SAMPLEDELAY_IND_DATA", 11091 "type_ref": "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA" 11092 }, 11093 { 11094 "chips": ["gfx10"], 11095 "map": {"at": 225872, "to": "mm"}, 11096 "name": "RLC_SPM_RING_WRPTR", 11097 "type_ref": "RLC_SPM_RING_WRPTR" 11098 }, 11099 { 11100 "chips": ["gfx10"], 11101 "map": {"at": 225876, "to": "mm"}, 11102 "name": "RLC_SPM_ACCUM_DATARAM_ADDR", 11103 "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR" 11104 }, 11105 { 11106 "chips": ["gfx10"], 11107 "map": {"at": 225880, "to": "mm"}, 11108 "name": "RLC_SPM_ACCUM_DATARAM_DATA" 11109 }, 11110 { 11111 "chips": ["gfx10"], 11112 "map": {"at": 225884, "to": "mm"}, 11113 "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR", 11114 "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR" 11115 }, 11116 { 11117 "chips": ["gfx10"], 11118 "map": {"at": 225888, "to": "mm"}, 11119 "name": "RLC_SPM_ACCUM_CTRLRAM_DATA", 11120 "type_ref": "RLC_SPM_ACCUM_CTRLRAM_DATA" 11121 }, 11122 { 11123 "chips": ["gfx10"], 11124 "map": {"at": 225892, "to": "mm"}, 11125 "name": "RLC_SPM_ACCUM_STATUS", 11126 "type_ref": "RLC_SPM_ACCUM_STATUS" 11127 }, 11128 { 11129 "chips": ["gfx10"], 11130 "map": {"at": 225896, "to": "mm"}, 11131 "name": "RLC_SPM_ACCUM_CTRL", 11132 "type_ref": "RLC_SPM_ACCUM_CTRL" 11133 }, 11134 { 11135 "chips": ["gfx10"], 11136 "map": {"at": 225900, "to": "mm"}, 11137 "name": "RLC_SPM_ACCUM_MODE", 11138 "type_ref": "RLC_SPM_ACCUM_MODE" 11139 }, 11140 { 11141 "chips": ["gfx10"], 11142 "map": {"at": 225904, "to": "mm"}, 11143 "name": "RLC_SPM_ACCUM_THRESHOLD", 11144 "type_ref": "RLC_SPM_ACCUM_THRESHOLD" 11145 }, 11146 { 11147 "chips": ["gfx10"], 11148 "map": {"at": 225908, "to": "mm"}, 11149 "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED", 11150 "type_ref": "RLC_SPM_ACCUM_SAMPLES_REQUESTED" 11151 }, 11152 { 11153 "chips": ["gfx10"], 11154 "map": {"at": 225912, "to": "mm"}, 11155 "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT", 11156 "type_ref": "RLC_SPM_ACCUM_DATARAM_WRCOUNT" 11157 }, 11158 { 11159 "chips": ["gfx10"], 11160 "map": {"at": 225916, "to": "mm"}, 11161 "name": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE", 11162 "type_ref": "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE" 11163 }, 11164 { 11165 "chips": ["gfx10"], 11166 "map": {"at": 225920, "to": "mm"}, 11167 "name": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE", 11168 "type_ref": "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE" 11169 }, 11170 { 11171 "chips": ["gfx10"], 11172 "map": {"at": 225924, "to": "mm"}, 11173 "name": "RLC_SPM_VIRT_CTRL", 11174 "type_ref": "RLC_SPM_VIRT_CTRL" 11175 }, 11176 { 11177 "chips": ["gfx10"], 11178 "map": {"at": 225932, "to": "mm"}, 11179 "name": "RLC_SPM_VIRT_STATUS", 11180 "type_ref": "RLC_SPM_VIRT_STATUS" 11181 }, 11182 { 11183 "chips": ["gfx10"], 11184 "map": {"at": 226048, "to": "mm"}, 11185 "name": "RLC_PERFMON_CNTL", 11186 "type_ref": "RLC_PERFMON_CNTL" 11187 }, 11188 { 11189 "chips": ["gfx10"], 11190 "map": {"at": 226052, "to": "mm"}, 11191 "name": "RLC_PERFCOUNTER0_SELECT", 11192 "type_ref": "RLC_PERFCOUNTER0_SELECT" 11193 }, 11194 { 11195 "chips": ["gfx10"], 11196 "map": {"at": 226056, "to": "mm"}, 11197 "name": "RLC_PERFCOUNTER1_SELECT", 11198 "type_ref": "RLC_PERFCOUNTER0_SELECT" 11199 }, 11200 { 11201 "chips": ["gfx10"], 11202 "map": {"at": 226060, "to": "mm"}, 11203 "name": "RLC_GPU_IOV_PERF_CNT_CNTL", 11204 "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL" 11205 }, 11206 { 11207 "chips": ["gfx10"], 11208 "map": {"at": 226064, "to": "mm"}, 11209 "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR", 11210 "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR" 11211 }, 11212 { 11213 "chips": ["gfx10"], 11214 "map": {"at": 226068, "to": "mm"}, 11215 "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA" 11216 }, 11217 { 11218 "chips": ["gfx10"], 11219 "map": {"at": 226072, "to": "mm"}, 11220 "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR", 11221 "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR" 11222 }, 11223 { 11224 "chips": ["gfx10"], 11225 "map": {"at": 226076, "to": "mm"}, 11226 "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA" 11227 }, 11228 { 11229 "chips": ["gfx10"], 11230 "map": {"at": 226192, "to": "mm"}, 11231 "name": "RLC_PERFMON_CLK_CNTL", 11232 "type_ref": "RLC_PERFMON_CLK_CNTL" 11233 }, 11234 { 11235 "chips": ["gfx10"], 11236 "map": {"at": 226196, "to": "mm"}, 11237 "name": "RLC_PERFMON_CLK_CNTL_UCODE", 11238 "type_ref": "RLC_PERFMON_CLK_CNTL" 11239 }, 11240 { 11241 "chips": ["gfx10"], 11242 "map": {"at": 226304, "to": "mm"}, 11243 "name": "RMI_PERFCOUNTER0_SELECT", 11244 "type_ref": "CB_PERFCOUNTER0_SELECT" 11245 }, 11246 { 11247 "chips": ["gfx10"], 11248 "map": {"at": 226308, "to": "mm"}, 11249 "name": "RMI_PERFCOUNTER0_SELECT1", 11250 "type_ref": "CB_PERFCOUNTER0_SELECT1" 11251 }, 11252 { 11253 "chips": ["gfx10"], 11254 "map": {"at": 226312, "to": "mm"}, 11255 "name": "RMI_PERFCOUNTER1_SELECT", 11256 "type_ref": "CB_PERFCOUNTER1_SELECT" 11257 }, 11258 { 11259 "chips": ["gfx10"], 11260 "map": {"at": 226316, "to": "mm"}, 11261 "name": "RMI_PERFCOUNTER2_SELECT", 11262 "type_ref": "CB_PERFCOUNTER0_SELECT" 11263 }, 11264 { 11265 "chips": ["gfx10"], 11266 "map": {"at": 226320, "to": "mm"}, 11267 "name": "RMI_PERFCOUNTER2_SELECT1", 11268 "type_ref": "CB_PERFCOUNTER0_SELECT1" 11269 }, 11270 { 11271 "chips": ["gfx10"], 11272 "map": {"at": 226324, "to": "mm"}, 11273 "name": "RMI_PERFCOUNTER3_SELECT", 11274 "type_ref": "CB_PERFCOUNTER1_SELECT" 11275 }, 11276 { 11277 "chips": ["gfx10"], 11278 "map": {"at": 226328, "to": "mm"}, 11279 "name": "RMI_PERF_COUNTER_CNTL", 11280 "type_ref": "RMI_PERF_COUNTER_CNTL" 11281 }, 11282 { 11283 "chips": ["gfx10"], 11284 "map": {"at": 226432, "to": "mm"}, 11285 "name": "GC_ATC_L2_PERFCOUNTER0_CFG", 11286 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11287 }, 11288 { 11289 "chips": ["gfx10"], 11290 "map": {"at": 226436, "to": "mm"}, 11291 "name": "GC_ATC_L2_PERFCOUNTER1_CFG", 11292 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11293 }, 11294 { 11295 "chips": ["gfx10"], 11296 "map": {"at": 226440, "to": "mm"}, 11297 "name": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL", 11298 "type_ref": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL" 11299 }, 11300 { 11301 "chips": ["gfx10"], 11302 "map": {"at": 226480, "to": "mm"}, 11303 "name": "GCMC_VM_L2_PERFCOUNTER0_CFG", 11304 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11305 }, 11306 { 11307 "chips": ["gfx10"], 11308 "map": {"at": 226484, "to": "mm"}, 11309 "name": "GCMC_VM_L2_PERFCOUNTER1_CFG", 11310 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11311 }, 11312 { 11313 "chips": ["gfx10"], 11314 "map": {"at": 226488, "to": "mm"}, 11315 "name": "GCMC_VM_L2_PERFCOUNTER2_CFG", 11316 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11317 }, 11318 { 11319 "chips": ["gfx10"], 11320 "map": {"at": 226492, "to": "mm"}, 11321 "name": "GCMC_VM_L2_PERFCOUNTER3_CFG", 11322 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11323 }, 11324 { 11325 "chips": ["gfx10"], 11326 "map": {"at": 226496, "to": "mm"}, 11327 "name": "GCMC_VM_L2_PERFCOUNTER4_CFG", 11328 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11329 }, 11330 { 11331 "chips": ["gfx10"], 11332 "map": {"at": 226500, "to": "mm"}, 11333 "name": "GCMC_VM_L2_PERFCOUNTER5_CFG", 11334 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11335 }, 11336 { 11337 "chips": ["gfx10"], 11338 "map": {"at": 226504, "to": "mm"}, 11339 "name": "GCMC_VM_L2_PERFCOUNTER6_CFG", 11340 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11341 }, 11342 { 11343 "chips": ["gfx10"], 11344 "map": {"at": 226508, "to": "mm"}, 11345 "name": "GCMC_VM_L2_PERFCOUNTER7_CFG", 11346 "type_ref": "GC_ATC_L2_PERFCOUNTER0_CFG" 11347 }, 11348 { 11349 "chips": ["gfx10"], 11350 "map": {"at": 226512, "to": "mm"}, 11351 "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL", 11352 "type_ref": "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL" 11353 }, 11354 { 11355 "chips": ["gfx10"], 11356 "map": {"at": 226544, "to": "mm"}, 11357 "name": "GCVML2_PERFCOUNTER2_0_SELECT", 11358 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11359 }, 11360 { 11361 "chips": ["gfx10"], 11362 "map": {"at": 226548, "to": "mm"}, 11363 "name": "GCVML2_PERFCOUNTER2_1_SELECT", 11364 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11365 }, 11366 { 11367 "chips": ["gfx10"], 11368 "map": {"at": 226552, "to": "mm"}, 11369 "name": "GCVML2_PERFCOUNTER2_0_SELECT1", 11370 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 11371 }, 11372 { 11373 "chips": ["gfx10"], 11374 "map": {"at": 226556, "to": "mm"}, 11375 "name": "GCVML2_PERFCOUNTER2_1_SELECT1", 11376 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 11377 }, 11378 { 11379 "chips": ["gfx10"], 11380 "map": {"at": 226560, "to": "mm"}, 11381 "name": "GCVML2_PERFCOUNTER2_0_MODE", 11382 "type_ref": "GCEA_PERFCOUNTER2_MODE" 11383 }, 11384 { 11385 "chips": ["gfx10"], 11386 "map": {"at": 226564, "to": "mm"}, 11387 "name": "GCVML2_PERFCOUNTER2_1_MODE", 11388 "type_ref": "GCEA_PERFCOUNTER2_MODE" 11389 }, 11390 { 11391 "chips": ["gfx10"], 11392 "map": {"at": 226608, "to": "mm"}, 11393 "name": "GC_ATC_L2_PERFCOUNTER2_SELECT", 11394 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11395 }, 11396 { 11397 "chips": ["gfx10"], 11398 "map": {"at": 226612, "to": "mm"}, 11399 "name": "GC_ATC_L2_PERFCOUNTER2_SELECT1", 11400 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 11401 }, 11402 { 11403 "chips": ["gfx10"], 11404 "map": {"at": 226616, "to": "mm"}, 11405 "name": "GC_ATC_L2_PERFCOUNTER2_MODE", 11406 "type_ref": "GCEA_PERFCOUNTER2_MODE" 11407 }, 11408 { 11409 "chips": ["gfx10"], 11410 "map": {"at": 226688, "to": "mm"}, 11411 "name": "GCR_PERFCOUNTER0_SELECT", 11412 "type_ref": "CB_PERFCOUNTER0_SELECT" 11413 }, 11414 { 11415 "chips": ["gfx10"], 11416 "map": {"at": 226692, "to": "mm"}, 11417 "name": "GCR_PERFCOUNTER0_SELECT1", 11418 "type_ref": "CB_PERFCOUNTER0_SELECT1" 11419 }, 11420 { 11421 "chips": ["gfx10"], 11422 "map": {"at": 226696, "to": "mm"}, 11423 "name": "GCR_PERFCOUNTER1_SELECT", 11424 "type_ref": "GCR_PERFCOUNTER1_SELECT" 11425 }, 11426 { 11427 "chips": ["gfx10"], 11428 "map": {"at": 226700, "to": "mm"}, 11429 "name": "UTCL1_PERFCOUNTER0_SELECT", 11430 "type_ref": "UTCL1_PERFCOUNTER0_SELECT" 11431 }, 11432 { 11433 "chips": ["gfx10"], 11434 "map": {"at": 226704, "to": "mm"}, 11435 "name": "UTCL1_PERFCOUNTER1_SELECT", 11436 "type_ref": "UTCL1_PERFCOUNTER0_SELECT" 11437 }, 11438 { 11439 "chips": ["gfx10"], 11440 "map": {"at": 226816, "to": "mm"}, 11441 "name": "PA_PH_PERFCOUNTER0_SELECT", 11442 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11443 }, 11444 { 11445 "chips": ["gfx10"], 11446 "map": {"at": 226820, "to": "mm"}, 11447 "name": "PA_PH_PERFCOUNTER0_SELECT1", 11448 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 11449 }, 11450 { 11451 "chips": ["gfx10"], 11452 "map": {"at": 226824, "to": "mm"}, 11453 "name": "PA_PH_PERFCOUNTER1_SELECT", 11454 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11455 }, 11456 { 11457 "chips": ["gfx10"], 11458 "map": {"at": 226828, "to": "mm"}, 11459 "name": "PA_PH_PERFCOUNTER2_SELECT", 11460 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11461 }, 11462 { 11463 "chips": ["gfx10"], 11464 "map": {"at": 226832, "to": "mm"}, 11465 "name": "PA_PH_PERFCOUNTER3_SELECT", 11466 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11467 }, 11468 { 11469 "chips": ["gfx10"], 11470 "map": {"at": 226836, "to": "mm"}, 11471 "name": "PA_PH_PERFCOUNTER4_SELECT", 11472 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 11473 }, 11474 { 11475 "chips": ["gfx10"], 11476 "map": {"at": 226840, "to": "mm"}, 11477 "name": "PA_PH_PERFCOUNTER5_SELECT", 11478 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 11479 }, 11480 { 11481 "chips": ["gfx10"], 11482 "map": {"at": 226844, "to": "mm"}, 11483 "name": "PA_PH_PERFCOUNTER6_SELECT", 11484 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 11485 }, 11486 { 11487 "chips": ["gfx10"], 11488 "map": {"at": 226848, "to": "mm"}, 11489 "name": "PA_PH_PERFCOUNTER7_SELECT", 11490 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 11491 }, 11492 { 11493 "chips": ["gfx10"], 11494 "map": {"at": 226880, "to": "mm"}, 11495 "name": "PA_PH_PERFCOUNTER1_SELECT1", 11496 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 11497 }, 11498 { 11499 "chips": ["gfx10"], 11500 "map": {"at": 226884, "to": "mm"}, 11501 "name": "PA_PH_PERFCOUNTER2_SELECT1", 11502 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 11503 }, 11504 { 11505 "chips": ["gfx10"], 11506 "map": {"at": 226888, "to": "mm"}, 11507 "name": "PA_PH_PERFCOUNTER3_SELECT1", 11508 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 11509 }, 11510 { 11511 "chips": ["gfx10"], 11512 "map": {"at": 227072, "to": "mm"}, 11513 "name": "GL1A_PERFCOUNTER0_SELECT", 11514 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11515 }, 11516 { 11517 "chips": ["gfx10"], 11518 "map": {"at": 227076, "to": "mm"}, 11519 "name": "GL1A_PERFCOUNTER0_SELECT1", 11520 "type_ref": "GE_PERFCOUNTER0_SELECT1" 11521 }, 11522 { 11523 "chips": ["gfx10"], 11524 "map": {"at": 227080, "to": "mm"}, 11525 "name": "GL1A_PERFCOUNTER1_SELECT", 11526 "type_ref": "TCP_PERFCOUNTER2_SELECT" 11527 }, 11528 { 11529 "chips": ["gfx10"], 11530 "map": {"at": 227084, "to": "mm"}, 11531 "name": "GL1A_PERFCOUNTER2_SELECT", 11532 "type_ref": "TCP_PERFCOUNTER2_SELECT" 11533 }, 11534 { 11535 "chips": ["gfx10"], 11536 "map": {"at": 227088, "to": "mm"}, 11537 "name": "GL1A_PERFCOUNTER3_SELECT", 11538 "type_ref": "TCP_PERFCOUNTER2_SELECT" 11539 }, 11540 { 11541 "chips": ["gfx10"], 11542 "map": {"at": 227200, "to": "mm"}, 11543 "name": "CHA_PERFCOUNTER0_SELECT", 11544 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11545 }, 11546 { 11547 "chips": ["gfx10"], 11548 "map": {"at": 227204, "to": "mm"}, 11549 "name": "CHA_PERFCOUNTER0_SELECT1", 11550 "type_ref": "GE_PERFCOUNTER0_SELECT1" 11551 }, 11552 { 11553 "chips": ["gfx10"], 11554 "map": {"at": 227208, "to": "mm"}, 11555 "name": "CHA_PERFCOUNTER1_SELECT", 11556 "type_ref": "TCP_PERFCOUNTER2_SELECT" 11557 }, 11558 { 11559 "chips": ["gfx10"], 11560 "map": {"at": 227212, "to": "mm"}, 11561 "name": "CHA_PERFCOUNTER2_SELECT", 11562 "type_ref": "TCP_PERFCOUNTER2_SELECT" 11563 }, 11564 { 11565 "chips": ["gfx10"], 11566 "map": {"at": 227216, "to": "mm"}, 11567 "name": "CHA_PERFCOUNTER3_SELECT", 11568 "type_ref": "TCP_PERFCOUNTER2_SELECT" 11569 }, 11570 { 11571 "chips": ["gfx10"], 11572 "map": {"at": 227328, "to": "mm"}, 11573 "name": "GUS_PERFCOUNTER2_SELECT", 11574 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 11575 }, 11576 { 11577 "chips": ["gfx10"], 11578 "map": {"at": 227332, "to": "mm"}, 11579 "name": "GUS_PERFCOUNTER2_SELECT1", 11580 "type_ref": "PA_SU_PERFCOUNTER0_SELECT1" 11581 }, 11582 { 11583 "chips": ["gfx10"], 11584 "map": {"at": 227336, "to": "mm"}, 11585 "name": "GUS_PERFCOUNTER2_MODE", 11586 "type_ref": "GCEA_PERFCOUNTER2_MODE" 11587 } 11588 ], 11589 "register_types": { 11590 "CB_BLEND0_CONTROL": { 11591 "fields": [ 11592 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, 11593 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, 11594 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, 11595 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, 11596 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, 11597 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, 11598 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, 11599 {"bits": [30, 30], "name": "ENABLE"}, 11600 {"bits": [31, 31], "name": "DISABLE_ROP3"} 11601 ] 11602 }, 11603 "CB_COLOR0_ATTRIB": { 11604 "fields": [ 11605 {"bits": [0, 4], "name": "TILE_MODE_INDEX"}, 11606 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, 11607 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, 11608 {"bits": [12, 14], "name": "NUM_SAMPLES"}, 11609 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, 11610 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}, 11611 {"bits": [18, 18], "name": "DISABLE_FMASK_NOFETCH_OPT"}, 11612 {"bits": [19, 19], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"} 11613 ] 11614 }, 11615 "CB_COLOR0_ATTRIB2": { 11616 "fields": [ 11617 {"bits": [0, 13], "name": "MIP0_HEIGHT"}, 11618 {"bits": [14, 27], "name": "MIP0_WIDTH"}, 11619 {"bits": [28, 31], "name": "MAX_MIP"} 11620 ] 11621 }, 11622 "CB_COLOR0_ATTRIB3": { 11623 "fields": [ 11624 {"bits": [0, 12], "name": "MIP0_DEPTH"}, 11625 {"bits": [13, 13], "name": "META_LINEAR"}, 11626 {"bits": [14, 18], "name": "COLOR_SW_MODE"}, 11627 {"bits": [19, 23], "name": "FMASK_SW_MODE"}, 11628 {"bits": [24, 25], "name": "RESOURCE_TYPE"}, 11629 {"bits": [26, 26], "name": "CMASK_PIPE_ALIGNED"}, 11630 {"bits": [27, 29], "name": "RESOURCE_LEVEL"}, 11631 {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"} 11632 ] 11633 }, 11634 "CB_COLOR0_BASE_EXT": { 11635 "fields": [ 11636 {"bits": [0, 7], "name": "BASE_256B"} 11637 ] 11638 }, 11639 "CB_COLOR0_CMASK_SLICE": { 11640 "fields": [ 11641 {"bits": [0, 13], "name": "TILE_MAX"} 11642 ] 11643 }, 11644 "CB_COLOR0_DCC_CONTROL": { 11645 "fields": [ 11646 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, 11647 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"}, 11648 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, 11649 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"}, 11650 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"}, 11651 {"bits": [7, 8], "name": "COLOR_TRANSFORM"}, 11652 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"}, 11653 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"}, 11654 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}, 11655 {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"}, 11656 {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"}, 11657 {"bits": [20, 20], "name": "INDEPENDENT_128B_BLOCKS"} 11658 ] 11659 }, 11660 "CB_COLOR0_INFO": { 11661 "fields": [ 11662 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, 11663 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, 11664 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, 11665 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, 11666 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, 11667 {"bits": [13, 13], "name": "FAST_CLEAR"}, 11668 {"bits": [14, 14], "name": "COMPRESSION"}, 11669 {"bits": [15, 15], "name": "BLEND_CLAMP"}, 11670 {"bits": [16, 16], "name": "BLEND_BYPASS"}, 11671 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, 11672 {"bits": [18, 18], "name": "ROUND_MODE"}, 11673 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, 11674 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, 11675 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, 11676 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"}, 11677 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"}, 11678 {"bits": [28, 28], "name": "DCC_ENABLE"}, 11679 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}, 11680 {"bits": [31, 31], "name": "ALT_TILE_MODE"} 11681 ] 11682 }, 11683 "CB_COLOR0_PITCH": { 11684 "fields": [ 11685 {"bits": [0, 10], "name": "TILE_MAX"}, 11686 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} 11687 ] 11688 }, 11689 "CB_COLOR0_SLICE": { 11690 "fields": [ 11691 {"bits": [0, 21], "name": "TILE_MAX"} 11692 ] 11693 }, 11694 "CB_COLOR0_VIEW": { 11695 "fields": [ 11696 {"bits": [0, 12], "name": "SLICE_START"}, 11697 {"bits": [13, 25], "name": "SLICE_MAX"}, 11698 {"bits": [26, 29], "name": "MIP_LEVEL"} 11699 ] 11700 }, 11701 "CB_COLOR_CONTROL": { 11702 "fields": [ 11703 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"}, 11704 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, 11705 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, 11706 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} 11707 ] 11708 }, 11709 "CB_COVERAGE_OUT_CONTROL": { 11710 "fields": [ 11711 {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"}, 11712 {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"}, 11713 {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"}, 11714 {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"} 11715 ] 11716 }, 11717 "CB_DCC_CONTROL": { 11718 "fields": [ 11719 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, 11720 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}, 11721 {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"}, 11722 {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"}, 11723 {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"}, 11724 {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"}, 11725 {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"}, 11726 {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"} 11727 ] 11728 }, 11729 "CB_PERFCOUNTER0_SELECT": { 11730 "fields": [ 11731 {"bits": [0, 8], "name": "PERF_SEL"}, 11732 {"bits": [10, 18], "name": "PERF_SEL1"}, 11733 {"bits": [20, 23], "name": "CNTR_MODE"}, 11734 {"bits": [24, 27], "name": "PERF_MODE1"}, 11735 {"bits": [28, 31], "name": "PERF_MODE"} 11736 ] 11737 }, 11738 "CB_PERFCOUNTER0_SELECT1": { 11739 "fields": [ 11740 {"bits": [0, 8], "name": "PERF_SEL2"}, 11741 {"bits": [10, 18], "name": "PERF_SEL3"}, 11742 {"bits": [24, 27], "name": "PERF_MODE3"}, 11743 {"bits": [28, 31], "name": "PERF_MODE2"} 11744 ] 11745 }, 11746 "CB_PERFCOUNTER1_SELECT": { 11747 "fields": [ 11748 {"bits": [0, 8], "name": "PERF_SEL"}, 11749 {"bits": [28, 31], "name": "PERF_MODE"} 11750 ] 11751 }, 11752 "CB_PERFCOUNTER_FILTER": { 11753 "fields": [ 11754 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"}, 11755 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, 11756 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"}, 11757 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"}, 11758 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"}, 11759 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, 11760 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"}, 11761 {"bits": [13, 15], "name": "MRT_FILTER_SEL"}, 11762 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"}, 11763 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"}, 11764 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"}, 11765 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"} 11766 ] 11767 }, 11768 "CB_RMI_GL2_CACHE_CONTROL": { 11769 "fields": [ 11770 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"}, 11771 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"}, 11772 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"}, 11773 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"}, 11774 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"}, 11775 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"}, 11776 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"}, 11777 {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"}, 11778 {"bits": [30, 30], "name": "FMASK_BIG_PAGE"}, 11779 {"bits": [31, 31], "name": "COLOR_BIG_PAGE"} 11780 ] 11781 }, 11782 "CB_SHADER_MASK": { 11783 "fields": [ 11784 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, 11785 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, 11786 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, 11787 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, 11788 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, 11789 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, 11790 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, 11791 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} 11792 ] 11793 }, 11794 "CB_TARGET_MASK": { 11795 "fields": [ 11796 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, 11797 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, 11798 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, 11799 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, 11800 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, 11801 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, 11802 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, 11803 {"bits": [28, 31], "name": "TARGET7_ENABLE"} 11804 ] 11805 }, 11806 "COHER_DEST_BASE_HI_0": { 11807 "fields": [ 11808 {"bits": [0, 7], "name": "DEST_BASE_HI_256B"} 11809 ] 11810 }, 11811 "COMPUTE_DDID_INDEX": { 11812 "fields": [ 11813 {"bits": [0, 10], "name": "INDEX"} 11814 ] 11815 }, 11816 "COMPUTE_DISPATCH_INITIATOR": { 11817 "fields": [ 11818 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, 11819 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, 11820 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, 11821 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, 11822 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, 11823 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, 11824 {"bits": [6, 6], "name": "ORDER_MODE"}, 11825 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, 11826 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, 11827 {"bits": [12, 12], "name": "RESERVED"}, 11828 {"bits": [13, 13], "name": "TUNNEL_ENABLE"}, 11829 {"bits": [14, 14], "name": "RESTORE"}, 11830 {"bits": [15, 15], "name": "CS_W32_EN"} 11831 ] 11832 }, 11833 "COMPUTE_DISPATCH_TUNNEL": { 11834 "fields": [ 11835 {"bits": [0, 9], "name": "OFF_DELAY"}, 11836 {"bits": [10, 10], "name": "IMMEDIATE"} 11837 ] 11838 }, 11839 "COMPUTE_MISC_RESERVED": { 11840 "fields": [ 11841 {"bits": [0, 1], "name": "SEND_SEID"}, 11842 {"bits": [2, 2], "name": "RESERVED2"}, 11843 {"bits": [3, 3], "name": "RESERVED3"}, 11844 {"bits": [4, 4], "name": "RESERVED4"}, 11845 {"bits": [5, 16], "name": "WAVE_ID_BASE"} 11846 ] 11847 }, 11848 "COMPUTE_NUM_THREAD_X": { 11849 "fields": [ 11850 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, 11851 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} 11852 ] 11853 }, 11854 "COMPUTE_PERFCOUNT_ENABLE": { 11855 "fields": [ 11856 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"} 11857 ] 11858 }, 11859 "COMPUTE_PGM_HI": { 11860 "fields": [ 11861 {"bits": [0, 7], "name": "DATA"} 11862 ] 11863 }, 11864 "COMPUTE_PGM_RSRC1": { 11865 "fields": [ 11866 {"bits": [0, 5], "name": "VGPRS"}, 11867 {"bits": [6, 9], "name": "SGPRS"}, 11868 {"bits": [10, 11], "name": "PRIORITY"}, 11869 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 11870 {"bits": [20, 20], "name": "PRIV"}, 11871 {"bits": [21, 21], "name": "DX10_CLAMP"}, 11872 {"bits": [23, 23], "name": "IEEE_MODE"}, 11873 {"bits": [24, 24], "name": "BULKY"}, 11874 {"bits": [26, 26], "name": "FP16_OVFL"}, 11875 {"bits": [29, 29], "name": "WGP_MODE"}, 11876 {"bits": [30, 30], "name": "MEM_ORDERED"}, 11877 {"bits": [31, 31], "name": "FWD_PROGRESS"} 11878 ] 11879 }, 11880 "COMPUTE_PGM_RSRC2": { 11881 "fields": [ 11882 {"bits": [0, 0], "name": "SCRATCH_EN"}, 11883 {"bits": [1, 5], "name": "USER_SGPR"}, 11884 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 11885 {"bits": [7, 7], "name": "TGID_X_EN"}, 11886 {"bits": [8, 8], "name": "TGID_Y_EN"}, 11887 {"bits": [9, 9], "name": "TGID_Z_EN"}, 11888 {"bits": [10, 10], "name": "TG_SIZE_EN"}, 11889 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, 11890 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, 11891 {"bits": [15, 23], "name": "LDS_SIZE"}, 11892 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 11893 ] 11894 }, 11895 "COMPUTE_PGM_RSRC3": { 11896 "fields": [ 11897 {"bits": [0, 3], "name": "SHARED_VGPR_CNT"} 11898 ] 11899 }, 11900 "COMPUTE_PIPELINESTAT_ENABLE": { 11901 "fields": [ 11902 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"} 11903 ] 11904 }, 11905 "COMPUTE_RELAUNCH": { 11906 "fields": [ 11907 {"bits": [0, 29], "name": "PAYLOAD"}, 11908 {"bits": [30, 30], "name": "IS_EVENT"}, 11909 {"bits": [31, 31], "name": "IS_STATE"} 11910 ] 11911 }, 11912 "COMPUTE_REQ_CTRL": { 11913 "fields": [ 11914 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"}, 11915 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"}, 11916 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"}, 11917 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"}, 11918 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"}, 11919 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"}, 11920 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"}, 11921 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}, 11922 {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"} 11923 ] 11924 }, 11925 "COMPUTE_RESOURCE_LIMITS": { 11926 "fields": [ 11927 {"bits": [0, 9], "name": "WAVES_PER_SH"}, 11928 {"bits": [12, 15], "name": "TG_PER_CU"}, 11929 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, 11930 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, 11931 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, 11932 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} 11933 ] 11934 }, 11935 "COMPUTE_THREAD_TRACE_ENABLE": { 11936 "fields": [ 11937 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"} 11938 ] 11939 }, 11940 "COMPUTE_TMPRING_SIZE": { 11941 "fields": [ 11942 {"bits": [0, 11], "name": "WAVES"}, 11943 {"bits": [12, 24], "name": "WAVESIZE"} 11944 ] 11945 }, 11946 "COMPUTE_VMID": { 11947 "fields": [ 11948 {"bits": [0, 3], "name": "DATA"} 11949 ] 11950 }, 11951 "COMPUTE_WAVE_RESTORE_ADDR_HI": { 11952 "fields": [ 11953 {"bits": [0, 15], "name": "ADDR"} 11954 ] 11955 }, 11956 "CPF_LATENCY_STATS_SELECT": { 11957 "fields": [ 11958 {"bits": [0, 3], "name": "INDEX"}, 11959 {"bits": [30, 30], "name": "CLEAR"}, 11960 {"bits": [31, 31], "name": "ENABLE"} 11961 ] 11962 }, 11963 "CPF_TC_PERF_COUNTER_WINDOW_SELECT": { 11964 "fields": [ 11965 {"bits": [0, 2], "name": "INDEX"}, 11966 {"bits": [30, 30], "name": "ALWAYS"}, 11967 {"bits": [31, 31], "name": "ENABLE"} 11968 ] 11969 }, 11970 "CPG_LATENCY_STATS_SELECT": { 11971 "fields": [ 11972 {"bits": [0, 4], "name": "INDEX"}, 11973 {"bits": [30, 30], "name": "CLEAR"}, 11974 {"bits": [31, 31], "name": "ENABLE"} 11975 ] 11976 }, 11977 "CPG_PERFCOUNTER0_SELECT1": { 11978 "fields": [ 11979 {"bits": [0, 9], "name": "PERF_SEL2"}, 11980 {"bits": [10, 19], "name": "PERF_SEL3"}, 11981 {"bits": [24, 27], "name": "CNTR_MODE3"}, 11982 {"bits": [28, 31], "name": "CNTR_MODE2"} 11983 ] 11984 }, 11985 "CPG_PERFCOUNTER1_SELECT": { 11986 "fields": [ 11987 {"bits": [0, 9], "name": "PERF_SEL"}, 11988 {"bits": [10, 19], "name": "PERF_SEL1"}, 11989 {"bits": [20, 23], "name": "SPM_MODE"}, 11990 {"bits": [24, 27], "name": "CNTR_MODE1"}, 11991 {"bits": [28, 31], "name": "CNTR_MODE0"} 11992 ] 11993 }, 11994 "CPG_TC_PERF_COUNTER_WINDOW_SELECT": { 11995 "fields": [ 11996 {"bits": [0, 4], "name": "INDEX"}, 11997 {"bits": [30, 30], "name": "ALWAYS"}, 11998 {"bits": [31, 31], "name": "ENABLE"} 11999 ] 12000 }, 12001 "CP_APPEND_ADDR_HI": { 12002 "fields": [ 12003 {"bits": [0, 15], "name": "MEM_ADDR_HI"}, 12004 {"bits": [16, 16], "name": "CS_PS_SEL"}, 12005 {"bits": [25, 26], "name": "CACHE_POLICY"}, 12006 {"bits": [29, 31], "name": "COMMAND"} 12007 ] 12008 }, 12009 "CP_APPEND_ADDR_LO": { 12010 "fields": [ 12011 {"bits": [2, 31], "name": "MEM_ADDR_LO"} 12012 ] 12013 }, 12014 "CP_CE_IB1_BASE_HI": { 12015 "fields": [ 12016 {"bits": [0, 15], "name": "IB1_BASE_HI"} 12017 ] 12018 }, 12019 "CP_CE_IB1_BASE_LO": { 12020 "fields": [ 12021 {"bits": [2, 31], "name": "IB1_BASE_LO"} 12022 ] 12023 }, 12024 "CP_CE_IB1_BUFSZ": { 12025 "fields": [ 12026 {"bits": [0, 19], "name": "IB1_BUFSZ"} 12027 ] 12028 }, 12029 "CP_CE_IB1_CMD_BUFSZ": { 12030 "fields": [ 12031 {"bits": [0, 19], "name": "IB1_CMD_REQSZ"} 12032 ] 12033 }, 12034 "CP_CE_IB2_BASE_HI": { 12035 "fields": [ 12036 {"bits": [0, 15], "name": "IB2_BASE_HI"} 12037 ] 12038 }, 12039 "CP_CE_IB2_BASE_LO": { 12040 "fields": [ 12041 {"bits": [2, 31], "name": "IB2_BASE_LO"} 12042 ] 12043 }, 12044 "CP_CE_IB2_BUFSZ": { 12045 "fields": [ 12046 {"bits": [0, 19], "name": "IB2_BUFSZ"} 12047 ] 12048 }, 12049 "CP_CE_IB2_CMD_BUFSZ": { 12050 "fields": [ 12051 {"bits": [0, 19], "name": "IB2_CMD_REQSZ"} 12052 ] 12053 }, 12054 "CP_CE_INIT_BASE_HI": { 12055 "fields": [ 12056 {"bits": [0, 15], "name": "INIT_BASE_HI"} 12057 ] 12058 }, 12059 "CP_CE_INIT_BASE_LO": { 12060 "fields": [ 12061 {"bits": [5, 31], "name": "INIT_BASE_LO"} 12062 ] 12063 }, 12064 "CP_CE_INIT_BUFSZ": { 12065 "fields": [ 12066 {"bits": [0, 11], "name": "INIT_BUFSZ"} 12067 ] 12068 }, 12069 "CP_CE_INIT_CMD_BUFSZ": { 12070 "fields": [ 12071 {"bits": [0, 11], "name": "INIT_CMD_REQSZ"} 12072 ] 12073 }, 12074 "CP_COHER_BASE_HI": { 12075 "fields": [ 12076 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"} 12077 ] 12078 }, 12079 "CP_COHER_CNTL": { 12080 "fields": [ 12081 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"}, 12082 {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"}, 12083 {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"}, 12084 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, 12085 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, 12086 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, 12087 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, 12088 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, 12089 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, 12090 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, 12091 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, 12092 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"}, 12093 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"} 12094 ] 12095 }, 12096 "CP_COHER_SIZE_HI": { 12097 "fields": [ 12098 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"} 12099 ] 12100 }, 12101 "CP_COHER_START_DELAY": { 12102 "fields": [ 12103 {"bits": [0, 5], "name": "START_DELAY_COUNT"} 12104 ] 12105 }, 12106 "CP_COHER_STATUS": { 12107 "fields": [ 12108 {"bits": [24, 25], "name": "MEID"}, 12109 {"bits": [31, 31], "name": "STATUS"} 12110 ] 12111 }, 12112 "CP_CPC_BUSY_STAT": { 12113 "fields": [ 12114 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"}, 12115 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"}, 12116 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"}, 12117 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"}, 12118 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"}, 12119 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"}, 12120 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"}, 12121 {"bits": [7, 7], "name": "MEC1_TC_BUSY"}, 12122 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"}, 12123 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"}, 12124 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"}, 12125 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"}, 12126 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"}, 12127 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"}, 12128 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"}, 12129 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"}, 12130 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"}, 12131 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"}, 12132 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"}, 12133 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"}, 12134 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"}, 12135 {"bits": [23, 23], "name": "MEC2_TC_BUSY"}, 12136 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"}, 12137 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"}, 12138 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"}, 12139 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"}, 12140 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"}, 12141 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"} 12142 ] 12143 }, 12144 "CP_CPC_BUSY_STAT2": { 12145 "fields": [ 12146 {"bits": [0, 0], "name": "MES_LOAD_BUSY"}, 12147 {"bits": [2, 2], "name": "MES_MUTEX_BUSY"}, 12148 {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"}, 12149 {"bits": [7, 7], "name": "MES_TC_BUSY"}, 12150 {"bits": [8, 8], "name": "MES_DMA_BUSY"}, 12151 {"bits": [10, 10], "name": "MES_PIPE0_BUSY"}, 12152 {"bits": [11, 11], "name": "MES_PIPE1_BUSY"}, 12153 {"bits": [12, 12], "name": "MES_PIPE2_BUSY"}, 12154 {"bits": [13, 13], "name": "MES_PIPE3_BUSY"} 12155 ] 12156 }, 12157 "CP_CPC_GRBM_FREE_COUNT": { 12158 "fields": [ 12159 {"bits": [0, 5], "name": "FREE_COUNT"} 12160 ] 12161 }, 12162 "CP_CPC_HALT_HYST_COUNT": { 12163 "fields": [ 12164 {"bits": [0, 3], "name": "COUNT"} 12165 ] 12166 }, 12167 "CP_CPC_SCRATCH_INDEX": { 12168 "fields": [ 12169 {"bits": [0, 8], "name": "SCRATCH_INDEX"}, 12170 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"} 12171 ] 12172 }, 12173 "CP_CPC_STALLED_STAT1": { 12174 "fields": [ 12175 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"}, 12176 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"}, 12177 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"}, 12178 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"}, 12179 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"}, 12180 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"}, 12181 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"}, 12182 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"}, 12183 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"}, 12184 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"}, 12185 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"}, 12186 {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"}, 12187 {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"}, 12188 {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"}, 12189 {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"} 12190 ] 12191 }, 12192 "CP_CPC_STATUS": { 12193 "fields": [ 12194 {"bits": [0, 0], "name": "MEC1_BUSY"}, 12195 {"bits": [1, 1], "name": "MEC2_BUSY"}, 12196 {"bits": [2, 2], "name": "DC0_BUSY"}, 12197 {"bits": [3, 3], "name": "DC1_BUSY"}, 12198 {"bits": [4, 4], "name": "RCIU1_BUSY"}, 12199 {"bits": [5, 5], "name": "RCIU2_BUSY"}, 12200 {"bits": [6, 6], "name": "ROQ1_BUSY"}, 12201 {"bits": [7, 7], "name": "ROQ2_BUSY"}, 12202 {"bits": [10, 10], "name": "TCIU_BUSY"}, 12203 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"}, 12204 {"bits": [12, 12], "name": "QU_BUSY"}, 12205 {"bits": [13, 13], "name": "UTCL2IU_BUSY"}, 12206 {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"}, 12207 {"bits": [15, 15], "name": "GCRIU_BUSY"}, 12208 {"bits": [16, 16], "name": "MES_BUSY"}, 12209 {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"}, 12210 {"bits": [18, 18], "name": "RCIU3_BUSY"}, 12211 {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"}, 12212 {"bits": [29, 29], "name": "CPG_CPC_BUSY"}, 12213 {"bits": [30, 30], "name": "CPF_CPC_BUSY"}, 12214 {"bits": [31, 31], "name": "CPC_BUSY"} 12215 ] 12216 }, 12217 "CP_CPF_BUSY_STAT": { 12218 "fields": [ 12219 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, 12220 {"bits": [1, 1], "name": "CSF_RING_BUSY"}, 12221 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"}, 12222 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"}, 12223 {"bits": [4, 4], "name": "CSF_STATE_BUSY"}, 12224 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"}, 12225 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"}, 12226 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"}, 12227 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"}, 12228 {"bits": [9, 9], "name": "CSF_DATA_BUSY"}, 12229 {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"}, 12230 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"}, 12231 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"}, 12232 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"}, 12233 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"}, 12234 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"}, 12235 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"}, 12236 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"}, 12237 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"}, 12238 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"}, 12239 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"}, 12240 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"}, 12241 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"}, 12242 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"}, 12243 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"}, 12244 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"}, 12245 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"}, 12246 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"}, 12247 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"}, 12248 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"}, 12249 {"bits": [30, 30], "name": "HQD_PQ_BUSY"}, 12250 {"bits": [31, 31], "name": "HQD_IB_BUSY"} 12251 ] 12252 }, 12253 "CP_CPF_BUSY_STAT2": { 12254 "fields": [ 12255 {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"}, 12256 {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"}, 12257 {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"}, 12258 {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"}, 12259 {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"}, 12260 {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"}, 12261 {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"}, 12262 {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"}, 12263 {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"} 12264 ] 12265 }, 12266 "CP_CPF_GRBM_FREE_COUNT": { 12267 "fields": [ 12268 {"bits": [0, 2], "name": "FREE_COUNT"} 12269 ] 12270 }, 12271 "CP_CPF_STALLED_STAT1": { 12272 "fields": [ 12273 {"bits": [0, 0], "name": "RING_FETCHING_DATA"}, 12274 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"}, 12275 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"}, 12276 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"}, 12277 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"}, 12278 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"}, 12279 {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"}, 12280 {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"}, 12281 {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"}, 12282 {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"}, 12283 {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"}, 12284 {"bits": [12, 12], "name": "DATA_FETCHING_DATA"}, 12285 {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"} 12286 ] 12287 }, 12288 "CP_CPF_STATUS": { 12289 "fields": [ 12290 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"}, 12291 {"bits": [1, 1], "name": "CSF_BUSY"}, 12292 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"}, 12293 {"bits": [5, 5], "name": "ROQ_RING_BUSY"}, 12294 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"}, 12295 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"}, 12296 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"}, 12297 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"}, 12298 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"}, 12299 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"}, 12300 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"}, 12301 {"bits": [13, 13], "name": "INTERRUPT_BUSY"}, 12302 {"bits": [14, 14], "name": "TCIU_BUSY"}, 12303 {"bits": [15, 15], "name": "HQD_BUSY"}, 12304 {"bits": [16, 16], "name": "PRT_BUSY"}, 12305 {"bits": [17, 17], "name": "UTCL2IU_BUSY"}, 12306 {"bits": [18, 18], "name": "RCIU_BUSY"}, 12307 {"bits": [19, 19], "name": "RCIU_GFX_BUSY"}, 12308 {"bits": [20, 20], "name": "RCIU_CMP_BUSY"}, 12309 {"bits": [21, 21], "name": "ROQ_DATA_BUSY"}, 12310 {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"}, 12311 {"bits": [23, 23], "name": "GCRIU_BUSY"}, 12312 {"bits": [24, 24], "name": "MES_HQD_BUSY"}, 12313 {"bits": [26, 26], "name": "CPF_GFX_BUSY"}, 12314 {"bits": [27, 27], "name": "CPF_CMP_BUSY"}, 12315 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"}, 12316 {"bits": [30, 30], "name": "CPC_CPF_BUSY"}, 12317 {"bits": [31, 31], "name": "CPF_BUSY"} 12318 ] 12319 }, 12320 "CP_DB_BASE_HI": { 12321 "fields": [ 12322 {"bits": [0, 15], "name": "DB_BASE_HI"} 12323 ] 12324 }, 12325 "CP_DB_BASE_LO": { 12326 "fields": [ 12327 {"bits": [2, 31], "name": "DB_BASE_LO"} 12328 ] 12329 }, 12330 "CP_DB_BUFSZ": { 12331 "fields": [ 12332 {"bits": [0, 19], "name": "DB_BUFSZ"} 12333 ] 12334 }, 12335 "CP_DB_CMD_BUFSZ": { 12336 "fields": [ 12337 {"bits": [0, 19], "name": "DB_CMD_REQSZ"} 12338 ] 12339 }, 12340 "CP_DMA_CNTL": { 12341 "fields": [ 12342 {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"}, 12343 {"bits": [1, 1], "name": "WATCH_CONTROL"}, 12344 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, 12345 {"bits": [16, 24], "name": "BUFFER_DEPTH"}, 12346 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, 12347 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, 12348 {"bits": [30, 31], "name": "PIO_COUNT"} 12349 ] 12350 }, 12351 "CP_DMA_ME_CMD_ADDR_HI": { 12352 "fields": [ 12353 {"bits": [0, 15], "name": "ADDR_HI"}, 12354 {"bits": [16, 31], "name": "RSVD"} 12355 ] 12356 }, 12357 "CP_DMA_ME_CMD_ADDR_LO": { 12358 "fields": [ 12359 {"bits": [0, 1], "name": "RSVD"}, 12360 {"bits": [2, 31], "name": "ADDR_LO"} 12361 ] 12362 }, 12363 "CP_DMA_ME_COMMAND": { 12364 "fields": [ 12365 {"bits": [0, 25], "name": "BYTE_COUNT"}, 12366 {"bits": [26, 26], "name": "SAS"}, 12367 {"bits": [27, 27], "name": "DAS"}, 12368 {"bits": [28, 28], "name": "SAIC"}, 12369 {"bits": [29, 29], "name": "DAIC"}, 12370 {"bits": [30, 30], "name": "RAW_WAIT"}, 12371 {"bits": [31, 31], "name": "DIS_WC"} 12372 ] 12373 }, 12374 "CP_DMA_ME_DST_ADDR_HI": { 12375 "fields": [ 12376 {"bits": [0, 15], "name": "DST_ADDR_HI"} 12377 ] 12378 }, 12379 "CP_DMA_ME_SRC_ADDR_HI": { 12380 "fields": [ 12381 {"bits": [0, 15], "name": "SRC_ADDR_HI"} 12382 ] 12383 }, 12384 "CP_DMA_PFP_CONTROL": { 12385 "fields": [ 12386 {"bits": [10, 10], "name": "MEMLOG_CLEAR"}, 12387 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"}, 12388 {"bits": [15, 15], "name": "SRC_VOLATLE"}, 12389 {"bits": [20, 21], "name": "DST_SELECT"}, 12390 {"bits": [25, 26], "name": "DST_CACHE_POLICY"}, 12391 {"bits": [27, 27], "name": "DST_VOLATLE"}, 12392 {"bits": [29, 30], "name": "SRC_SELECT"} 12393 ] 12394 }, 12395 "CP_DMA_READ_TAGS": { 12396 "fields": [ 12397 {"bits": [0, 25], "name": "DMA_READ_TAG"}, 12398 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} 12399 ] 12400 }, 12401 "CP_DRAW_WINDOW_CNTL": { 12402 "fields": [ 12403 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"}, 12404 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"}, 12405 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"}, 12406 {"bits": [8, 8], "name": "MODE"} 12407 ] 12408 }, 12409 "CP_DRAW_WINDOW_LO": { 12410 "fields": [ 12411 {"bits": [0, 15], "name": "MIN"}, 12412 {"bits": [16, 31], "name": "MAX"} 12413 ] 12414 }, 12415 "CP_EOP_DONE_ADDR_HI": { 12416 "fields": [ 12417 {"bits": [0, 15], "name": "ADDR_HI"} 12418 ] 12419 }, 12420 "CP_EOP_DONE_ADDR_LO": { 12421 "fields": [ 12422 {"bits": [2, 31], "name": "ADDR_LO"} 12423 ] 12424 }, 12425 "CP_EOP_DONE_DATA_CNTL": { 12426 "fields": [ 12427 {"bits": [16, 17], "name": "DST_SEL"}, 12428 {"bits": [24, 26], "name": "INT_SEL"}, 12429 {"bits": [29, 31], "name": "DATA_SEL"} 12430 ] 12431 }, 12432 "CP_EOP_DONE_DOORBELL": { 12433 "fields": [ 12434 {"bits": [2, 27], "name": "DOORBELL_OFFSET"} 12435 ] 12436 }, 12437 "CP_EOP_DONE_EVENT_CNTL": { 12438 "fields": [ 12439 {"bits": [12, 23], "name": "GCR_CNTL"}, 12440 {"bits": [25, 26], "name": "CACHE_POLICY"}, 12441 {"bits": [27, 27], "name": "EOP_VOLATILE"}, 12442 {"bits": [28, 28], "name": "EXECUTE"} 12443 ] 12444 }, 12445 "CP_IB1_OFFSET": { 12446 "fields": [ 12447 {"bits": [0, 19], "name": "IB1_OFFSET"} 12448 ] 12449 }, 12450 "CP_IB1_PREAMBLE_BEGIN": { 12451 "fields": [ 12452 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} 12453 ] 12454 }, 12455 "CP_IB1_PREAMBLE_END": { 12456 "fields": [ 12457 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} 12458 ] 12459 }, 12460 "CP_IB2_OFFSET": { 12461 "fields": [ 12462 {"bits": [0, 19], "name": "IB2_OFFSET"} 12463 ] 12464 }, 12465 "CP_IB2_PREAMBLE_BEGIN": { 12466 "fields": [ 12467 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} 12468 ] 12469 }, 12470 "CP_IB2_PREAMBLE_END": { 12471 "fields": [ 12472 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} 12473 ] 12474 }, 12475 "CP_INDEX_TYPE": { 12476 "fields": [ 12477 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} 12478 ] 12479 }, 12480 "CP_ME_COHER_CNTL": { 12481 "fields": [ 12482 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, 12483 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, 12484 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, 12485 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, 12486 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, 12487 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, 12488 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, 12489 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, 12490 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, 12491 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, 12492 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, 12493 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, 12494 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"} 12495 ] 12496 }, 12497 "CP_ME_COHER_STATUS": { 12498 "fields": [ 12499 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, 12500 {"bits": [31, 31], "name": "STATUS"} 12501 ] 12502 }, 12503 "CP_ME_MC_RADDR_HI": { 12504 "fields": [ 12505 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"}, 12506 {"bits": [22, 23], "name": "CACHE_POLICY"} 12507 ] 12508 }, 12509 "CP_ME_MC_RADDR_LO": { 12510 "fields": [ 12511 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} 12512 ] 12513 }, 12514 "CP_ME_MC_WADDR_HI": { 12515 "fields": [ 12516 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"}, 12517 {"bits": [22, 23], "name": "CACHE_POLICY"} 12518 ] 12519 }, 12520 "CP_ME_MC_WADDR_LO": { 12521 "fields": [ 12522 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} 12523 ] 12524 }, 12525 "CP_PERFMON_CNTL": { 12526 "fields": [ 12527 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, 12528 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, 12529 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, 12530 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} 12531 ] 12532 }, 12533 "CP_PERFMON_CNTX_CNTL": { 12534 "fields": [ 12535 {"bits": [31, 31], "name": "PERFMON_ENABLE"} 12536 ] 12537 }, 12538 "CP_PFP_COMPLETION_STATUS": { 12539 "fields": [ 12540 {"bits": [0, 1], "name": "STATUS"} 12541 ] 12542 }, 12543 "CP_PFP_IB_CONTROL": { 12544 "fields": [ 12545 {"bits": [0, 7], "name": "IB_EN"} 12546 ] 12547 }, 12548 "CP_PFP_LOAD_CONTROL": { 12549 "fields": [ 12550 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, 12551 {"bits": [1, 1], "name": "CNTX_REG_EN"}, 12552 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, 12553 {"bits": [24, 24], "name": "SH_CS_REG_EN"} 12554 ] 12555 }, 12556 "CP_PIPEID": { 12557 "fields": [ 12558 {"bits": [0, 1], "name": "PIPE_ID"} 12559 ] 12560 }, 12561 "CP_PIPE_STATS_ADDR_HI": { 12562 "fields": [ 12563 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"} 12564 ] 12565 }, 12566 "CP_PIPE_STATS_ADDR_LO": { 12567 "fields": [ 12568 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} 12569 ] 12570 }, 12571 "CP_PIPE_STATS_CONTROL": { 12572 "fields": [ 12573 {"bits": [25, 26], "name": "CACHE_POLICY"} 12574 ] 12575 }, 12576 "CP_PRED_NOT_VISIBLE": { 12577 "fields": [ 12578 {"bits": [0, 0], "name": "NOT_VISIBLE"} 12579 ] 12580 }, 12581 "CP_RB_OFFSET": { 12582 "fields": [ 12583 {"bits": [0, 19], "name": "RB_OFFSET"} 12584 ] 12585 }, 12586 "CP_SAMPLE_STATUS": { 12587 "fields": [ 12588 {"bits": [0, 0], "name": "Z_PASS_ACITVE"}, 12589 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"}, 12590 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"}, 12591 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"}, 12592 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"}, 12593 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"}, 12594 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"}, 12595 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"} 12596 ] 12597 }, 12598 "CP_SCRATCH_INDEX": { 12599 "fields": [ 12600 {"bits": [0, 7], "name": "SCRATCH_INDEX"}, 12601 {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"} 12602 ] 12603 }, 12604 "CP_SIG_SEM_ADDR_HI": { 12605 "fields": [ 12606 {"bits": [0, 15], "name": "SEM_ADDR_HI"}, 12607 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, 12608 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, 12609 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, 12610 {"bits": [29, 31], "name": "SEM_SELECT"} 12611 ] 12612 }, 12613 "CP_SIG_SEM_ADDR_LO": { 12614 "fields": [ 12615 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, 12616 {"bits": [3, 31], "name": "SEM_ADDR_LO"} 12617 ] 12618 }, 12619 "CP_STREAM_OUT_ADDR_HI": { 12620 "fields": [ 12621 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"} 12622 ] 12623 }, 12624 "CP_STREAM_OUT_ADDR_LO": { 12625 "fields": [ 12626 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} 12627 ] 12628 }, 12629 "CP_STRMOUT_CNTL": { 12630 "fields": [ 12631 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} 12632 ] 12633 }, 12634 "CP_ST_BASE_HI": { 12635 "fields": [ 12636 {"bits": [0, 15], "name": "ST_BASE_HI"} 12637 ] 12638 }, 12639 "CP_ST_BASE_LO": { 12640 "fields": [ 12641 {"bits": [2, 31], "name": "ST_BASE_LO"} 12642 ] 12643 }, 12644 "CP_ST_BUFSZ": { 12645 "fields": [ 12646 {"bits": [0, 19], "name": "ST_BUFSZ"} 12647 ] 12648 }, 12649 "CP_ST_CMD_BUFSZ": { 12650 "fields": [ 12651 {"bits": [0, 19], "name": "ST_CMD_REQSZ"} 12652 ] 12653 }, 12654 "CP_VMID": { 12655 "fields": [ 12656 {"bits": [0, 3], "name": "VMID"} 12657 ] 12658 }, 12659 "CS_COPY_STATE": { 12660 "fields": [ 12661 {"bits": [0, 2], "name": "SRC_STATE_ID"} 12662 ] 12663 }, 12664 "DB_ALPHA_TO_MASK": { 12665 "fields": [ 12666 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, 12667 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, 12668 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, 12669 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, 12670 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, 12671 {"bits": [16, 16], "name": "OFFSET_ROUND"} 12672 ] 12673 }, 12674 "DB_COUNT_CONTROL": { 12675 "fields": [ 12676 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, 12677 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, 12678 {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"}, 12679 {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"}, 12680 {"bits": [4, 6], "name": "SAMPLE_RATE"}, 12681 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, 12682 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, 12683 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, 12684 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, 12685 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, 12686 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} 12687 ] 12688 }, 12689 "DB_DEPTH_CONTROL": { 12690 "fields": [ 12691 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, 12692 {"bits": [1, 1], "name": "Z_ENABLE"}, 12693 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, 12694 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, 12695 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, 12696 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, 12697 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, 12698 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, 12699 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, 12700 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} 12701 ] 12702 }, 12703 "DB_DEPTH_SIZE_XY": { 12704 "fields": [ 12705 {"bits": [0, 13], "name": "X_MAX"}, 12706 {"bits": [16, 29], "name": "Y_MAX"} 12707 ] 12708 }, 12709 "DB_DEPTH_VIEW": { 12710 "fields": [ 12711 {"bits": [0, 10], "name": "SLICE_START"}, 12712 {"bits": [11, 12], "name": "SLICE_START_HI"}, 12713 {"bits": [13, 23], "name": "SLICE_MAX"}, 12714 {"bits": [24, 24], "name": "Z_READ_ONLY"}, 12715 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}, 12716 {"bits": [26, 29], "name": "MIPID"}, 12717 {"bits": [30, 31], "name": "SLICE_MAX_HI"} 12718 ] 12719 }, 12720 "DB_DFSM_CONTROL": { 12721 "fields": [ 12722 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"}, 12723 {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"}, 12724 {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"} 12725 ] 12726 }, 12727 "DB_EQAA": { 12728 "fields": [ 12729 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, 12730 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, 12731 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, 12732 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, 12733 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, 12734 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, 12735 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, 12736 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, 12737 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, 12738 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, 12739 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, 12740 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} 12741 ] 12742 }, 12743 "DB_HTILE_SURFACE": { 12744 "fields": [ 12745 {"bits": [0, 0], "name": "RESERVED_FIELD_1"}, 12746 {"bits": [1, 1], "name": "FULL_CACHE"}, 12747 {"bits": [2, 2], "name": "RESERVED_FIELD_2"}, 12748 {"bits": [3, 3], "name": "RESERVED_FIELD_3"}, 12749 {"bits": [4, 9], "name": "RESERVED_FIELD_4"}, 12750 {"bits": [10, 15], "name": "RESERVED_FIELD_5"}, 12751 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"}, 12752 {"bits": [17, 17], "name": "RESERVED_FIELD_6"}, 12753 {"bits": [18, 18], "name": "PIPE_ALIGNED"} 12754 ] 12755 }, 12756 "DB_OCCLUSION_COUNT0_HI": { 12757 "fields": [ 12758 {"bits": [0, 30], "name": "COUNT_HI"} 12759 ] 12760 }, 12761 "DB_PRELOAD_CONTROL": { 12762 "fields": [ 12763 {"bits": [0, 7], "name": "START_X"}, 12764 {"bits": [8, 15], "name": "START_Y"}, 12765 {"bits": [16, 23], "name": "MAX_X"}, 12766 {"bits": [24, 31], "name": "MAX_Y"} 12767 ] 12768 }, 12769 "DB_RENDER_CONTROL": { 12770 "fields": [ 12771 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, 12772 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, 12773 {"bits": [2, 2], "name": "DEPTH_COPY"}, 12774 {"bits": [3, 3], "name": "STENCIL_COPY"}, 12775 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, 12776 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, 12777 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, 12778 {"bits": [7, 7], "name": "COPY_CENTROID"}, 12779 {"bits": [8, 11], "name": "COPY_SAMPLE"}, 12780 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"} 12781 ] 12782 }, 12783 "DB_RENDER_OVERRIDE": { 12784 "fields": [ 12785 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, 12786 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, 12787 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, 12788 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, 12789 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, 12790 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, 12791 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, 12792 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, 12793 {"bits": [11, 11], "name": "FORCE_Z_READ"}, 12794 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, 12795 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, 12796 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, 12797 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, 12798 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, 12799 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, 12800 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, 12801 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, 12802 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, 12803 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, 12804 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, 12805 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, 12806 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, 12807 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} 12808 ] 12809 }, 12810 "DB_RENDER_OVERRIDE2": { 12811 "fields": [ 12812 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, 12813 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, 12814 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, 12815 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, 12816 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, 12817 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, 12818 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, 12819 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, 12820 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, 12821 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, 12822 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, 12823 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, 12824 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, 12825 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, 12826 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}, 12827 {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"} 12828 ] 12829 }, 12830 "DB_RESERVED_REG_1": { 12831 "fields": [ 12832 {"bits": [0, 10], "name": "FIELD_1"}, 12833 {"bits": [11, 21], "name": "FIELD_2"} 12834 ] 12835 }, 12836 "DB_RESERVED_REG_2": { 12837 "fields": [ 12838 {"bits": [0, 3], "name": "FIELD_1"}, 12839 {"bits": [4, 7], "name": "FIELD_2"}, 12840 {"bits": [8, 12], "name": "FIELD_3"}, 12841 {"bits": [13, 14], "name": "FIELD_4"}, 12842 {"bits": [15, 16], "name": "FIELD_5"}, 12843 {"bits": [17, 18], "name": "FIELD_6"}, 12844 {"bits": [19, 20], "name": "FIELD_7"}, 12845 {"bits": [28, 31], "name": "RESOURCE_LEVEL"} 12846 ] 12847 }, 12848 "DB_RESERVED_REG_3": { 12849 "fields": [ 12850 {"bits": [0, 21], "name": "FIELD_1"} 12851 ] 12852 }, 12853 "DB_RMI_L2_CACHE_CONTROL": { 12854 "fields": [ 12855 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"}, 12856 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"}, 12857 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"}, 12858 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"}, 12859 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"}, 12860 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"}, 12861 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"}, 12862 {"bits": [24, 24], "name": "Z_BIG_PAGE"}, 12863 {"bits": [25, 25], "name": "S_BIG_PAGE"} 12864 ] 12865 }, 12866 "DB_SHADER_CONTROL": { 12867 "fields": [ 12868 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, 12869 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, 12870 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, 12871 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, 12872 {"bits": [6, 6], "name": "KILL_ENABLE"}, 12873 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, 12874 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, 12875 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, 12876 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, 12877 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, 12878 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, 12879 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, 12880 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}, 12881 {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"}, 12882 {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"}, 12883 {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"}, 12884 {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"} 12885 ] 12886 }, 12887 "DB_SRESULTS_COMPARE_STATE0": { 12888 "fields": [ 12889 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, 12890 {"bits": [4, 11], "name": "COMPAREVALUE0"}, 12891 {"bits": [12, 19], "name": "COMPAREMASK0"}, 12892 {"bits": [24, 24], "name": "ENABLE0"} 12893 ] 12894 }, 12895 "DB_SRESULTS_COMPARE_STATE1": { 12896 "fields": [ 12897 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, 12898 {"bits": [4, 11], "name": "COMPAREVALUE1"}, 12899 {"bits": [12, 19], "name": "COMPAREMASK1"}, 12900 {"bits": [24, 24], "name": "ENABLE1"} 12901 ] 12902 }, 12903 "DB_STENCILREFMASK": { 12904 "fields": [ 12905 {"bits": [0, 7], "name": "STENCILTESTVAL"}, 12906 {"bits": [8, 15], "name": "STENCILMASK"}, 12907 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, 12908 {"bits": [24, 31], "name": "STENCILOPVAL"} 12909 ] 12910 }, 12911 "DB_STENCILREFMASK_BF": { 12912 "fields": [ 12913 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, 12914 {"bits": [8, 15], "name": "STENCILMASK_BF"}, 12915 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, 12916 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} 12917 ] 12918 }, 12919 "DB_STENCIL_CLEAR": { 12920 "fields": [ 12921 {"bits": [0, 7], "name": "CLEAR"} 12922 ] 12923 }, 12924 "DB_STENCIL_CONTROL": { 12925 "fields": [ 12926 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, 12927 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, 12928 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, 12929 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, 12930 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, 12931 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} 12932 ] 12933 }, 12934 "DB_STENCIL_INFO": { 12935 "fields": [ 12936 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, 12937 {"bits": [4, 8], "name": "SW_MODE"}, 12938 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, 12939 {"bits": [11, 11], "name": "ITERATE_FLUSH"}, 12940 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, 12941 {"bits": [13, 15], "name": "RESERVED_FIELD_1"}, 12942 {"bits": [20, 20], "name": "ITERATE_256"}, 12943 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 12944 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"} 12945 ] 12946 }, 12947 "DB_Z_INFO": { 12948 "fields": [ 12949 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, 12950 {"bits": [2, 3], "name": "NUM_SAMPLES"}, 12951 {"bits": [4, 8], "name": "SW_MODE"}, 12952 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, 12953 {"bits": [11, 11], "name": "ITERATE_FLUSH"}, 12954 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, 12955 {"bits": [13, 15], "name": "RESERVED_FIELD_1"}, 12956 {"bits": [16, 19], "name": "MAXMIP"}, 12957 {"bits": [20, 20], "name": "ITERATE_256"}, 12958 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"}, 12959 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 12960 {"bits": [28, 28], "name": "READ_SIZE"}, 12961 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, 12962 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} 12963 ] 12964 }, 12965 "DB_Z_READ_BASE_HI": { 12966 "fields": [ 12967 {"bits": [0, 7], "name": "BASE_HI"} 12968 ] 12969 }, 12970 "GB_ADDR_CONFIG": { 12971 "fields": [ 12972 {"bits": [0, 2], "name": "NUM_PIPES"}, 12973 {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"}, 12974 {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"}, 12975 {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"}, 12976 {"bits": [26, 27], "name": "NUM_RB_PER_SE"} 12977 ] 12978 }, 12979 "GB_MACROTILE_MODE0": { 12980 "fields": [ 12981 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, 12982 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, 12983 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, 12984 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} 12985 ] 12986 }, 12987 "GB_TILE_MODE0": { 12988 "fields": [ 12989 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 12990 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 12991 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 12992 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, 12993 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} 12994 ] 12995 }, 12996 "GCEA_PERFCOUNTER2_MODE": { 12997 "fields": [ 12998 {"bits": [0, 1], "name": "COMPARE_MODE0"}, 12999 {"bits": [2, 3], "name": "COMPARE_MODE1"}, 13000 {"bits": [4, 5], "name": "COMPARE_MODE2"}, 13001 {"bits": [6, 7], "name": "COMPARE_MODE3"}, 13002 {"bits": [8, 11], "name": "COMPARE_VALUE0"}, 13003 {"bits": [12, 15], "name": "COMPARE_VALUE1"}, 13004 {"bits": [16, 19], "name": "COMPARE_VALUE2"}, 13005 {"bits": [20, 23], "name": "COMPARE_VALUE3"} 13006 ] 13007 }, 13008 "GCR_PERFCOUNTER1_SELECT": { 13009 "fields": [ 13010 {"bits": [0, 8], "name": "PERF_SEL"}, 13011 {"bits": [24, 27], "name": "PERF_MODE"}, 13012 {"bits": [28, 31], "name": "CNTL_MODE"} 13013 ] 13014 }, 13015 "GC_ATC_L2_PERFCOUNTER0_CFG": { 13016 "fields": [ 13017 {"bits": [0, 7], "name": "PERF_SEL"}, 13018 {"bits": [8, 15], "name": "PERF_SEL_END"}, 13019 {"bits": [24, 27], "name": "PERF_MODE"}, 13020 {"bits": [28, 28], "name": "ENABLE"}, 13021 {"bits": [29, 29], "name": "CLEAR"} 13022 ] 13023 }, 13024 "GC_ATC_L2_PERFCOUNTER_HI": { 13025 "fields": [ 13026 {"bits": [0, 15], "name": "COUNTER_HI"}, 13027 {"bits": [16, 31], "name": "COMPARE_VALUE"} 13028 ] 13029 }, 13030 "GC_ATC_L2_PERFCOUNTER_RSLT_CNTL": { 13031 "fields": [ 13032 {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"}, 13033 {"bits": [8, 15], "name": "START_TRIGGER"}, 13034 {"bits": [16, 23], "name": "STOP_TRIGGER"}, 13035 {"bits": [24, 24], "name": "ENABLE_ANY"}, 13036 {"bits": [25, 25], "name": "CLEAR_ALL"}, 13037 {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"} 13038 ] 13039 }, 13040 "GDS_ATOM_BASE": { 13041 "fields": [ 13042 {"bits": [0, 15], "name": "BASE"}, 13043 {"bits": [16, 31], "name": "UNUSED"} 13044 ] 13045 }, 13046 "GDS_ATOM_CNTL": { 13047 "fields": [ 13048 {"bits": [0, 5], "name": "AINC"}, 13049 {"bits": [6, 7], "name": "UNUSED1"}, 13050 {"bits": [8, 9], "name": "DMODE"}, 13051 {"bits": [10, 31], "name": "UNUSED2"} 13052 ] 13053 }, 13054 "GDS_ATOM_COMPLETE": { 13055 "fields": [ 13056 {"bits": [0, 0], "name": "COMPLETE"}, 13057 {"bits": [1, 31], "name": "UNUSED"} 13058 ] 13059 }, 13060 "GDS_ATOM_OFFSET0": { 13061 "fields": [ 13062 {"bits": [0, 7], "name": "OFFSET0"}, 13063 {"bits": [8, 31], "name": "UNUSED"} 13064 ] 13065 }, 13066 "GDS_ATOM_OFFSET1": { 13067 "fields": [ 13068 {"bits": [0, 7], "name": "OFFSET1"}, 13069 {"bits": [8, 31], "name": "UNUSED"} 13070 ] 13071 }, 13072 "GDS_ATOM_OP": { 13073 "fields": [ 13074 {"bits": [0, 7], "name": "OP"}, 13075 {"bits": [8, 31], "name": "UNUSED"} 13076 ] 13077 }, 13078 "GDS_ATOM_SIZE": { 13079 "fields": [ 13080 {"bits": [0, 15], "name": "SIZE"}, 13081 {"bits": [16, 31], "name": "UNUSED"} 13082 ] 13083 }, 13084 "GDS_GWS_RESOURCE": { 13085 "fields": [ 13086 {"bits": [0, 0], "name": "FLAG"}, 13087 {"bits": [1, 12], "name": "COUNTER"}, 13088 {"bits": [13, 13], "name": "TYPE"}, 13089 {"bits": [14, 14], "name": "DED"}, 13090 {"bits": [15, 15], "name": "RELEASE_ALL"}, 13091 {"bits": [16, 26], "name": "HEAD_QUEUE"}, 13092 {"bits": [27, 27], "name": "HEAD_VALID"}, 13093 {"bits": [28, 28], "name": "HEAD_FLAG"}, 13094 {"bits": [29, 29], "name": "HALTED"}, 13095 {"bits": [30, 31], "name": "UNUSED1"} 13096 ] 13097 }, 13098 "GDS_GWS_RESOURCE_CNT": { 13099 "fields": [ 13100 {"bits": [0, 15], "name": "RESOURCE_CNT"}, 13101 {"bits": [16, 31], "name": "UNUSED"} 13102 ] 13103 }, 13104 "GDS_GWS_RESOURCE_CNTL": { 13105 "fields": [ 13106 {"bits": [0, 5], "name": "INDEX"}, 13107 {"bits": [6, 31], "name": "UNUSED"} 13108 ] 13109 }, 13110 "GDS_OA_ADDRESS": { 13111 "fields": [ 13112 {"bits": [0, 15], "name": "DS_ADDRESS"}, 13113 {"bits": [16, 19], "name": "CRAWLER_TYPE"}, 13114 {"bits": [20, 23], "name": "CRAWLER"}, 13115 {"bits": [24, 29], "name": "UNUSED"}, 13116 {"bits": [30, 30], "name": "NO_ALLOC"}, 13117 {"bits": [31, 31], "name": "ENABLE"} 13118 ] 13119 }, 13120 "GDS_OA_CNTL": { 13121 "fields": [ 13122 {"bits": [0, 3], "name": "INDEX"}, 13123 {"bits": [4, 31], "name": "UNUSED"} 13124 ] 13125 }, 13126 "GDS_OA_INCDEC": { 13127 "fields": [ 13128 {"bits": [0, 30], "name": "VALUE"}, 13129 {"bits": [31, 31], "name": "INCDEC"} 13130 ] 13131 }, 13132 "GE_CNTL": { 13133 "fields": [ 13134 {"bits": [0, 8], "name": "PRIM_GRP_SIZE"}, 13135 {"bits": [9, 17], "name": "VERT_GRP_SIZE"}, 13136 {"bits": [18, 18], "name": "BREAK_WAVE_AT_EOI"}, 13137 {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"} 13138 ] 13139 }, 13140 "GE_MAX_OUTPUT_PER_SUBGROUP": { 13141 "fields": [ 13142 {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"} 13143 ] 13144 }, 13145 "GE_NGG_SUBGRP_CNTL": { 13146 "fields": [ 13147 {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"}, 13148 {"bits": [9, 17], "name": "THDS_PER_SUBGRP"} 13149 ] 13150 }, 13151 "GE_PC_ALLOC": { 13152 "fields": [ 13153 {"bits": [0, 0], "name": "OVERSUB_EN"}, 13154 {"bits": [1, 10], "name": "NUM_PC_LINES"} 13155 ] 13156 }, 13157 "GE_PERFCOUNTER0_SELECT": { 13158 "fields": [ 13159 {"bits": [0, 9], "name": "PERF_SEL0"}, 13160 {"bits": [10, 19], "name": "PERF_SEL1"}, 13161 {"bits": [20, 23], "name": "CNTR_MODE"}, 13162 {"bits": [24, 27], "name": "PERF_MODE0"}, 13163 {"bits": [28, 31], "name": "PERF_MODE1"} 13164 ] 13165 }, 13166 "GE_PERFCOUNTER0_SELECT1": { 13167 "fields": [ 13168 {"bits": [0, 9], "name": "PERF_SEL2"}, 13169 {"bits": [10, 19], "name": "PERF_SEL3"}, 13170 {"bits": [24, 27], "name": "PERF_MODE2"}, 13171 {"bits": [28, 31], "name": "PERF_MODE3"} 13172 ] 13173 }, 13174 "GE_PERFCOUNTER4_SELECT": { 13175 "fields": [ 13176 {"bits": [0, 9], "name": "PERF_SEL0"}, 13177 {"bits": [28, 31], "name": "PERF_MODE"} 13178 ] 13179 }, 13180 "GE_STEREO_CNTL": { 13181 "fields": [ 13182 {"bits": [0, 2], "name": "RT_SLICE"}, 13183 {"bits": [3, 6], "name": "VIEWPORT"}, 13184 {"bits": [8, 8], "name": "EN_STEREO"} 13185 ] 13186 }, 13187 "GE_USER_VGPR_EN": { 13188 "fields": [ 13189 {"bits": [0, 0], "name": "EN_USER_VGPR1"}, 13190 {"bits": [1, 1], "name": "EN_USER_VGPR2"}, 13191 {"bits": [2, 2], "name": "EN_USER_VGPR3"} 13192 ] 13193 }, 13194 "GRBM_GFX_INDEX": { 13195 "fields": [ 13196 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, 13197 {"bits": [8, 15], "name": "SA_INDEX"}, 13198 {"bits": [16, 23], "name": "SE_INDEX"}, 13199 {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"}, 13200 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, 13201 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} 13202 ] 13203 }, 13204 "GRBM_PERFCOUNTER0_SELECT": { 13205 "fields": [ 13206 {"bits": [0, 5], "name": "PERF_SEL"}, 13207 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 13208 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 13209 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, 13210 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, 13211 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 13212 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, 13213 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, 13214 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, 13215 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, 13216 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, 13217 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, 13218 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, 13219 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, 13220 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, 13221 {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"}, 13222 {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"}, 13223 {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"}, 13224 {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"}, 13225 {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"} 13226 ] 13227 }, 13228 "GRBM_PERFCOUNTER0_SELECT_HI": { 13229 "fields": [ 13230 {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"}, 13231 {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"}, 13232 {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"}, 13233 {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"}, 13234 {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"}, 13235 {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"}, 13236 {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"}, 13237 {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"} 13238 ] 13239 }, 13240 "GRBM_SE0_PERFCOUNTER_SELECT": { 13241 "fields": [ 13242 {"bits": [0, 5], "name": "PERF_SEL"}, 13243 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 13244 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 13245 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, 13246 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, 13247 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 13248 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, 13249 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, 13250 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, 13251 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, 13252 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}, 13253 {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"}, 13254 {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"}, 13255 {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"}, 13256 {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"} 13257 ] 13258 }, 13259 "GRBM_STATUS": { 13260 "fields": [ 13261 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, 13262 {"bits": [5, 5], "name": "RSMU_RQ_PENDING"}, 13263 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, 13264 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, 13265 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, 13266 {"bits": [12, 12], "name": "DB_CLEAN"}, 13267 {"bits": [13, 13], "name": "CB_CLEAN"}, 13268 {"bits": [14, 14], "name": "TA_BUSY"}, 13269 {"bits": [15, 15], "name": "GDS_BUSY"}, 13270 {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"}, 13271 {"bits": [20, 20], "name": "SX_BUSY"}, 13272 {"bits": [21, 21], "name": "GE_BUSY"}, 13273 {"bits": [22, 22], "name": "SPI_BUSY"}, 13274 {"bits": [23, 23], "name": "BCI_BUSY"}, 13275 {"bits": [24, 24], "name": "SC_BUSY"}, 13276 {"bits": [25, 25], "name": "PA_BUSY"}, 13277 {"bits": [26, 26], "name": "DB_BUSY"}, 13278 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, 13279 {"bits": [29, 29], "name": "CP_BUSY"}, 13280 {"bits": [30, 30], "name": "CB_BUSY"}, 13281 {"bits": [31, 31], "name": "GUI_ACTIVE"} 13282 ] 13283 }, 13284 "GRBM_STATUS2": { 13285 "fields": [ 13286 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, 13287 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, 13288 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, 13289 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, 13290 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, 13291 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, 13292 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, 13293 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, 13294 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, 13295 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, 13296 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, 13297 {"bits": [14, 14], "name": "RLC_RQ_PENDING"}, 13298 {"bits": [15, 15], "name": "UTCL2_BUSY"}, 13299 {"bits": [16, 16], "name": "EA_BUSY"}, 13300 {"bits": [17, 17], "name": "RMI_BUSY"}, 13301 {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"}, 13302 {"bits": [19, 19], "name": "CPF_RQ_PENDING"}, 13303 {"bits": [20, 20], "name": "EA_LINK_BUSY"}, 13304 {"bits": [21, 21], "name": "SDMA_BUSY"}, 13305 {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"}, 13306 {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"}, 13307 {"bits": [24, 24], "name": "RLC_BUSY"}, 13308 {"bits": [25, 25], "name": "TCP_BUSY"}, 13309 {"bits": [28, 28], "name": "CPF_BUSY"}, 13310 {"bits": [29, 29], "name": "CPC_BUSY"}, 13311 {"bits": [30, 30], "name": "CPG_BUSY"}, 13312 {"bits": [31, 31], "name": "CPAXI_BUSY"} 13313 ] 13314 }, 13315 "GRBM_STATUS3": { 13316 "fields": [ 13317 {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"}, 13318 {"bits": [6, 6], "name": "GRBM_UTCL2_INTR_CREDIT_PENDING"}, 13319 {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"}, 13320 {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"}, 13321 {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"}, 13322 {"bits": [10, 10], "name": "MESPIPE2_RQ_PENDING"}, 13323 {"bits": [11, 11], "name": "MESPIPE3_RQ_PENDING"}, 13324 {"bits": [13, 13], "name": "PH_BUSY"}, 13325 {"bits": [14, 14], "name": "CH_BUSY"}, 13326 {"bits": [15, 15], "name": "GL2CC_BUSY"}, 13327 {"bits": [16, 16], "name": "GL1CC_BUSY"}, 13328 {"bits": [28, 28], "name": "GUS_LINK_BUSY"}, 13329 {"bits": [29, 29], "name": "GUS_BUSY"}, 13330 {"bits": [30, 30], "name": "UTCL1_BUSY"}, 13331 {"bits": [31, 31], "name": "PMM_BUSY"} 13332 ] 13333 }, 13334 "GRBM_STATUS_SE0": { 13335 "fields": [ 13336 {"bits": [1, 1], "name": "DB_CLEAN"}, 13337 {"bits": [2, 2], "name": "CB_CLEAN"}, 13338 {"bits": [3, 3], "name": "UTCL1_BUSY"}, 13339 {"bits": [4, 4], "name": "TCP_BUSY"}, 13340 {"bits": [5, 5], "name": "GL1CC_BUSY"}, 13341 {"bits": [21, 21], "name": "RMI_BUSY"}, 13342 {"bits": [22, 22], "name": "BCI_BUSY"}, 13343 {"bits": [24, 24], "name": "PA_BUSY"}, 13344 {"bits": [25, 25], "name": "TA_BUSY"}, 13345 {"bits": [26, 26], "name": "SX_BUSY"}, 13346 {"bits": [27, 27], "name": "SPI_BUSY"}, 13347 {"bits": [29, 29], "name": "SC_BUSY"}, 13348 {"bits": [30, 30], "name": "DB_BUSY"}, 13349 {"bits": [31, 31], "name": "CB_BUSY"} 13350 ] 13351 }, 13352 "IA_MULTI_VGT_PARAM": { 13353 "fields": [ 13354 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, 13355 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, 13356 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, 13357 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, 13358 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, 13359 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"} 13360 ] 13361 }, 13362 "IA_MULTI_VGT_PARAM_PIPED": { 13363 "fields": [ 13364 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, 13365 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, 13366 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, 13367 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, 13368 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, 13369 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}, 13370 {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"}, 13371 {"bits": [22, 22], "name": "EN_INST_OPT_ADV"}, 13372 {"bits": [23, 23], "name": "HW_USE_ONLY"} 13373 ] 13374 }, 13375 "PA_CL_CLIP_CNTL": { 13376 "fields": [ 13377 {"bits": [0, 0], "name": "UCP_ENA_0"}, 13378 {"bits": [1, 1], "name": "UCP_ENA_1"}, 13379 {"bits": [2, 2], "name": "UCP_ENA_2"}, 13380 {"bits": [3, 3], "name": "UCP_ENA_3"}, 13381 {"bits": [4, 4], "name": "UCP_ENA_4"}, 13382 {"bits": [5, 5], "name": "UCP_ENA_5"}, 13383 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, 13384 {"bits": [14, 15], "name": "PS_UCP_MODE"}, 13385 {"bits": [16, 16], "name": "CLIP_DISABLE"}, 13386 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, 13387 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, 13388 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, 13389 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, 13390 {"bits": [21, 21], "name": "VTX_KILL_OR"}, 13391 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, 13392 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, 13393 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, 13394 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, 13395 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}, 13396 {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"} 13397 ] 13398 }, 13399 "PA_CL_NANINF_CNTL": { 13400 "fields": [ 13401 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, 13402 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, 13403 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, 13404 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, 13405 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, 13406 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, 13407 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, 13408 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, 13409 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, 13410 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, 13411 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, 13412 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, 13413 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, 13414 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, 13415 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, 13416 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} 13417 ] 13418 }, 13419 "PA_CL_NGG_CNTL": { 13420 "fields": [ 13421 {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"}, 13422 {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"} 13423 ] 13424 }, 13425 "PA_CL_OBJPRIM_ID_CNTL": { 13426 "fields": [ 13427 {"bits": [0, 0], "name": "OBJ_ID_SEL"}, 13428 {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"} 13429 ] 13430 }, 13431 "PA_CL_VS_OUT_CNTL": { 13432 "fields": [ 13433 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, 13434 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, 13435 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, 13436 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, 13437 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, 13438 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, 13439 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, 13440 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, 13441 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, 13442 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, 13443 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, 13444 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, 13445 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, 13446 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, 13447 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, 13448 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, 13449 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, 13450 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, 13451 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, 13452 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, 13453 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, 13454 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, 13455 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, 13456 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, 13457 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, 13458 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"}, 13459 {"bits": [26, 26], "name": "USE_VTX_SHD_OBJPRIM_ID"}, 13460 {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"} 13461 ] 13462 }, 13463 "PA_CL_VTE_CNTL": { 13464 "fields": [ 13465 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, 13466 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, 13467 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, 13468 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, 13469 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, 13470 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, 13471 {"bits": [8, 8], "name": "VTX_XY_FMT"}, 13472 {"bits": [9, 9], "name": "VTX_Z_FMT"}, 13473 {"bits": [10, 10], "name": "VTX_W0_FMT"}, 13474 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} 13475 ] 13476 }, 13477 "PA_SC_AA_CONFIG": { 13478 "fields": [ 13479 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, 13480 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, 13481 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, 13482 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, 13483 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}, 13484 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"} 13485 ] 13486 }, 13487 "PA_SC_AA_MASK_X0Y0_X1Y0": { 13488 "fields": [ 13489 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, 13490 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} 13491 ] 13492 }, 13493 "PA_SC_AA_MASK_X0Y1_X1Y1": { 13494 "fields": [ 13495 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, 13496 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} 13497 ] 13498 }, 13499 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": { 13500 "fields": [ 13501 {"bits": [0, 3], "name": "S0_X"}, 13502 {"bits": [4, 7], "name": "S0_Y"}, 13503 {"bits": [8, 11], "name": "S1_X"}, 13504 {"bits": [12, 15], "name": "S1_Y"}, 13505 {"bits": [16, 19], "name": "S2_X"}, 13506 {"bits": [20, 23], "name": "S2_Y"}, 13507 {"bits": [24, 27], "name": "S3_X"}, 13508 {"bits": [28, 31], "name": "S3_Y"} 13509 ] 13510 }, 13511 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": { 13512 "fields": [ 13513 {"bits": [0, 3], "name": "S4_X"}, 13514 {"bits": [4, 7], "name": "S4_Y"}, 13515 {"bits": [8, 11], "name": "S5_X"}, 13516 {"bits": [12, 15], "name": "S5_Y"}, 13517 {"bits": [16, 19], "name": "S6_X"}, 13518 {"bits": [20, 23], "name": "S6_Y"}, 13519 {"bits": [24, 27], "name": "S7_X"}, 13520 {"bits": [28, 31], "name": "S7_Y"} 13521 ] 13522 }, 13523 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": { 13524 "fields": [ 13525 {"bits": [0, 3], "name": "S8_X"}, 13526 {"bits": [4, 7], "name": "S8_Y"}, 13527 {"bits": [8, 11], "name": "S9_X"}, 13528 {"bits": [12, 15], "name": "S9_Y"}, 13529 {"bits": [16, 19], "name": "S10_X"}, 13530 {"bits": [20, 23], "name": "S10_Y"}, 13531 {"bits": [24, 27], "name": "S11_X"}, 13532 {"bits": [28, 31], "name": "S11_Y"} 13533 ] 13534 }, 13535 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": { 13536 "fields": [ 13537 {"bits": [0, 3], "name": "S12_X"}, 13538 {"bits": [4, 7], "name": "S12_Y"}, 13539 {"bits": [8, 11], "name": "S13_X"}, 13540 {"bits": [12, 15], "name": "S13_Y"}, 13541 {"bits": [16, 19], "name": "S14_X"}, 13542 {"bits": [20, 23], "name": "S14_Y"}, 13543 {"bits": [24, 27], "name": "S15_X"}, 13544 {"bits": [28, 31], "name": "S15_Y"} 13545 ] 13546 }, 13547 "PA_SC_BINNER_CNTL_0": { 13548 "fields": [ 13549 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"}, 13550 {"bits": [2, 2], "name": "BIN_SIZE_X"}, 13551 {"bits": [3, 3], "name": "BIN_SIZE_Y"}, 13552 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"}, 13553 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"}, 13554 {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"}, 13555 {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"}, 13556 {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"}, 13557 {"bits": [19, 26], "name": "FPOVS_PER_BATCH"}, 13558 {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"}, 13559 {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"}, 13560 {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"} 13561 ] 13562 }, 13563 "PA_SC_BINNER_CNTL_1": { 13564 "fields": [ 13565 {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"}, 13566 {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"} 13567 ] 13568 }, 13569 "PA_SC_CENTROID_PRIORITY_0": { 13570 "fields": [ 13571 {"bits": [0, 3], "name": "DISTANCE_0"}, 13572 {"bits": [4, 7], "name": "DISTANCE_1"}, 13573 {"bits": [8, 11], "name": "DISTANCE_2"}, 13574 {"bits": [12, 15], "name": "DISTANCE_3"}, 13575 {"bits": [16, 19], "name": "DISTANCE_4"}, 13576 {"bits": [20, 23], "name": "DISTANCE_5"}, 13577 {"bits": [24, 27], "name": "DISTANCE_6"}, 13578 {"bits": [28, 31], "name": "DISTANCE_7"} 13579 ] 13580 }, 13581 "PA_SC_CENTROID_PRIORITY_1": { 13582 "fields": [ 13583 {"bits": [0, 3], "name": "DISTANCE_8"}, 13584 {"bits": [4, 7], "name": "DISTANCE_9"}, 13585 {"bits": [8, 11], "name": "DISTANCE_10"}, 13586 {"bits": [12, 15], "name": "DISTANCE_11"}, 13587 {"bits": [16, 19], "name": "DISTANCE_12"}, 13588 {"bits": [20, 23], "name": "DISTANCE_13"}, 13589 {"bits": [24, 27], "name": "DISTANCE_14"}, 13590 {"bits": [28, 31], "name": "DISTANCE_15"} 13591 ] 13592 }, 13593 "PA_SC_CLIPRECT_0_TL": { 13594 "fields": [ 13595 {"bits": [0, 14], "name": "TL_X"}, 13596 {"bits": [16, 30], "name": "TL_Y"} 13597 ] 13598 }, 13599 "PA_SC_CLIPRECT_RULE": { 13600 "fields": [ 13601 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} 13602 ] 13603 }, 13604 "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": { 13605 "fields": [ 13606 {"bits": [0, 0], "name": "OVER_RAST_ENABLE"}, 13607 {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"}, 13608 {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"}, 13609 {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"}, 13610 {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"}, 13611 {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"}, 13612 {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"}, 13613 {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"}, 13614 {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"}, 13615 {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"}, 13616 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"}, 13617 {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"}, 13618 {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"}, 13619 {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"}, 13620 {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"}, 13621 {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"}, 13622 {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"}, 13623 {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"}, 13624 {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"}, 13625 {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"} 13626 ] 13627 }, 13628 "PA_SC_EDGERULE": { 13629 "fields": [ 13630 {"bits": [0, 3], "name": "ER_TRI"}, 13631 {"bits": [4, 7], "name": "ER_POINT"}, 13632 {"bits": [8, 11], "name": "ER_RECT"}, 13633 {"bits": [12, 17], "name": "ER_LINE_LR"}, 13634 {"bits": [18, 23], "name": "ER_LINE_RL"}, 13635 {"bits": [24, 27], "name": "ER_LINE_TB"}, 13636 {"bits": [28, 31], "name": "ER_LINE_BT"} 13637 ] 13638 }, 13639 "PA_SC_HORIZ_GRID": { 13640 "fields": [ 13641 {"bits": [0, 7], "name": "TOP_QTR"}, 13642 {"bits": [8, 15], "name": "TOP_HALF"}, 13643 {"bits": [16, 23], "name": "BOT_HALF"}, 13644 {"bits": [24, 31], "name": "BOT_QTR"} 13645 ] 13646 }, 13647 "PA_SC_LINE_CNTL": { 13648 "fields": [ 13649 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, 13650 {"bits": [10, 10], "name": "LAST_PIXEL"}, 13651 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, 13652 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}, 13653 {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"} 13654 ] 13655 }, 13656 "PA_SC_LINE_STIPPLE": { 13657 "fields": [ 13658 {"bits": [0, 15], "name": "LINE_PATTERN"}, 13659 {"bits": [16, 23], "name": "REPEAT_COUNT"}, 13660 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, 13661 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} 13662 ] 13663 }, 13664 "PA_SC_LINE_STIPPLE_STATE": { 13665 "fields": [ 13666 {"bits": [0, 3], "name": "CURRENT_PTR"}, 13667 {"bits": [8, 15], "name": "CURRENT_COUNT"} 13668 ] 13669 }, 13670 "PA_SC_MODE_CNTL_0": { 13671 "fields": [ 13672 {"bits": [0, 0], "name": "MSAA_ENABLE"}, 13673 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, 13674 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, 13675 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}, 13676 {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"}, 13677 {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"}, 13678 {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"} 13679 ] 13680 }, 13681 "PA_SC_MODE_CNTL_1": { 13682 "fields": [ 13683 {"bits": [0, 0], "name": "WALK_SIZE"}, 13684 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, 13685 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, 13686 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, 13687 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, 13688 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, 13689 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, 13690 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, 13691 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, 13692 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, 13693 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, 13694 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, 13695 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, 13696 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, 13697 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, 13698 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, 13699 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, 13700 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, 13701 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, 13702 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, 13703 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, 13704 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, 13705 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, 13706 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} 13707 ] 13708 }, 13709 "PA_SC_NGG_MODE_CNTL": { 13710 "fields": [ 13711 {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"}, 13712 {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"} 13713 ] 13714 }, 13715 "PA_SC_P3D_TRAP_SCREEN_H": { 13716 "fields": [ 13717 {"bits": [0, 13], "name": "X_COORD"} 13718 ] 13719 }, 13720 "PA_SC_P3D_TRAP_SCREEN_HV_EN": { 13721 "fields": [ 13722 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"}, 13723 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"} 13724 ] 13725 }, 13726 "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": { 13727 "fields": [ 13728 {"bits": [0, 15], "name": "COUNT"} 13729 ] 13730 }, 13731 "PA_SC_P3D_TRAP_SCREEN_V": { 13732 "fields": [ 13733 {"bits": [0, 13], "name": "Y_COORD"} 13734 ] 13735 }, 13736 "PA_SC_PERFCOUNTER1_SELECT": { 13737 "fields": [ 13738 {"bits": [0, 9], "name": "PERF_SEL"} 13739 ] 13740 }, 13741 "PA_SC_RASTER_CONFIG": { 13742 "fields": [ 13743 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, 13744 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, 13745 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, 13746 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, 13747 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, 13748 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, 13749 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, 13750 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, 13751 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, 13752 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, 13753 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, 13754 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, 13755 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, 13756 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, 13757 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} 13758 ] 13759 }, 13760 "PA_SC_RASTER_CONFIG_1": { 13761 "fields": [ 13762 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, 13763 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, 13764 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} 13765 ] 13766 }, 13767 "PA_SC_RIGHT_VERT_GRID": { 13768 "fields": [ 13769 {"bits": [0, 7], "name": "LEFT_QTR"}, 13770 {"bits": [8, 15], "name": "LEFT_HALF"}, 13771 {"bits": [16, 23], "name": "RIGHT_HALF"}, 13772 {"bits": [24, 31], "name": "RIGHT_QTR"} 13773 ] 13774 }, 13775 "PA_SC_SCREEN_EXTENT_CONTROL": { 13776 "fields": [ 13777 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"}, 13778 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"} 13779 ] 13780 }, 13781 "PA_SC_SCREEN_EXTENT_MIN_0": { 13782 "fields": [ 13783 {"bits": [0, 15], "name": "X"}, 13784 {"bits": [16, 31], "name": "Y"} 13785 ] 13786 }, 13787 "PA_SC_SCREEN_SCISSOR_BR": { 13788 "fields": [ 13789 {"bits": [0, 15], "name": "BR_X"}, 13790 {"bits": [16, 31], "name": "BR_Y"} 13791 ] 13792 }, 13793 "PA_SC_SCREEN_SCISSOR_TL": { 13794 "fields": [ 13795 {"bits": [0, 15], "name": "TL_X"}, 13796 {"bits": [16, 31], "name": "TL_Y"} 13797 ] 13798 }, 13799 "PA_SC_SHADER_CONTROL": { 13800 "fields": [ 13801 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}, 13802 {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"}, 13803 {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"}, 13804 {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"} 13805 ] 13806 }, 13807 "PA_SC_TILE_STEERING_OVERRIDE": { 13808 "fields": [ 13809 {"bits": [0, 0], "name": "ENABLE"}, 13810 {"bits": [1, 2], "name": "NUM_SE"}, 13811 {"bits": [5, 6], "name": "NUM_RB_PER_SE"}, 13812 {"bits": [8, 8], "name": "DISABLE_SRBSL_DB_OPTIMIZED_PACKING"}, 13813 {"bits": [12, 13], "name": "NUM_SC"}, 13814 {"bits": [16, 17], "name": "NUM_RB_PER_SC"}, 13815 {"bits": [20, 20], "name": "NUM_PACKER_PER_SC"} 13816 ] 13817 }, 13818 "PA_SC_WINDOW_OFFSET": { 13819 "fields": [ 13820 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, 13821 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} 13822 ] 13823 }, 13824 "PA_SC_WINDOW_SCISSOR_BR": { 13825 "fields": [ 13826 {"bits": [0, 14], "name": "BR_X"}, 13827 {"bits": [16, 30], "name": "BR_Y"} 13828 ] 13829 }, 13830 "PA_SC_WINDOW_SCISSOR_TL": { 13831 "fields": [ 13832 {"bits": [0, 14], "name": "TL_X"}, 13833 {"bits": [16, 30], "name": "TL_Y"}, 13834 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} 13835 ] 13836 }, 13837 "PA_STEREO_CNTL": { 13838 "fields": [ 13839 {"bits": [1, 4], "name": "STEREO_MODE"}, 13840 {"bits": [5, 7], "name": "RT_SLICE_MODE"}, 13841 {"bits": [8, 11], "name": "RT_SLICE_OFFSET"}, 13842 {"bits": [16, 18], "name": "VP_ID_MODE"}, 13843 {"bits": [19, 22], "name": "VP_ID_OFFSET"} 13844 ] 13845 }, 13846 "PA_SU_HARDWARE_SCREEN_OFFSET": { 13847 "fields": [ 13848 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, 13849 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} 13850 ] 13851 }, 13852 "PA_SU_LINE_CNTL": { 13853 "fields": [ 13854 {"bits": [0, 15], "name": "WIDTH"} 13855 ] 13856 }, 13857 "PA_SU_LINE_STIPPLE_CNTL": { 13858 "fields": [ 13859 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, 13860 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, 13861 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, 13862 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} 13863 ] 13864 }, 13865 "PA_SU_LINE_STIPPLE_VALUE": { 13866 "fields": [ 13867 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} 13868 ] 13869 }, 13870 "PA_SU_OVER_RASTERIZATION_CNTL": { 13871 "fields": [ 13872 {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"}, 13873 {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"}, 13874 {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"}, 13875 {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"}, 13876 {"bits": [4, 4], "name": "USE_PROVOKING_ZW"} 13877 ] 13878 }, 13879 "PA_SU_PERFCOUNTER0_HI": { 13880 "fields": [ 13881 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} 13882 ] 13883 }, 13884 "PA_SU_PERFCOUNTER0_SELECT": { 13885 "fields": [ 13886 {"bits": [0, 9], "name": "PERF_SEL"}, 13887 {"bits": [10, 19], "name": "PERF_SEL1"}, 13888 {"bits": [20, 23], "name": "CNTR_MODE"}, 13889 {"bits": [24, 27], "name": "PERF_MODE1"}, 13890 {"bits": [28, 31], "name": "PERF_MODE"} 13891 ] 13892 }, 13893 "PA_SU_PERFCOUNTER0_SELECT1": { 13894 "fields": [ 13895 {"bits": [0, 9], "name": "PERF_SEL2"}, 13896 {"bits": [10, 19], "name": "PERF_SEL3"}, 13897 {"bits": [24, 27], "name": "PERF_MODE3"}, 13898 {"bits": [28, 31], "name": "PERF_MODE2"} 13899 ] 13900 }, 13901 "PA_SU_POINT_MINMAX": { 13902 "fields": [ 13903 {"bits": [0, 15], "name": "MIN_SIZE"}, 13904 {"bits": [16, 31], "name": "MAX_SIZE"} 13905 ] 13906 }, 13907 "PA_SU_POINT_SIZE": { 13908 "fields": [ 13909 {"bits": [0, 15], "name": "HEIGHT"}, 13910 {"bits": [16, 31], "name": "WIDTH"} 13911 ] 13912 }, 13913 "PA_SU_POLY_OFFSET_DB_FMT_CNTL": { 13914 "fields": [ 13915 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, 13916 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} 13917 ] 13918 }, 13919 "PA_SU_PRIM_FILTER_CNTL": { 13920 "fields": [ 13921 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, 13922 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, 13923 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, 13924 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, 13925 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, 13926 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, 13927 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, 13928 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, 13929 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, 13930 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, 13931 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} 13932 ] 13933 }, 13934 "PA_SU_SC_MODE_CNTL": { 13935 "fields": [ 13936 {"bits": [0, 0], "name": "CULL_FRONT"}, 13937 {"bits": [1, 1], "name": "CULL_BACK"}, 13938 {"bits": [2, 2], "name": "FACE"}, 13939 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, 13940 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"}, 13941 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"}, 13942 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, 13943 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, 13944 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, 13945 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, 13946 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, 13947 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, 13948 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}, 13949 {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"}, 13950 {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"}, 13951 {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"} 13952 ] 13953 }, 13954 "PA_SU_SMALL_PRIM_FILTER_CNTL": { 13955 "fields": [ 13956 {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"}, 13957 {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"}, 13958 {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"}, 13959 {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"}, 13960 {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}, 13961 {"bits": [5, 5], "name": "SRBSL_ENABLE"}, 13962 {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"} 13963 ] 13964 }, 13965 "PA_SU_VTX_CNTL": { 13966 "fields": [ 13967 {"bits": [0, 0], "name": "PIX_CENTER"}, 13968 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, 13969 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} 13970 ] 13971 }, 13972 "RLC_GPM_PERF_COUNT_0": { 13973 "fields": [ 13974 {"bits": [0, 3], "name": "FEATURE_SEL"}, 13975 {"bits": [4, 7], "name": "SE_INDEX"}, 13976 {"bits": [8, 11], "name": "SA_INDEX"}, 13977 {"bits": [12, 15], "name": "WGP_INDEX"}, 13978 {"bits": [16, 17], "name": "EVENT_SEL"}, 13979 {"bits": [18, 19], "name": "UNUSED"}, 13980 {"bits": [20, 20], "name": "ENABLE"}, 13981 {"bits": [21, 31], "name": "RESERVED"} 13982 ] 13983 }, 13984 "RLC_GPU_IOV_PERF_CNT_CNTL": { 13985 "fields": [ 13986 {"bits": [0, 0], "name": "ENABLE"}, 13987 {"bits": [1, 1], "name": "MODE_SELECT"}, 13988 {"bits": [2, 2], "name": "RESET"}, 13989 {"bits": [3, 31], "name": "RESERVED"} 13990 ] 13991 }, 13992 "RLC_GPU_IOV_PERF_CNT_WR_ADDR": { 13993 "fields": [ 13994 {"bits": [0, 3], "name": "VFID"}, 13995 {"bits": [4, 5], "name": "CNT_ID"}, 13996 {"bits": [6, 31], "name": "RESERVED"} 13997 ] 13998 }, 13999 "RLC_PERFCOUNTER0_SELECT": { 14000 "fields": [ 14001 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"} 14002 ] 14003 }, 14004 "RLC_PERFMON_CLK_CNTL": { 14005 "fields": [ 14006 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"} 14007 ] 14008 }, 14009 "RLC_PERFMON_CNTL": { 14010 "fields": [ 14011 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, 14012 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} 14013 ] 14014 }, 14015 "RLC_SPM_ACCUM_CTRL": { 14016 "fields": [ 14017 {"bits": [0, 0], "name": "StrobeResetPerfMonitors"}, 14018 {"bits": [1, 1], "name": "StrobeStartAccumulation"}, 14019 {"bits": [2, 2], "name": "StrobeRearmAccum"}, 14020 {"bits": [3, 3], "name": "StrobeSpmDoneInt"}, 14021 {"bits": [4, 4], "name": "StrobeAccumDoneInt"}, 14022 {"bits": [5, 5], "name": "StrobeResetAccum"}, 14023 {"bits": [6, 9], "name": "StrobeStartSpm"}, 14024 {"bits": [10, 31], "name": "RESERVED"} 14025 ] 14026 }, 14027 "RLC_SPM_ACCUM_CTRLRAM_ADDR": { 14028 "fields": [ 14029 {"bits": [0, 8], "name": "addr"}, 14030 {"bits": [9, 31], "name": "RESERVED"} 14031 ] 14032 }, 14033 "RLC_SPM_ACCUM_CTRLRAM_DATA": { 14034 "fields": [ 14035 {"bits": [0, 7], "name": "data"}, 14036 {"bits": [8, 31], "name": "RESERVED"} 14037 ] 14038 }, 14039 "RLC_SPM_ACCUM_DATARAM_ADDR": { 14040 "fields": [ 14041 {"bits": [0, 6], "name": "addr"}, 14042 {"bits": [7, 31], "name": "RESERVED"} 14043 ] 14044 }, 14045 "RLC_SPM_ACCUM_DATARAM_WRCOUNT": { 14046 "fields": [ 14047 {"bits": [0, 18], "name": "DataRamWrCount"}, 14048 {"bits": [19, 31], "name": "RESERVED"} 14049 ] 14050 }, 14051 "RLC_SPM_ACCUM_MODE": { 14052 "fields": [ 14053 {"bits": [0, 0], "name": "EnableAccum"}, 14054 {"bits": [1, 1], "name": "AutoAccumEn"}, 14055 {"bits": [2, 2], "name": "AutoSpmEn"}, 14056 {"bits": [3, 3], "name": "Globals_LoadOverride"}, 14057 {"bits": [4, 4], "name": "SE0_LoadOverride"}, 14058 {"bits": [5, 5], "name": "SE1_LoadOverride"}, 14059 {"bits": [6, 6], "name": "AutoResetPerfmonDisable"}, 14060 {"bits": [7, 31], "name": "RESERVED"} 14061 ] 14062 }, 14063 "RLC_SPM_ACCUM_SAMPLES_REQUESTED": { 14064 "fields": [ 14065 {"bits": [0, 7], "name": "SamplesRequested"}, 14066 {"bits": [8, 31], "name": "RESERVED"} 14067 ] 14068 }, 14069 "RLC_SPM_ACCUM_STATUS": { 14070 "fields": [ 14071 {"bits": [0, 7], "name": "NumbSamplesCompleted"}, 14072 {"bits": [8, 8], "name": "AccumDone"}, 14073 {"bits": [9, 9], "name": "SpmDone"}, 14074 {"bits": [10, 10], "name": "AccumOverflow"}, 14075 {"bits": [11, 11], "name": "AccumArmed"}, 14076 {"bits": [12, 12], "name": "SequenceInProgress"}, 14077 {"bits": [13, 13], "name": "FinalSequenceInProgress"}, 14078 {"bits": [14, 14], "name": "AllFifosEmpty"}, 14079 {"bits": [15, 15], "name": "FSMIsIdle"}, 14080 {"bits": [16, 31], "name": "RESERVED"} 14081 ] 14082 }, 14083 "RLC_SPM_ACCUM_THRESHOLD": { 14084 "fields": [ 14085 {"bits": [0, 15], "name": "Threshold"}, 14086 {"bits": [16, 31], "name": "RESERVED"} 14087 ] 14088 }, 14089 "RLC_SPM_DESER_START_SKEW": { 14090 "fields": [ 14091 {"bits": [0, 6], "name": "DESER_START_SKEW"}, 14092 {"bits": [7, 31], "name": "RESERVED"} 14093 ] 14094 }, 14095 "RLC_SPM_GLB_SAMPLEDELAY_IND_DATA": { 14096 "fields": [ 14097 {"bits": [0, 6], "name": "data"}, 14098 {"bits": [7, 31], "name": "RESERVED"} 14099 ] 14100 }, 14101 "RLC_SPM_GLOBALS_MUXSEL_SKEW": { 14102 "fields": [ 14103 {"bits": [0, 6], "name": "GLOBALS_MUXSEL_SKEW"}, 14104 {"bits": [7, 31], "name": "RESERVED"} 14105 ] 14106 }, 14107 "RLC_SPM_GLOBALS_SAMPLE_SKEW": { 14108 "fields": [ 14109 {"bits": [0, 6], "name": "GLOBALS_SAMPLE_SKEW"}, 14110 {"bits": [7, 31], "name": "RESERVED"} 14111 ] 14112 }, 14113 "RLC_SPM_GLOBAL_MUXSEL_ADDR": { 14114 "fields": [ 14115 {"bits": [0, 7], "name": "PERFMON_SEL_ADDR"}, 14116 {"bits": [8, 31], "name": "RESERVED"} 14117 ] 14118 }, 14119 "RLC_SPM_PERFMON_CNTL": { 14120 "fields": [ 14121 {"bits": [0, 11], "name": "RESERVED1"}, 14122 {"bits": [12, 13], "name": "PERFMON_RING_MODE"}, 14123 {"bits": [14, 15], "name": "RESERVED"}, 14124 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"} 14125 ] 14126 }, 14127 "RLC_SPM_PERFMON_GLB_SEGMENT_SIZE": { 14128 "fields": [ 14129 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, 14130 {"bits": [8, 15], "name": "GLOBAL_NUM_LINE"}, 14131 {"bits": [16, 31], "name": "RESERVED"} 14132 ] 14133 }, 14134 "RLC_SPM_PERFMON_RING_BASE_HI": { 14135 "fields": [ 14136 {"bits": [0, 15], "name": "RING_BASE_HI"}, 14137 {"bits": [16, 31], "name": "RESERVED"} 14138 ] 14139 }, 14140 "RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE": { 14141 "fields": [ 14142 {"bits": [0, 7], "name": "SE0_NUM_LINE"}, 14143 {"bits": [8, 15], "name": "SE1_NUM_LINE"}, 14144 {"bits": [16, 23], "name": "SE2_NUM_LINE"}, 14145 {"bits": [24, 31], "name": "SE3_NUM_LINE"} 14146 ] 14147 }, 14148 "RLC_SPM_PERFMON_SEGMENT_SIZE": { 14149 "fields": [ 14150 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, 14151 {"bits": [8, 10], "name": "RESERVED1"}, 14152 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"}, 14153 {"bits": [16, 20], "name": "SE0_NUM_LINE"}, 14154 {"bits": [21, 25], "name": "SE1_NUM_LINE"}, 14155 {"bits": [26, 30], "name": "SE2_NUM_LINE"}, 14156 {"bits": [31, 31], "name": "RESERVED"} 14157 ] 14158 }, 14159 "RLC_SPM_RING_WRPTR": { 14160 "fields": [ 14161 {"bits": [0, 4], "name": "RESERVED"}, 14162 {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"} 14163 ] 14164 }, 14165 "RLC_SPM_SEGMENT_THRESHOLD": { 14166 "fields": [ 14167 {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"}, 14168 {"bits": [8, 31], "name": "RESERVED"} 14169 ] 14170 }, 14171 "RLC_SPM_SE_MUXSEL_ADDR": { 14172 "fields": [ 14173 {"bits": [0, 8], "name": "PERFMON_SEL_ADDR"}, 14174 {"bits": [9, 31], "name": "RESERVED"} 14175 ] 14176 }, 14177 "RLC_SPM_SE_MUXSEL_SKEW": { 14178 "fields": [ 14179 {"bits": [0, 6], "name": "SE_MUXSEL_SKEW"}, 14180 {"bits": [7, 31], "name": "RESERVED"} 14181 ] 14182 }, 14183 "RLC_SPM_SE_SAMPLE_SKEW": { 14184 "fields": [ 14185 {"bits": [0, 6], "name": "SE_SAMPLE_SKEW"}, 14186 {"bits": [7, 31], "name": "RESERVED"} 14187 ] 14188 }, 14189 "RLC_SPM_VIRT_CTRL": { 14190 "fields": [ 14191 {"bits": [0, 0], "name": "PauseSpmSamplingRequest"} 14192 ] 14193 }, 14194 "RLC_SPM_VIRT_STATUS": { 14195 "fields": [ 14196 {"bits": [0, 0], "name": "SpmSamplingPaused"} 14197 ] 14198 }, 14199 "RMI_PERF_COUNTER_CNTL": { 14200 "fields": [ 14201 {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"}, 14202 {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"}, 14203 {"bits": [4, 5], "name": "TC_PERF_EN_SEL"}, 14204 {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"}, 14205 {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"}, 14206 {"bits": [10, 13], "name": "PERF_COUNTER_CID"}, 14207 {"bits": [14, 18], "name": "PERF_COUNTER_VMID"}, 14208 {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"}, 14209 {"bits": [25, 25], "name": "PERF_SOFT_RESET"}, 14210 {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"} 14211 ] 14212 }, 14213 "SCRATCH_UMSK": { 14214 "fields": [ 14215 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, 14216 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} 14217 ] 14218 }, 14219 "SPI_BARYC_CNTL": { 14220 "fields": [ 14221 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, 14222 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, 14223 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, 14224 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, 14225 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, 14226 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, 14227 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} 14228 ] 14229 }, 14230 "SPI_CONFIG_CNTL": { 14231 "fields": [ 14232 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, 14233 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, 14234 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, 14235 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, 14236 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, 14237 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}, 14238 {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"}, 14239 {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"}, 14240 {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"} 14241 ] 14242 }, 14243 "SPI_INTERP_CONTROL_0": { 14244 "fields": [ 14245 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, 14246 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, 14247 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, 14248 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, 14249 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, 14250 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, 14251 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} 14252 ] 14253 }, 14254 "SPI_PERFCOUNTER_BINS": { 14255 "fields": [ 14256 {"bits": [0, 3], "name": "BIN0_MIN"}, 14257 {"bits": [4, 7], "name": "BIN0_MAX"}, 14258 {"bits": [8, 11], "name": "BIN1_MIN"}, 14259 {"bits": [12, 15], "name": "BIN1_MAX"}, 14260 {"bits": [16, 19], "name": "BIN2_MIN"}, 14261 {"bits": [20, 23], "name": "BIN2_MAX"}, 14262 {"bits": [24, 27], "name": "BIN3_MIN"}, 14263 {"bits": [28, 31], "name": "BIN3_MAX"} 14264 ] 14265 }, 14266 "SPI_PS_INPUT_CNTL_0": { 14267 "fields": [ 14268 {"bits": [0, 5], "name": "OFFSET"}, 14269 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 14270 {"bits": [10, 10], "name": "FLAT_SHADE"}, 14271 {"bits": [13, 16], "name": "CYL_WRAP"}, 14272 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, 14273 {"bits": [18, 18], "name": "DUP"}, 14274 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, 14275 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, 14276 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, 14277 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"}, 14278 {"bits": [24, 24], "name": "ATTR0_VALID"}, 14279 {"bits": [25, 25], "name": "ATTR1_VALID"} 14280 ] 14281 }, 14282 "SPI_PS_INPUT_CNTL_20": { 14283 "fields": [ 14284 {"bits": [0, 5], "name": "OFFSET"}, 14285 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 14286 {"bits": [10, 10], "name": "FLAT_SHADE"}, 14287 {"bits": [18, 18], "name": "DUP"}, 14288 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, 14289 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, 14290 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, 14291 {"bits": [24, 24], "name": "ATTR0_VALID"}, 14292 {"bits": [25, 25], "name": "ATTR1_VALID"} 14293 ] 14294 }, 14295 "SPI_PS_INPUT_ENA": { 14296 "fields": [ 14297 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, 14298 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, 14299 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, 14300 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, 14301 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, 14302 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, 14303 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, 14304 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, 14305 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, 14306 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, 14307 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, 14308 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, 14309 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, 14310 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, 14311 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, 14312 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} 14313 ] 14314 }, 14315 "SPI_PS_IN_CONTROL": { 14316 "fields": [ 14317 {"bits": [0, 5], "name": "NUM_INTERP"}, 14318 {"bits": [6, 6], "name": "PARAM_GEN"}, 14319 {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"}, 14320 {"bits": [8, 8], "name": "LATE_PC_DEALLOC"}, 14321 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"}, 14322 {"bits": [15, 15], "name": "PS_W32_EN"} 14323 ] 14324 }, 14325 "SPI_SHADER_COL_FORMAT": { 14326 "fields": [ 14327 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, 14328 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, 14329 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, 14330 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, 14331 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, 14332 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, 14333 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, 14334 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} 14335 ] 14336 }, 14337 "SPI_SHADER_IDX_FORMAT": { 14338 "fields": [ 14339 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"} 14340 ] 14341 }, 14342 "SPI_SHADER_LATE_ALLOC_VS": { 14343 "fields": [ 14344 {"bits": [0, 5], "name": "LIMIT"} 14345 ] 14346 }, 14347 "SPI_SHADER_PGM_HI_PS": { 14348 "fields": [ 14349 {"bits": [0, 7], "name": "MEM_BASE"} 14350 ] 14351 }, 14352 "SPI_SHADER_PGM_RSRC1_ES": { 14353 "fields": [ 14354 {"bits": [0, 5], "name": "VGPRS"}, 14355 {"bits": [6, 9], "name": "SGPRS"}, 14356 {"bits": [10, 11], "name": "PRIORITY"}, 14357 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 14358 {"bits": [20, 20], "name": "PRIV"}, 14359 {"bits": [21, 21], "name": "DX10_CLAMP"}, 14360 {"bits": [23, 23], "name": "IEEE_MODE"}, 14361 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 14362 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, 14363 {"bits": [31, 31], "name": "FP16_OVFL"} 14364 ] 14365 }, 14366 "SPI_SHADER_PGM_RSRC1_GS": { 14367 "fields": [ 14368 {"bits": [0, 5], "name": "VGPRS"}, 14369 {"bits": [6, 9], "name": "SGPRS"}, 14370 {"bits": [10, 11], "name": "PRIORITY"}, 14371 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 14372 {"bits": [20, 20], "name": "PRIV"}, 14373 {"bits": [21, 21], "name": "DX10_CLAMP"}, 14374 {"bits": [23, 23], "name": "IEEE_MODE"}, 14375 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, 14376 {"bits": [25, 25], "name": "MEM_ORDERED"}, 14377 {"bits": [26, 26], "name": "FWD_PROGRESS"}, 14378 {"bits": [27, 27], "name": "WGP_MODE"}, 14379 {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"}, 14380 {"bits": [31, 31], "name": "FP16_OVFL"} 14381 ] 14382 }, 14383 "SPI_SHADER_PGM_RSRC1_HS": { 14384 "fields": [ 14385 {"bits": [0, 5], "name": "VGPRS"}, 14386 {"bits": [6, 9], "name": "SGPRS"}, 14387 {"bits": [10, 11], "name": "PRIORITY"}, 14388 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 14389 {"bits": [20, 20], "name": "PRIV"}, 14390 {"bits": [21, 21], "name": "DX10_CLAMP"}, 14391 {"bits": [23, 23], "name": "IEEE_MODE"}, 14392 {"bits": [24, 24], "name": "MEM_ORDERED"}, 14393 {"bits": [25, 25], "name": "FWD_PROGRESS"}, 14394 {"bits": [26, 26], "name": "WGP_MODE"}, 14395 {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"}, 14396 {"bits": [30, 30], "name": "FP16_OVFL"} 14397 ] 14398 }, 14399 "SPI_SHADER_PGM_RSRC1_LS": { 14400 "fields": [ 14401 {"bits": [0, 5], "name": "VGPRS"}, 14402 {"bits": [6, 9], "name": "SGPRS"}, 14403 {"bits": [10, 11], "name": "PRIORITY"}, 14404 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 14405 {"bits": [20, 20], "name": "PRIV"}, 14406 {"bits": [21, 21], "name": "DX10_CLAMP"}, 14407 {"bits": [23, 23], "name": "IEEE_MODE"}, 14408 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 14409 {"bits": [30, 30], "name": "FP16_OVFL"} 14410 ] 14411 }, 14412 "SPI_SHADER_PGM_RSRC1_PS": { 14413 "fields": [ 14414 {"bits": [0, 5], "name": "VGPRS"}, 14415 {"bits": [6, 9], "name": "SGPRS"}, 14416 {"bits": [10, 11], "name": "PRIORITY"}, 14417 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 14418 {"bits": [20, 20], "name": "PRIV"}, 14419 {"bits": [21, 21], "name": "DX10_CLAMP"}, 14420 {"bits": [23, 23], "name": "IEEE_MODE"}, 14421 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, 14422 {"bits": [25, 25], "name": "MEM_ORDERED"}, 14423 {"bits": [26, 26], "name": "FWD_PROGRESS"}, 14424 {"bits": [29, 29], "name": "FP16_OVFL"} 14425 ] 14426 }, 14427 "SPI_SHADER_PGM_RSRC1_VS": { 14428 "fields": [ 14429 {"bits": [0, 5], "name": "VGPRS"}, 14430 {"bits": [6, 9], "name": "SGPRS"}, 14431 {"bits": [10, 11], "name": "PRIORITY"}, 14432 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 14433 {"bits": [20, 20], "name": "PRIV"}, 14434 {"bits": [21, 21], "name": "DX10_CLAMP"}, 14435 {"bits": [23, 23], "name": "IEEE_MODE"}, 14436 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 14437 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, 14438 {"bits": [27, 27], "name": "MEM_ORDERED"}, 14439 {"bits": [28, 28], "name": "FWD_PROGRESS"}, 14440 {"bits": [31, 31], "name": "FP16_OVFL"} 14441 ] 14442 }, 14443 "SPI_SHADER_PGM_RSRC2_ES_VS": { 14444 "fields": [ 14445 {"bits": [0, 0], "name": "SCRATCH_EN"}, 14446 {"bits": [1, 5], "name": "USER_SGPR"}, 14447 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 14448 {"bits": [7, 7], "name": "OC_LDS_EN"}, 14449 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 14450 {"bits": [20, 28], "name": "LDS_SIZE"} 14451 ] 14452 }, 14453 "SPI_SHADER_PGM_RSRC2_GS": { 14454 "fields": [ 14455 {"bits": [0, 0], "name": "SCRATCH_EN"}, 14456 {"bits": [1, 5], "name": "USER_SGPR"}, 14457 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 14458 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 14459 {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"}, 14460 {"bits": [18, 18], "name": "OC_LDS_EN"}, 14461 {"bits": [19, 26], "name": "LDS_SIZE"}, 14462 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, 14463 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} 14464 ] 14465 }, 14466 "SPI_SHADER_PGM_RSRC2_GS_VS": { 14467 "fields": [ 14468 {"bits": [0, 0], "name": "SCRATCH_EN"}, 14469 {"bits": [1, 5], "name": "USER_SGPR"}, 14470 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 14471 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 14472 {"bits": [16, 17], "name": "VGPR_COMP_CNT"}, 14473 {"bits": [18, 18], "name": "OC_LDS_EN"}, 14474 {"bits": [19, 26], "name": "LDS_SIZE"}, 14475 {"bits": [27, 27], "name": "SKIP_USGPR0"}, 14476 {"bits": [28, 28], "name": "USER_SGPR_MSB"} 14477 ] 14478 }, 14479 "SPI_SHADER_PGM_RSRC2_HS": { 14480 "fields": [ 14481 {"bits": [0, 0], "name": "SCRATCH_EN"}, 14482 {"bits": [1, 5], "name": "USER_SGPR"}, 14483 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 14484 {"bits": [7, 7], "name": "OC_LDS_EN"}, 14485 {"bits": [8, 8], "name": "TG_SIZE_EN"}, 14486 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 14487 {"bits": [18, 26], "name": "LDS_SIZE"}, 14488 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, 14489 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} 14490 ] 14491 }, 14492 "SPI_SHADER_PGM_RSRC2_LS_VS": { 14493 "fields": [ 14494 {"bits": [0, 0], "name": "SCRATCH_EN"}, 14495 {"bits": [1, 5], "name": "USER_SGPR"}, 14496 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 14497 {"bits": [7, 15], "name": "LDS_SIZE"}, 14498 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 14499 ] 14500 }, 14501 "SPI_SHADER_PGM_RSRC2_PS": { 14502 "fields": [ 14503 {"bits": [0, 0], "name": "SCRATCH_EN"}, 14504 {"bits": [1, 5], "name": "USER_SGPR"}, 14505 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 14506 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, 14507 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, 14508 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 14509 {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"}, 14510 {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"}, 14511 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, 14512 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} 14513 ] 14514 }, 14515 "SPI_SHADER_PGM_RSRC2_VS": { 14516 "fields": [ 14517 {"bits": [0, 0], "name": "SCRATCH_EN"}, 14518 {"bits": [1, 5], "name": "USER_SGPR"}, 14519 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 14520 {"bits": [7, 7], "name": "OC_LDS_EN"}, 14521 {"bits": [8, 8], "name": "SO_BASE0_EN"}, 14522 {"bits": [9, 9], "name": "SO_BASE1_EN"}, 14523 {"bits": [10, 10], "name": "SO_BASE2_EN"}, 14524 {"bits": [11, 11], "name": "SO_BASE3_EN"}, 14525 {"bits": [12, 12], "name": "SO_EN"}, 14526 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 14527 {"bits": [22, 22], "name": "PC_BASE_EN"}, 14528 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}, 14529 {"bits": [27, 27], "name": "USER_SGPR_MSB"}, 14530 {"bits": [28, 31], "name": "SHARED_VGPR_CNT"} 14531 ] 14532 }, 14533 "SPI_SHADER_PGM_RSRC3_GS": { 14534 "fields": [ 14535 {"bits": [0, 15], "name": "CU_EN"}, 14536 {"bits": [16, 21], "name": "WAVE_LIMIT"}, 14537 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}, 14538 {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"} 14539 ] 14540 }, 14541 "SPI_SHADER_PGM_RSRC3_HS": { 14542 "fields": [ 14543 {"bits": [0, 5], "name": "WAVE_LIMIT"}, 14544 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"}, 14545 {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"}, 14546 {"bits": [16, 31], "name": "CU_EN"} 14547 ] 14548 }, 14549 "SPI_SHADER_PGM_RSRC3_PS": { 14550 "fields": [ 14551 {"bits": [0, 15], "name": "CU_EN"}, 14552 {"bits": [16, 21], "name": "WAVE_LIMIT"}, 14553 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"} 14554 ] 14555 }, 14556 "SPI_SHADER_PGM_RSRC4_GS": { 14557 "fields": [ 14558 {"bits": [0, 15], "name": "CU_EN"}, 14559 {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"} 14560 ] 14561 }, 14562 "SPI_SHADER_PGM_RSRC4_PS": { 14563 "fields": [ 14564 {"bits": [0, 15], "name": "CU_EN"} 14565 ] 14566 }, 14567 "SPI_SHADER_POS_FORMAT": { 14568 "fields": [ 14569 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, 14570 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, 14571 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, 14572 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}, 14573 {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"} 14574 ] 14575 }, 14576 "SPI_SHADER_PREF_PRI_CNTR_CTRL_PS": { 14577 "fields": [ 14578 {"bits": [0, 2], "name": "TOTAL_WAVE_COUNT_HIER_SELECT"}, 14579 {"bits": [3, 5], "name": "PER_TYPE_WAVE_COUNT_HIER_SELECT"}, 14580 {"bits": [6, 6], "name": "GROUP_UPDATE_EN"}, 14581 {"bits": [8, 15], "name": "TOTAL_WAVE_COUNT_COEFFICIENT"}, 14582 {"bits": [16, 23], "name": "PER_TYPE_WAVE_COUNT_COEFFICIENT"} 14583 ] 14584 }, 14585 "SPI_SHADER_REQ_CTRL_PS": { 14586 "fields": [ 14587 {"bits": [0, 0], "name": "SOFT_GROUPING_EN"}, 14588 {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"}, 14589 {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"}, 14590 {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"}, 14591 {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"}, 14592 {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"}, 14593 {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"}, 14594 {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"} 14595 ] 14596 }, 14597 "SPI_SHADER_USER_ACCUM_PS_0": { 14598 "fields": [ 14599 {"bits": [0, 6], "name": "CONTRIBUTION"} 14600 ] 14601 }, 14602 "SPI_SHADER_Z_FORMAT": { 14603 "fields": [ 14604 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} 14605 ] 14606 }, 14607 "SPI_VS_OUT_CONFIG": { 14608 "fields": [ 14609 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, 14610 {"bits": [6, 6], "name": "VS_HALF_PACK"}, 14611 {"bits": [7, 7], "name": "NO_PC_EXPORT"} 14612 ] 14613 }, 14614 "SQC_CACHES": { 14615 "fields": [ 14616 {"bits": [0, 0], "name": "TARGET_INST"}, 14617 {"bits": [1, 1], "name": "TARGET_DATA"}, 14618 {"bits": [2, 2], "name": "INVALIDATE"}, 14619 {"bits": [3, 3], "name": "WRITEBACK"}, 14620 {"bits": [4, 4], "name": "VOL"}, 14621 {"bits": [16, 16], "name": "COMPLETE"}, 14622 {"bits": [17, 18], "name": "L2_WB_POLICY"} 14623 ] 14624 }, 14625 "SQC_WRITEBACK": { 14626 "fields": [ 14627 {"bits": [0, 0], "name": "DWB"}, 14628 {"bits": [1, 1], "name": "DIRTY"} 14629 ] 14630 }, 14631 "SQ_PERFCOUNTER0_SELECT": { 14632 "fields": [ 14633 {"bits": [0, 8], "name": "PERF_SEL"}, 14634 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, 14635 {"bits": [20, 23], "name": "SPM_MODE"}, 14636 {"bits": [28, 31], "name": "PERF_MODE"} 14637 ] 14638 }, 14639 "SQ_PERFCOUNTER_CTRL": { 14640 "fields": [ 14641 {"bits": [0, 0], "name": "PS_EN"}, 14642 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 14643 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 14644 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 14645 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 14646 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 14647 {"bits": [6, 6], "name": "CS_EN"}, 14648 {"bits": [8, 9], "name": "CNTR_RATE"}, 14649 {"bits": [13, 13], "name": "DISABLE_FLUSH"} 14650 ] 14651 }, 14652 "SQ_PERFCOUNTER_CTRL2": { 14653 "fields": [ 14654 {"bits": [0, 0], "name": "FORCE_EN"} 14655 ] 14656 }, 14657 "SQ_THREAD_TRACE_BUF0_SIZE": { 14658 "fields": [ 14659 {"bits": [0, 3], "name": "BASE_HI"}, 14660 {"bits": [8, 29], "name": "SIZE"} 14661 ] 14662 }, 14663 "SQ_THREAD_TRACE_CTRL": { 14664 "fields": [ 14665 {"bits": [0, 1], "name": "MODE"}, 14666 {"bits": [2, 2], "name": "ALL_VMID"}, 14667 {"bits": [3, 3], "name": "CH_PERF_EN"}, 14668 {"bits": [4, 4], "name": "INTERRUPT_EN"}, 14669 {"bits": [5, 5], "name": "DOUBLE_BUFFER"}, 14670 {"bits": [6, 8], "name": "HIWATER"}, 14671 {"bits": [9, 9], "name": "REG_STALL_EN"}, 14672 {"bits": [10, 10], "name": "SPI_STALL_EN"}, 14673 {"bits": [11, 11], "name": "SQ_STALL_EN"}, 14674 {"bits": [12, 12], "name": "REG_DROP_ON_STALL"}, 14675 {"bits": [13, 13], "name": "UTIL_TIMER"}, 14676 {"bits": [14, 15], "name": "WAVESTART_MODE"}, 14677 {"bits": [16, 17], "name": "RT_FREQ"}, 14678 {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"}, 14679 {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"}, 14680 {"bits": [30, 30], "name": "CAPTURE_ALL"}, 14681 {"bits": [31, 31], "name": "DRAW_EVENT_EN"} 14682 ] 14683 }, 14684 "SQ_THREAD_TRACE_MASK": { 14685 "fields": [ 14686 {"bits": [0, 1], "name": "SIMD_SEL"}, 14687 {"bits": [4, 7], "name": "WGP_SEL"}, 14688 {"bits": [9, 9], "name": "SA_SEL"}, 14689 {"bits": [10, 16], "name": "WTYPE_INCLUDE"} 14690 ] 14691 }, 14692 "SQ_THREAD_TRACE_STATUS": { 14693 "fields": [ 14694 {"bits": [0, 11], "name": "FINISH_PENDING"}, 14695 {"bits": [12, 23], "name": "FINISH_DONE"}, 14696 {"bits": [24, 24], "name": "UTC_ERR"}, 14697 {"bits": [25, 25], "name": "BUSY"}, 14698 {"bits": [26, 26], "name": "EVENT_CNTR_OVERFLOW"}, 14699 {"bits": [27, 27], "name": "EVENT_CNTR_STALL"} 14700 ] 14701 }, 14702 "SQ_THREAD_TRACE_TOKEN_MASK": { 14703 "fields": [ 14704 {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"}, 14705 {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"}, 14706 {"bits": [24, 25], "name": "INST_EXCLUDE"}, 14707 {"bits": [31, 31], "name": "REG_DETAIL_ALL"} 14708 ] 14709 }, 14710 "SQ_THREAD_TRACE_WPTR": { 14711 "fields": [ 14712 {"bits": [0, 28], "name": "OFFSET"}, 14713 {"bits": [31, 31], "name": "BUFFER_ID"} 14714 ] 14715 }, 14716 "SQ_WAVE_GPR_ALLOC": { 14717 "fields": [ 14718 {"bits": [0, 7], "name": "VGPR_BASE"}, 14719 {"bits": [8, 15], "name": "VGPR_SIZE"}, 14720 {"bits": [16, 23], "name": "SGPR_BASE"}, 14721 {"bits": [24, 27], "name": "SGPR_SIZE"} 14722 ] 14723 }, 14724 "SQ_WAVE_HW_ID1": { 14725 "fields": [ 14726 {"bits": [0, 4], "name": "WAVE_ID"}, 14727 {"bits": [8, 9], "name": "SIMD_ID"}, 14728 {"bits": [10, 13], "name": "WGP_ID"}, 14729 {"bits": [16, 16], "name": "SA_ID"}, 14730 {"bits": [18, 19], "name": "SE_ID"} 14731 ] 14732 }, 14733 "SQ_WAVE_HW_ID2": { 14734 "fields": [ 14735 {"bits": [0, 3], "name": "QUEUE_ID"}, 14736 {"bits": [4, 5], "name": "PIPE_ID"}, 14737 {"bits": [8, 9], "name": "ME_ID"}, 14738 {"bits": [12, 14], "name": "STATE_ID"}, 14739 {"bits": [16, 20], "name": "WG_ID"}, 14740 {"bits": [24, 27], "name": "VM_ID"}, 14741 {"bits": [29, 30], "name": "COMPAT_LEVEL"} 14742 ] 14743 }, 14744 "SQ_WAVE_HW_ID_LEGACY": { 14745 "fields": [ 14746 {"bits": [0, 3], "name": "WAVE_ID"}, 14747 {"bits": [4, 5], "name": "SIMD_ID"}, 14748 {"bits": [6, 7], "name": "PIPE_ID"}, 14749 {"bits": [8, 11], "name": "CU_ID"}, 14750 {"bits": [12, 12], "name": "SH_ID"}, 14751 {"bits": [13, 14], "name": "SE_ID"}, 14752 {"bits": [15, 15], "name": "WAVE_ID_MSB"}, 14753 {"bits": [16, 19], "name": "TG_ID"}, 14754 {"bits": [20, 23], "name": "VM_ID"}, 14755 {"bits": [24, 26], "name": "QUEUE_ID"}, 14756 {"bits": [27, 29], "name": "STATE_ID"}, 14757 {"bits": [30, 31], "name": "ME_ID"} 14758 ] 14759 }, 14760 "SQ_WAVE_IB_DBG1": { 14761 "fields": [ 14762 {"bits": [0, 0], "name": "XNACK_ERROR"}, 14763 {"bits": [1, 1], "name": "XNACK"}, 14764 {"bits": [2, 2], "name": "TA_NEED_RESET"}, 14765 {"bits": [3, 3], "name": "XNACK_OVERRIDE"}, 14766 {"bits": [4, 9], "name": "XCNT"}, 14767 {"bits": [11, 16], "name": "QCNT"}, 14768 {"bits": [18, 23], "name": "RCNT"}, 14769 {"bits": [24, 24], "name": "WAVE_IDLE"}, 14770 {"bits": [25, 31], "name": "MISC_CNT"} 14771 ] 14772 }, 14773 "SQ_WAVE_IB_STS": { 14774 "fields": [ 14775 {"bits": [0, 3], "name": "VM_CNT"}, 14776 {"bits": [4, 6], "name": "EXP_CNT"}, 14777 {"bits": [7, 7], "name": "LGKM_CNT_BIT4"}, 14778 {"bits": [8, 11], "name": "LGKM_CNT"}, 14779 {"bits": [12, 14], "name": "VALU_CNT"}, 14780 {"bits": [15, 15], "name": "FIRST_REPLAY"}, 14781 {"bits": [16, 21], "name": "RCNT"}, 14782 {"bits": [22, 23], "name": "VM_CNT_HI"}, 14783 {"bits": [24, 24], "name": "LGKM_CNT_BIT5"}, 14784 {"bits": [25, 25], "name": "REPLAY_W64H"}, 14785 {"bits": [26, 31], "name": "VS_CNT"} 14786 ] 14787 }, 14788 "SQ_WAVE_IB_STS2": { 14789 "fields": [ 14790 {"bits": [0, 1], "name": "INST_PREFETCH"}, 14791 {"bits": [7, 7], "name": "RESOURCE_OVERRIDE"}, 14792 {"bits": [8, 9], "name": "MEM_ORDER"}, 14793 {"bits": [10, 10], "name": "FWD_PROGRESS"}, 14794 {"bits": [11, 11], "name": "WAVE64"}, 14795 {"bits": [12, 12], "name": "WAVE64HI"}, 14796 {"bits": [13, 13], "name": "SUBV_LOOP"} 14797 ] 14798 }, 14799 "SQ_WAVE_LDS_ALLOC": { 14800 "fields": [ 14801 {"bits": [0, 8], "name": "LDS_BASE"}, 14802 {"bits": [12, 20], "name": "LDS_SIZE"}, 14803 {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"} 14804 ] 14805 }, 14806 "SQ_WAVE_MODE": { 14807 "fields": [ 14808 {"bits": [0, 3], "name": "FP_ROUND"}, 14809 {"bits": [4, 7], "name": "FP_DENORM"}, 14810 {"bits": [8, 8], "name": "DX10_CLAMP"}, 14811 {"bits": [9, 9], "name": "IEEE"}, 14812 {"bits": [10, 10], "name": "LOD_CLAMPED"}, 14813 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 14814 {"bits": [23, 23], "name": "FP16_OVFL"}, 14815 {"bits": [27, 27], "name": "DISABLE_PERF"}, 14816 {"bits": [28, 28], "name": "VSKIP"}, 14817 {"bits": [29, 31], "name": "CSP"} 14818 ] 14819 }, 14820 "SQ_WAVE_PC_HI": { 14821 "fields": [ 14822 {"bits": [0, 15], "name": "PC_HI"} 14823 ] 14824 }, 14825 "SQ_WAVE_POPS_PACKER": { 14826 "fields": [ 14827 {"bits": [0, 0], "name": "POPS_EN"}, 14828 {"bits": [1, 2], "name": "POPS_PACKER_ID"} 14829 ] 14830 }, 14831 "SQ_WAVE_SCHED_MODE": { 14832 "fields": [ 14833 {"bits": [0, 1], "name": "DEP_MODE"} 14834 ] 14835 }, 14836 "SQ_WAVE_STATUS": { 14837 "fields": [ 14838 {"bits": [0, 0], "name": "SCC"}, 14839 {"bits": [1, 2], "name": "SPI_PRIO"}, 14840 {"bits": [3, 4], "name": "USER_PRIO"}, 14841 {"bits": [5, 5], "name": "PRIV"}, 14842 {"bits": [6, 6], "name": "TRAP_EN"}, 14843 {"bits": [7, 7], "name": "TTRACE_EN"}, 14844 {"bits": [8, 8], "name": "EXPORT_RDY"}, 14845 {"bits": [9, 9], "name": "EXECZ"}, 14846 {"bits": [10, 10], "name": "VCCZ"}, 14847 {"bits": [11, 11], "name": "IN_TG"}, 14848 {"bits": [12, 12], "name": "IN_BARRIER"}, 14849 {"bits": [13, 13], "name": "HALT"}, 14850 {"bits": [14, 14], "name": "TRAP"}, 14851 {"bits": [15, 15], "name": "TTRACE_SIMD_EN"}, 14852 {"bits": [16, 16], "name": "VALID"}, 14853 {"bits": [17, 17], "name": "ECC_ERR"}, 14854 {"bits": [18, 18], "name": "SKIP_EXPORT"}, 14855 {"bits": [19, 19], "name": "PERF_EN"}, 14856 {"bits": [23, 23], "name": "FATAL_HALT"}, 14857 {"bits": [27, 27], "name": "MUST_EXPORT"} 14858 ] 14859 }, 14860 "SQ_WAVE_TRAPSTS": { 14861 "fields": [ 14862 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, 14863 {"bits": [10, 10], "name": "SAVECTX"}, 14864 {"bits": [11, 11], "name": "ILLEGAL_INST"}, 14865 {"bits": [12, 14], "name": "EXCP_HI"}, 14866 {"bits": [15, 15], "name": "BUFFER_OOB"}, 14867 {"bits": [16, 19], "name": "EXCP_CYCLE"}, 14868 {"bits": [20, 23], "name": "EXCP_GROUP_MASK"}, 14869 {"bits": [24, 24], "name": "EXCP_WAVE64HI"}, 14870 {"bits": [28, 28], "name": "XNACK_ERROR"}, 14871 {"bits": [29, 31], "name": "DP_RATE"} 14872 ] 14873 }, 14874 "SQ_WAVE_VGPR_OFFSET": { 14875 "fields": [ 14876 {"bits": [0, 5], "name": "SRC0"}, 14877 {"bits": [6, 11], "name": "SRC1"}, 14878 {"bits": [12, 17], "name": "SRC2"}, 14879 {"bits": [18, 23], "name": "DST"} 14880 ] 14881 }, 14882 "SX_BLEND_OPT_CONTROL": { 14883 "fields": [ 14884 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"}, 14885 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"}, 14886 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"}, 14887 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"}, 14888 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"}, 14889 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"}, 14890 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"}, 14891 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"}, 14892 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"}, 14893 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"}, 14894 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"}, 14895 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"}, 14896 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"}, 14897 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"}, 14898 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"}, 14899 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"}, 14900 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"} 14901 ] 14902 }, 14903 "SX_BLEND_OPT_EPSILON": { 14904 "fields": [ 14905 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, 14906 {"bits": [4, 7], "name": "MRT1_EPSILON"}, 14907 {"bits": [8, 11], "name": "MRT2_EPSILON"}, 14908 {"bits": [12, 15], "name": "MRT3_EPSILON"}, 14909 {"bits": [16, 19], "name": "MRT4_EPSILON"}, 14910 {"bits": [20, 23], "name": "MRT5_EPSILON"}, 14911 {"bits": [24, 27], "name": "MRT6_EPSILON"}, 14912 {"bits": [28, 31], "name": "MRT7_EPSILON"} 14913 ] 14914 }, 14915 "SX_MRT0_BLEND_OPT": { 14916 "fields": [ 14917 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, 14918 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, 14919 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, 14920 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, 14921 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, 14922 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} 14923 ] 14924 }, 14925 "SX_PERFCOUNTER0_SELECT": { 14926 "fields": [ 14927 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT"}, 14928 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT1"}, 14929 {"bits": [20, 23], "name": "CNTR_MODE"} 14930 ] 14931 }, 14932 "SX_PERFCOUNTER0_SELECT1": { 14933 "fields": [ 14934 {"bits": [0, 9], "name": "PERFCOUNTER_SELECT2"}, 14935 {"bits": [10, 19], "name": "PERFCOUNTER_SELECT3"} 14936 ] 14937 }, 14938 "SX_PS_DOWNCONVERT": { 14939 "fields": [ 14940 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, 14941 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, 14942 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, 14943 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, 14944 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, 14945 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, 14946 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, 14947 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} 14948 ] 14949 }, 14950 "TA_BC_BASE_ADDR_HI": { 14951 "fields": [ 14952 {"bits": [0, 7], "name": "ADDRESS"} 14953 ] 14954 }, 14955 "TA_PERFCOUNTER0_SELECT": { 14956 "fields": [ 14957 {"bits": [0, 7], "name": "PERF_SEL"}, 14958 {"bits": [10, 17], "name": "PERF_SEL1"}, 14959 {"bits": [20, 23], "name": "CNTR_MODE"}, 14960 {"bits": [24, 27], "name": "PERF_MODE1"}, 14961 {"bits": [28, 31], "name": "PERF_MODE"} 14962 ] 14963 }, 14964 "TA_PERFCOUNTER0_SELECT1": { 14965 "fields": [ 14966 {"bits": [0, 7], "name": "PERF_SEL2"}, 14967 {"bits": [10, 17], "name": "PERF_SEL3"}, 14968 {"bits": [24, 27], "name": "PERF_MODE3"}, 14969 {"bits": [28, 31], "name": "PERF_MODE2"} 14970 ] 14971 }, 14972 "TA_PERFCOUNTER1_SELECT": { 14973 "fields": [ 14974 {"bits": [0, 7], "name": "PERF_SEL"}, 14975 {"bits": [20, 23], "name": "CNTR_MODE"}, 14976 {"bits": [28, 31], "name": "PERF_MODE"} 14977 ] 14978 }, 14979 "TCP_PERFCOUNTER2_SELECT": { 14980 "fields": [ 14981 {"bits": [0, 9], "name": "PERF_SEL"}, 14982 {"bits": [20, 23], "name": "CNTR_MODE"}, 14983 {"bits": [28, 31], "name": "PERF_MODE"} 14984 ] 14985 }, 14986 "UTCL1_PERFCOUNTER0_SELECT": { 14987 "fields": [ 14988 {"bits": [0, 9], "name": "PERF_SEL"}, 14989 {"bits": [28, 31], "name": "COUNTER_MODE"} 14990 ] 14991 }, 14992 "VGT_DMA_BASE_HI": { 14993 "fields": [ 14994 {"bits": [0, 15], "name": "BASE_ADDR"} 14995 ] 14996 }, 14997 "VGT_DMA_INDEX_TYPE": { 14998 "fields": [ 14999 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, 15000 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, 15001 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, 15002 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, 15003 {"bits": [8, 8], "name": "ATC"}, 15004 {"bits": [9, 9], "name": "NOT_EOP"}, 15005 {"bits": [10, 10], "name": "REQ_PATH"}, 15006 {"bits": [11, 13], "name": "MTYPE"} 15007 ] 15008 }, 15009 "VGT_DRAW_INITIATOR": { 15010 "fields": [ 15011 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, 15012 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, 15013 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, 15014 {"bits": [5, 5], "name": "NOT_EOP"}, 15015 {"bits": [6, 6], "name": "USE_OPAQUE"}, 15016 {"bits": [7, 7], "name": "UNROLLED_INST"}, 15017 {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"}, 15018 {"bits": [29, 31], "name": "REG_RT_INDEX"} 15019 ] 15020 }, 15021 "VGT_DRAW_PAYLOAD_CNTL": { 15022 "fields": [ 15023 {"bits": [0, 0], "name": "OBJPRIM_ID_EN"}, 15024 {"bits": [1, 1], "name": "EN_REG_RT_INDEX"}, 15025 {"bits": [2, 2], "name": "OBJECT_ID_INST_EN"}, 15026 {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"}, 15027 {"bits": [4, 4], "name": "EN_DRAW_VP"} 15028 ] 15029 }, 15030 "VGT_ESGS_RING_ITEMSIZE": { 15031 "fields": [ 15032 {"bits": [0, 14], "name": "ITEMSIZE"} 15033 ] 15034 }, 15035 "VGT_ES_PER_GS": { 15036 "fields": [ 15037 {"bits": [0, 10], "name": "ES_PER_GS"} 15038 ] 15039 }, 15040 "VGT_EVENT_ADDRESS_REG": { 15041 "fields": [ 15042 {"bits": [0, 27], "name": "ADDRESS_LOW"} 15043 ] 15044 }, 15045 "VGT_EVENT_INITIATOR": { 15046 "fields": [ 15047 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, 15048 {"bits": [10, 26], "name": "ADDRESS_HI"}, 15049 {"bits": [27, 27], "name": "EXTENDED_EVENT"} 15050 ] 15051 }, 15052 "VGT_GROUP_DECR": { 15053 "fields": [ 15054 {"bits": [0, 3], "name": "DECR"} 15055 ] 15056 }, 15057 "VGT_GROUP_FIRST_DECR": { 15058 "fields": [ 15059 {"bits": [0, 3], "name": "FIRST_DECR"} 15060 ] 15061 }, 15062 "VGT_GROUP_PRIM_TYPE": { 15063 "fields": [ 15064 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, 15065 {"bits": [14, 14], "name": "RETAIN_ORDER"}, 15066 {"bits": [15, 15], "name": "RETAIN_QUADS"}, 15067 {"bits": [16, 18], "name": "PRIM_ORDER"} 15068 ] 15069 }, 15070 "VGT_GROUP_VECT_0_CNTL": { 15071 "fields": [ 15072 {"bits": [0, 0], "name": "COMP_X_EN"}, 15073 {"bits": [1, 1], "name": "COMP_Y_EN"}, 15074 {"bits": [2, 2], "name": "COMP_Z_EN"}, 15075 {"bits": [3, 3], "name": "COMP_W_EN"}, 15076 {"bits": [8, 15], "name": "STRIDE"}, 15077 {"bits": [16, 23], "name": "SHIFT"} 15078 ] 15079 }, 15080 "VGT_GROUP_VECT_0_FMT_CNTL": { 15081 "fields": [ 15082 {"bits": [0, 3], "name": "X_CONV"}, 15083 {"bits": [4, 7], "name": "X_OFFSET"}, 15084 {"bits": [8, 11], "name": "Y_CONV"}, 15085 {"bits": [12, 15], "name": "Y_OFFSET"}, 15086 {"bits": [16, 19], "name": "Z_CONV"}, 15087 {"bits": [20, 23], "name": "Z_OFFSET"}, 15088 {"bits": [24, 27], "name": "W_CONV"}, 15089 {"bits": [28, 31], "name": "W_OFFSET"} 15090 ] 15091 }, 15092 "VGT_GSVS_RING_OFFSET_1": { 15093 "fields": [ 15094 {"bits": [0, 14], "name": "OFFSET"} 15095 ] 15096 }, 15097 "VGT_GS_INSTANCE_CNT": { 15098 "fields": [ 15099 {"bits": [0, 0], "name": "ENABLE"}, 15100 {"bits": [2, 8], "name": "CNT"}, 15101 {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"} 15102 ] 15103 }, 15104 "VGT_GS_MAX_VERT_OUT": { 15105 "fields": [ 15106 {"bits": [0, 10], "name": "MAX_VERT_OUT"} 15107 ] 15108 }, 15109 "VGT_GS_MODE": { 15110 "fields": [ 15111 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, 15112 {"bits": [3, 3], "name": "RESERVED_0"}, 15113 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, 15114 {"bits": [6, 10], "name": "RESERVED_1"}, 15115 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, 15116 {"bits": [12, 12], "name": "RESERVED_2"}, 15117 {"bits": [13, 13], "name": "ES_PASSTHRU"}, 15118 {"bits": [14, 14], "name": "COMPUTE_MODE"}, 15119 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"}, 15120 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"}, 15121 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, 15122 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, 15123 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, 15124 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, 15125 {"bits": [21, 22], "name": "ONCHIP"} 15126 ] 15127 }, 15128 "VGT_GS_ONCHIP_CNTL": { 15129 "fields": [ 15130 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"}, 15131 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}, 15132 {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"} 15133 ] 15134 }, 15135 "VGT_GS_OUT_PRIM_TYPE": { 15136 "fields": [ 15137 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, 15138 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, 15139 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, 15140 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, 15141 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} 15142 ] 15143 }, 15144 "VGT_GS_PER_ES": { 15145 "fields": [ 15146 {"bits": [0, 10], "name": "GS_PER_ES"} 15147 ] 15148 }, 15149 "VGT_GS_PER_VS": { 15150 "fields": [ 15151 {"bits": [0, 3], "name": "GS_PER_VS"} 15152 ] 15153 }, 15154 "VGT_HOS_CNTL": { 15155 "fields": [ 15156 {"bits": [0, 1], "name": "TESS_MODE"} 15157 ] 15158 }, 15159 "VGT_HOS_REUSE_DEPTH": { 15160 "fields": [ 15161 {"bits": [0, 7], "name": "REUSE_DEPTH"} 15162 ] 15163 }, 15164 "VGT_HS_OFFCHIP_PARAM_UMD": { 15165 "fields": [ 15166 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"}, 15167 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"} 15168 ] 15169 }, 15170 "VGT_LS_HS_CONFIG": { 15171 "fields": [ 15172 {"bits": [0, 7], "name": "NUM_PATCHES"}, 15173 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, 15174 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} 15175 ] 15176 }, 15177 "VGT_MULTI_PRIM_IB_RESET_EN": { 15178 "fields": [ 15179 {"bits": [0, 0], "name": "RESET_EN"}, 15180 {"bits": [1, 1], "name": "MATCH_ALL_BITS"} 15181 ] 15182 }, 15183 "VGT_OUTPUT_PATH_CNTL": { 15184 "fields": [ 15185 {"bits": [0, 2], "name": "PATH_SELECT"} 15186 ] 15187 }, 15188 "VGT_OUT_DEALLOC_CNTL": { 15189 "fields": [ 15190 {"bits": [0, 6], "name": "DEALLOC_DIST"} 15191 ] 15192 }, 15193 "VGT_PRIMITIVEID_EN": { 15194 "fields": [ 15195 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, 15196 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}, 15197 {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"} 15198 ] 15199 }, 15200 "VGT_PRIMITIVE_TYPE": { 15201 "fields": [ 15202 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} 15203 ] 15204 }, 15205 "VGT_REUSE_OFF": { 15206 "fields": [ 15207 {"bits": [0, 0], "name": "REUSE_OFF"} 15208 ] 15209 }, 15210 "VGT_SHADER_STAGES_EN": { 15211 "fields": [ 15212 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 15213 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 15214 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 15215 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 15216 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 15217 {"bits": [8, 8], "name": "DYNAMIC_HS"}, 15218 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"}, 15219 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"}, 15220 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"}, 15221 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}, 15222 {"bits": [13, 13], "name": "PRIMGEN_EN"}, 15223 {"bits": [14, 14], "name": "ORDERED_ID_MODE"}, 15224 {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"}, 15225 {"bits": [19, 20], "name": "GS_FAST_LAUNCH"}, 15226 {"bits": [21, 21], "name": "HS_W32_EN"}, 15227 {"bits": [22, 22], "name": "GS_W32_EN"}, 15228 {"bits": [23, 23], "name": "VS_W32_EN"}, 15229 {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"}, 15230 {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"} 15231 ] 15232 }, 15233 "VGT_STRMOUT_BUFFER_CONFIG": { 15234 "fields": [ 15235 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, 15236 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, 15237 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, 15238 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} 15239 ] 15240 }, 15241 "VGT_STRMOUT_CONFIG": { 15242 "fields": [ 15243 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, 15244 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, 15245 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, 15246 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, 15247 {"bits": [4, 6], "name": "RAST_STREAM"}, 15248 {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"}, 15249 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, 15250 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} 15251 ] 15252 }, 15253 "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": { 15254 "fields": [ 15255 {"bits": [0, 8], "name": "VERTEX_STRIDE"} 15256 ] 15257 }, 15258 "VGT_STRMOUT_VTX_STRIDE_0": { 15259 "fields": [ 15260 {"bits": [0, 9], "name": "STRIDE"} 15261 ] 15262 }, 15263 "VGT_TESS_DISTRIBUTION": { 15264 "fields": [ 15265 {"bits": [0, 7], "name": "ACCUM_ISOLINE"}, 15266 {"bits": [8, 15], "name": "ACCUM_TRI"}, 15267 {"bits": [16, 23], "name": "ACCUM_QUAD"}, 15268 {"bits": [24, 28], "name": "DONUT_SPLIT"}, 15269 {"bits": [29, 31], "name": "TRAP_SPLIT"} 15270 ] 15271 }, 15272 "VGT_TF_PARAM": { 15273 "fields": [ 15274 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, 15275 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, 15276 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, 15277 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, 15278 {"bits": [9, 9], "name": "DEPRECATED"}, 15279 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, 15280 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, 15281 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, 15282 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}, 15283 {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"}, 15284 {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"}, 15285 {"bits": [23, 25], "name": "MTYPE"} 15286 ] 15287 }, 15288 "VGT_TF_RING_SIZE_UMD": { 15289 "fields": [ 15290 {"bits": [0, 15], "name": "SIZE"} 15291 ] 15292 }, 15293 "VGT_VERTEX_REUSE_BLOCK_CNTL": { 15294 "fields": [ 15295 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} 15296 ] 15297 }, 15298 "VGT_VTX_CNT_EN": { 15299 "fields": [ 15300 {"bits": [0, 0], "name": "VTX_CNT_EN"} 15301 ] 15302 } 15303 } 15304} 15305