Lines Matching +full:uniphier +full:- +full:system +full:- +full:cache
1 # SPDX-License-Identifier: GPL-2.0
131 The ARM series is a line of low-power-consumption RISC chip designs
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
244 Patch phys-to-virt and virt-to-phys translation functions at
246 kernel in system memory.
248 This can only be used with non-XIP MMU kernels where the base
280 location of main memory in your system.
291 menu "System Type"
294 bool "MMU-based Paged Memory Management Support"
297 Select if you want MMU-based virtualised addressing space
309 # The "ARM system type" choice list is ordered alphabetically by option
313 prompt "ARM system type"
336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
349 bool "EBSA-110"
358 from Digital. It has limited hardware on-board, including an
363 bool "EP93xx-based"
391 bool "IOP32x-based"
404 bool "IXP4xx-based"
440 bool "PXA2xx/PXA3xx-based"
477 On the Acorn Risc-PC, Linux can support the internal IDE disk and
478 CD-ROM interface, serial and parallel port, and the floppy drive.
481 bool "SA1100-based"
580 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
609 # This is sorted alphabetically by mach-* pathname. However, plat-*
611 # plat- suffix) or along side the corresponding mach-* source.
613 source "arch/arm/mach-actions/Kconfig"
615 source "arch/arm/mach-alpine/Kconfig"
617 source "arch/arm/mach-artpec/Kconfig"
619 source "arch/arm/mach-asm9260/Kconfig"
621 source "arch/arm/mach-aspeed/Kconfig"
623 source "arch/arm/mach-at91/Kconfig"
625 source "arch/arm/mach-axxia/Kconfig"
627 source "arch/arm/mach-bcm/Kconfig"
629 source "arch/arm/mach-berlin/Kconfig"
631 source "arch/arm/mach-clps711x/Kconfig"
633 source "arch/arm/mach-cns3xxx/Kconfig"
635 source "arch/arm/mach-davinci/Kconfig"
637 source "arch/arm/mach-digicolor/Kconfig"
639 source "arch/arm/mach-dove/Kconfig"
641 source "arch/arm/mach-ep93xx/Kconfig"
643 source "arch/arm/mach-exynos/Kconfig"
645 source "arch/arm/mach-footbridge/Kconfig"
647 source "arch/arm/mach-gemini/Kconfig"
649 source "arch/arm/mach-highbank/Kconfig"
651 source "arch/arm/mach-hisi/Kconfig"
653 source "arch/arm/mach-imx/Kconfig"
655 source "arch/arm/mach-integrator/Kconfig"
657 source "arch/arm/mach-iop32x/Kconfig"
659 source "arch/arm/mach-ixp4xx/Kconfig"
661 source "arch/arm/mach-keystone/Kconfig"
663 source "arch/arm/mach-lpc32xx/Kconfig"
665 source "arch/arm/mach-mediatek/Kconfig"
667 source "arch/arm/mach-meson/Kconfig"
669 source "arch/arm/mach-milbeaut/Kconfig"
671 source "arch/arm/mach-mmp/Kconfig"
673 source "arch/arm/mach-moxart/Kconfig"
675 source "arch/arm/mach-mstar/Kconfig"
677 source "arch/arm/mach-mv78xx0/Kconfig"
679 source "arch/arm/mach-mvebu/Kconfig"
681 source "arch/arm/mach-mxs/Kconfig"
683 source "arch/arm/mach-nomadik/Kconfig"
685 source "arch/arm/mach-npcm/Kconfig"
687 source "arch/arm/mach-nspire/Kconfig"
689 source "arch/arm/plat-omap/Kconfig"
691 source "arch/arm/mach-omap1/Kconfig"
693 source "arch/arm/mach-omap2/Kconfig"
695 source "arch/arm/mach-orion5x/Kconfig"
697 source "arch/arm/mach-oxnas/Kconfig"
699 source "arch/arm/mach-picoxcell/Kconfig"
701 source "arch/arm/mach-prima2/Kconfig"
703 source "arch/arm/mach-pxa/Kconfig"
704 source "arch/arm/plat-pxa/Kconfig"
706 source "arch/arm/mach-qcom/Kconfig"
708 source "arch/arm/mach-rda/Kconfig"
710 source "arch/arm/mach-realtek/Kconfig"
712 source "arch/arm/mach-realview/Kconfig"
714 source "arch/arm/mach-rockchip/Kconfig"
716 source "arch/arm/mach-s3c/Kconfig"
718 source "arch/arm/mach-s5pv210/Kconfig"
720 source "arch/arm/mach-sa1100/Kconfig"
722 source "arch/arm/mach-shmobile/Kconfig"
724 source "arch/arm/mach-socfpga/Kconfig"
726 source "arch/arm/mach-spear/Kconfig"
728 source "arch/arm/mach-sti/Kconfig"
730 source "arch/arm/mach-stm32/Kconfig"
732 source "arch/arm/mach-sunxi/Kconfig"
734 source "arch/arm/mach-tango/Kconfig"
736 source "arch/arm/mach-tegra/Kconfig"
738 source "arch/arm/mach-u300/Kconfig"
740 source "arch/arm/mach-uniphier/Kconfig"
742 source "arch/arm/mach-ux500/Kconfig"
744 source "arch/arm/mach-versatile/Kconfig"
746 source "arch/arm/mach-vexpress/Kconfig"
748 source "arch/arm/mach-vt8500/Kconfig"
750 source "arch/arm/mach-zx/Kconfig"
752 source "arch/arm/mach-zynq/Kconfig"
754 # ARMv7-M architecture
771 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
780 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
781 with a range of available cores like Cortex-M3/M4/M7.
822 source "arch/arm/Kconfig-nommu"
840 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
843 Executing a SWP instruction to read-only memory does not set bit 11
849 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
852 Invalidation of the Instruction Cache operation can
861 This option enables the workaround for the 430973 Cortex-A8
864 same virtual address, whether due to self-modifying code or virtual
865 to physical address re-mapping, Cortex-A8 does not recover from the
866 stale interworking branch prediction. This results in Cortex-A8
869 and also flushes the branch target cache at every context switch.
871 available in non-secure mode.
878 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
880 possible for a hazard condition intended for a cache line to instead
881 be incorrectly associated with a different cache line. This false
885 register may not be available in non-secure mode.
888 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
892 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
893 erratum. Any asynchronous access to the L2 cache may encounter a
894 situation in which recent store transactions to the L2 cache are lost
896 workaround disables the write-allocate mode for the L2 cache via the
898 may not be available in non-secure mode.
905 This option enables the workaround for the 742230 Cortex-A9
909 the diagnostic register of the Cortex-A9 which causes the DMB
918 This option enables the workaround for the 742231 Cortex-A9
920 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
921 accessing some data located in the same cache line, may get corrupted
925 register of the Cortex-A9 which reduces the linefill issuing
933 This option enables the workaround for the 643719 Cortex-A9 (prior to
936 corrects this value, ensuring cache maintenance operations which use
943 This option enables the workaround for the 720789 Cortex-A9 (prior to
947 invalidated are not, resulting in an incoherency in the system page
956 This option enables the workaround for the 743622 Cortex-A9
958 optimisation in the Cortex-A9 Store Buffer may lead to data
960 register of the Cortex-A9 which disables the Store Buffer
970 This option enables the workaround for the 751472 Cortex-A9 (prior
974 potentially leading to corrupted entries in the cache or TLB.
980 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
983 can populate the micro-TLB with a stale entry which may be hit with
991 This option enables the workaround for the 754327 Cortex-A9 (prior to
999 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1003 r0p2 erratum (possible cache data corruption with
1004 hit-under-miss enabled). It sets the undocumented bit 31 in
1006 register, thus disabling hit-under-miss without putting the
1011 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1015 affecting Cortex-A9 MPCore with two or more processors (all
1017 cache line maintenance operation by MVA targeting an Inner
1020 system. This workaround adds a DSB instruction before the
1021 relevant cache maintenance functions and sets a specific bit
1025 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1028 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1029 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1032 an abort may occur on cache maintenance.
1035 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1038 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1048 This option enables the workaround for the 773022 Cortex-A15
1058 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1060 - Cortex-A12 852422: Execution of a sequence of instructions might
1062 any Cortex-A12 cores yet.
1071 This option enables the workaround for the 821420 Cortex-A12
1075 deadlock when the VMOV instructions are issued out-of-order.
1081 This option enables the workaround for the 825619 Cortex-A12
1084 and Device/Strongly-Ordered loads and stores might cause deadlock
1090 This option enables the workaround for the 857271 Cortex-A12
1098 This option enables the workaround for the 852421 Cortex-A17
1108 - Cortex-A17 852423: Execution of a sequence of instructions might
1110 any Cortex-A17 cores yet.
1111 This is identical to Cortex-A12 erratum 852422. It is a separate
1119 This option enables the workaround for the 857272 Cortex-A17 erratum.
1121 This is identical to Cortex-A12 erratum 857271. It is a separate
1135 name of a bus system, i.e. the way the CPU talks to the other stuff
1137 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1156 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1159 The v7 ARM states that all cache and branch predictor maintenance
1162 However, because of this erratum, an L2 set/way cache maintenance
1163 operation can overtake an L1 set/way cache maintenance operation.
1164 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1174 This option should be selected by machines which have an SMP-
1177 The only effect of this option is to make the SMP-related
1181 bool "Symmetric Multi-Processing"
1189 a system with only one CPU, say N. If you have a system with more
1192 If you say N here, the kernel will run on uni- and multiprocessor
1198 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1199 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1200 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1209 SMP kernels contain instructions which fail on non-SMP processors.
1223 topology of an ARM System.
1226 bool "Multi-core scheduler support"
1229 Multi-core scheduler support improves the CPU scheduler's decision
1230 making when dealing with multi-core CPU chips at a cost of slightly
1259 bool "Multi-Cluster Power Management"
1263 for (multi-)cluster based systems, such as big.LITTLE based
1281 system architecture.
1290 and a cluster of A7's in a big.LITTLE system.
1339 int "Maximum number of CPUs (2-32)"
1345 bool "Support for hot-pluggable CPUs"
1350 can be controlled through /sys/devices/system/cpu.
1357 Say Y here if you want Linux to communicate with system firmware
1358 implementing the PSCI specification for CPU-centric power
1360 0022A ("Power State Coordination Interface System Software on
1380 Maximum number of GPIOs in the system.
1428 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1434 Thumb-2 mode.
1484 The seccomp filter system will not be available when this is
1528 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1536 user-space 2nd level page tables to reside in high memory.
1539 bool "Enable use of CPU domains to implement privileged no-access"
1545 use-after-free bugs becoming an exploitable privilege escalation
1549 CPUs with low-vector mappings use a best-efforts implementation.
1582 Disabling this is usually safe for small single-platform
1609 address divisible by 4. On 32-bit ARM processors, these non-aligned
1612 correct operation of some network protocols. With an IP-only
1621 cores where a 8-word STM instruction give significantly higher
1628 However, if the CPU data cache is using a write-allocate mode,
1677 the entire duration that the system is up.
1733 The physical address at which the ROM-able zImage is to be
1735 ROM-able zImage formats normally set this to a suitable
1745 for the ROM-able zImage which must be available while the
1748 Platforms which normally make use of ROM-able zImage formats
1800 Uses the command-line options passed by the boot loader instead of
1807 The command-line arguments provided by the boot loader will be
1818 architectures, you should supply some command-line options at build
1830 Uses the command-line options passed by the boot loader. If
1837 The command-line arguments provided by the boot loader will be
1846 command-line options your boot loader passes to the kernel.
1850 bool "Kernel Execute-In-Place from ROM"
1853 Execute-In-Place allows the kernel to run from non-volatile storage
1856 to RAM. Read-write sections, such as the data section and stack,
1891 bool "Kexec system call (EXPERIMENTAL)"
1896 kexec is a system call that implements the ability to shutdown your
1898 but it is independent of the system firmware. And like a reboot
1918 loaded in the main kernel with kexec-tools into a specially
1923 For more details see Documentation/admin-guide/kdump/kdump.rst
1930 will be determined at run-time by masking the current IP with
1947 by UEFI firmware (such as non-volatile variables, realtime
1962 continue to boot on existing non-UEFI platforms.
1968 to be enabled much earlier than we do on ARM, which is non-trivial.
1991 your machine has an FPA or floating point co-processor podule.
2000 Say Y to include 80-bit support in the kernel floating-point
2001 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2002 Note that gcc does not generate 80-bit operations by default,
2015 It is very simple, and approximately 3-6 times faster than NWFPE.
2023 bool "VFP-format floating point maths"
2029 Please see <file:Documentation/arm/vfp/release-notes.rst> for