Lines Matching full:p15
139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
484 mrc p15, 0, r1, c0, c1, 1 @ read ID_PFR1 register
486 mrrcne p15, 1, r3, r1, c14 @ read CNTVCT
756 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
791 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
792 mcr p15, 0, r0, c6, c7, 1
795 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
796 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
797 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
800 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
801 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
804 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
805 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
806 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
807 mrc p15, 0, r0, c1, c0, 0 @ read control reg
812 mcr p15, 0, r0, c1, c0, 0 @ write control reg
815 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
816 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
821 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
824 mcr p15, 0, r0, c2, c0, 0 @ cache on
825 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
828 mcr p15, 0, r0, c5, c0, 0 @ access permission
831 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
836 mrc p15, 0, r0, c1, c0, 0 @ read control reg
841 mcr p15, 0, r0, c1, c0, 0 @ write control reg
844 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
901 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
904 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
910 mcr p15, 7, r0, c15, c0, 0
919 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
920 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
921 mrc p15, 0, r0, c1, c0, 0 @ read control reg
927 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
935 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
940 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
942 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
944 mrc p15, 0, r0, c1, c0, 0 @ read control reg
953 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
958 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
959 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
960 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
962 mcr p15, 0, r0, c7, c5, 4 @ ISB
963 mcr p15, 0, r0, c1, c0, 0 @ load control register
964 mrc p15, 0, r0, c1, c0, 0 @ and read it back
966 mcr p15, 0, r0, c7, c5, 4 @ ISB
974 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
975 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
976 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
977 mrc p15, 0, r0, c1, c0, 0 @ read control reg
981 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
990 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
991 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
994 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
995 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
1017 mrc p15, 0, r9, c0, c0 @ get processor ID
1224 mrc p15, 0, r0, c1, c0
1226 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1228 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1229 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1230 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1234 mrc p15, 0, r0, c1, c0
1236 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1238 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1243 mrc p15, 0, r0, c1, c0
1245 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1247 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1248 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1253 mrc p15, 0, r0, c1, c0
1259 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1262 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1264 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1265 mcr p15, 0, r0, c7, c10, 4 @ DSB
1266 mcr p15, 0, r0, c7, c5, 4 @ ISB
1291 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1294 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1301 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1302 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1309 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1310 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1311 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1317 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1318 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1319 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1320 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1327 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1331 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1341 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1345 mcr p15, 0, r10, c7, c10, 4 @ DSB
1346 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1347 mcr p15, 0, r10, c7, c10, 4 @ DSB
1348 mcr p15, 0, r10, c7, c5, 4 @ ISB
1354 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
1356 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1357 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1365 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1389 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1390 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1391 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1399 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1546 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1548 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1576 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1589 mcr p15, 4, r1, c1, c0, 0
1591 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1608 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR