Lines Matching full:r0
79 mov r0, \val
84 mov r0, \val
252 mov r0, #0x17 @ angel_SWIreason_EnterSVC
256 safe_svcmode_maskall r0
304 mov r0, pc
305 cmp r0, r4
306 ldrcc r0, .Lheadroom
307 addcc r0, r0, pc
308 cmpcc r4, r0
312 restart: adr_l r0, LC1
313 ldr sp, [r0]
314 ldr r6, [r0, #4]
315 add sp, sp, r0
316 add r6, r6, r0
390 mov r0, r8
400 cmp r0, #1
401 sub r0, r4, #TEXT_OFFSET
402 bic r0, r0, #1
403 add r0, r0, #0x100
451 stmfd sp!, {r0-r3, ip, lr}
455 mov r0, r4
457 lsr r0, r0, #20
458 lsl r0, r0, #20
460 lsr r0, r0, #21
461 lsl r0, r0, #21
463 add r0, r0, #0x1000
464 ldr r1, [r0]
471 moveq r8, r0
488 adr_l r0, __kaslr_offset @ pass &__kaslr_offset in r0
494 cmp r0, #0
495 addne r4, r4, r0 @ add offset to base address
504 ldmfd sp!, {r0-r3, ip, lr}
548 mrs r0, spsr
549 and r0, r0, #MODE_MASK
550 cmp r0, #HYP_MODE
558 adr_l r0, __hyp_stub_vectors
559 sub r0, r0, r5
560 add r0, r0, r10
585 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
587 stmdb r9!, {r0 - r3, r10 - r12, lr}
593 mov r0, r9 @ start of relocated zImage
597 badr r0, restart
598 add r0, r0, r6
599 mov pc, r0
602 adr r0, LC0
603 ldmia r0, {r1, r2, r3, r11, r12}
604 sub r0, r0, r1 @ calculate the delta offset
608 * r0 = delta
619 orrs r1, r0, r5
622 add r11, r11, r0
623 add r12, r12, r0
631 add r2, r2, r0
632 add r3, r3, r0
639 add r1, r1, r0 @ This fixes up C references
660 addlo r1, r1, r0 @ table. This fixes up the
666 not_relocated: mov r0, #0
667 1: str r0, [r2], #4 @ clear bss
668 str r0, [r2], #4
669 str r0, [r2], #4
670 str r0, [r2], #4
690 mov r0, r4
698 mov r0, r4 @ start of inflated image
699 add r1, r1, r0 @ end of inflated image
704 mrs r0, spsr @ Get saved CPU boot mode
705 and r0, r0, #MODE_MASK
706 cmp r0, #HYP_MODE @ if not booted in HYP mode...
709 adr_l r0, __hyp_reentry_vectors
740 params: ldr r0, =0x10000100 @ params_phys for RPC
777 * r0, r1, r2, r3, r9, r10, r12 corrupted
790 mov r0, #0x3f @ 4G, the whole
791 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
792 mcr p15, 0, r0, c6, c7, 1
794 mov r0, #0x80 @ PR7
795 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
796 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
797 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
799 mov r0, #0xc000
800 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
801 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
803 mov r0, #0
804 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
805 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
806 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
807 mrc p15, 0, r0, c1, c0, 0 @ read control reg
809 orr r0, r0, #0x002d @ .... .... ..1. 11.1
810 orr r0, r0, #0x1000 @ ...1 .... .... ....
812 mcr p15, 0, r0, c1, c0, 0 @ write control reg
814 mov r0, #0
815 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
816 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
820 mov r0, #0x3f @ 4G, the whole
821 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
823 mov r0, #0x80 @ PR7
824 mcr p15, 0, r0, c2, c0, 0 @ cache on
825 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
827 mov r0, #0xc000
828 mcr p15, 0, r0, c5, c0, 0 @ access permission
830 mov r0, #0
831 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
836 mrc p15, 0, r0, c1, c0, 0 @ read control reg
838 orr r0, r0, #0x000d @ .... .... .... 11.1
840 mov r0, #0
841 mcr p15, 0, r0, c1, c0, 0 @ write control reg
844 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
860 mov r0, r3
861 mov r9, r0, lsr #18
872 str r1, [r0], #4 @ 1:1 mapping
874 teq r0, r2
889 add r0, r3, r2, lsl #2
891 0: str r1, [r0], #4
893 cmp r0, r9
901 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
902 bic r0, r0, #2 @ A (no unaligned access fault)
903 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
904 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
909 mov r0, #4 @ put dcache in WT mode
910 mcr p15, 7, r0, c15, c0, 0
918 mov r0, #0
919 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
920 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
921 mrc p15, 0, r0, c1, c0, 0 @ read control reg
922 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
923 orr r0, r0, #0x0030
924 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
926 mov r0, #0
927 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
939 mov r0, #0
940 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
942 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
944 mrc p15, 0, r0, c1, c0, 0 @ read control reg
945 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
946 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
947 orr r0, r0, #0x003c @ write buffer
948 bic r0, r0, #2 @ A (no unaligned access fault)
949 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
952 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
954 orrne r0, r0, #1 @ MMU enabled
962 mcr p15, 0, r0, c7, c5, 4 @ ISB
963 mcr p15, 0, r0, c1, c0, 0 @ load control register
964 mrc p15, 0, r0, c1, c0, 0 @ and read it back
965 mov r0, #0
966 mcr p15, 0, r0, c7, c5, 4 @ ISB
973 mov r0, #0
974 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
975 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
976 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
977 mrc p15, 0, r0, c1, c0, 0 @ read control reg
978 orr r0, r0, #0x1000 @ I-cache enable
980 mov r0, #0
981 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
987 orr r0, r0, #0x000d @ Write buffer, mmu
994 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
995 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
996 sub pc, lr, r0, lsr #32 @ properly flush pipeline
1215 * r0, r1, r2, r3, r9, r12 corrupted
1224 mrc p15, 0, r0, c1, c0
1225 bic r0, r0, #0x000d
1226 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1227 mov r0, #0
1228 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1229 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1230 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1234 mrc p15, 0, r0, c1, c0
1235 bic r0, r0, #0x000d
1236 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1237 mov r0, #0
1238 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1243 mrc p15, 0, r0, c1, c0
1244 bic r0, r0, #0x000d
1245 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1246 mov r0, #0
1247 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1248 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1253 mrc p15, 0, r0, c1, c0
1255 bic r0, r0, #0x0005
1257 bic r0, r0, #0x0004
1259 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1260 mov r0, #0
1262 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1264 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1265 mcr p15, 0, r0, c7, c10, 4 @ DSB
1266 mcr p15, 0, r0, c7, c5, 4 @ ISB
1273 * r0 = start address
1336 bic r0, r0, r2 @ round down start to line size
1339 0: cmp r0, r11 @ finished?
1341 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1342 add r0, r0, r1
1356 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1357 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1412 @ phex corrupts {r0, r1, r2, r3}
1417 movmi r0, r3
1419 and r2, r0, #15
1420 mov r0, r0, lsr #4
1427 @ puts corrupts {r0, r1, r2, r3}
1429 1: ldrb r2, [r0], #1
1439 teq r0, #0
1442 @ putc corrupts {r0, r1, r2, r3}
1444 mov r2, r0
1445 loadsp r3, r1, r0
1446 mov r0, #0
1449 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1450 memdump: mov r12, r0
1453 2: mov r0, r11, lsl #2
1454 add r0, r0, r12
1457 mov r0, #':'
1459 1: mov r0, #' '
1461 ldr r0, [r12, r11, lsl #2]
1464 and r0, r11, #7
1465 teq r0, #3
1466 moveq r0, #' '
1468 and r0, r11, #7
1470 teq r0, #7
1472 mov r0, #'\n'
1499 mov r0, #0 @ must be 0
1529 eor r0, r0, r4
1531 lsrs r0, r0, #1
1532 eorcs r0, r0, r3
1546 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1547 bic r0, r0, #0x5 @ disable MMU and caches
1548 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1553 mov r4, r0 @ preserve image base
1556 adr_l r0, call_cache_fn
1570 mrs r0, cpsr @ get the current mode
1571 msr spsr_cxsf, r0 @ record boot mode
1572 and r0, r0, #MODE_MASK @ are we running in HYP mode?
1573 cmp r0, #HYP_MODE
1590 adr r0, __hyp_reentry_vectors
1591 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1603 msr spsr_cxsf, r0 @ record boot mode
1608 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1609 tst r0, #0x1 @ MMU enabled?
1613 mov r0, r8 @ DT start
1617 adr r0, 0f @ switch to our stack
1618 ldr sp, [r0]
1619 add sp, sp, r0