Lines Matching +full:1 +full:c00
48 #address-cells = <1>;
49 #size-cells = <1>;
87 #address-cells = <1>;
101 timer@1 {
103 reg = <1>;
117 #address-cells = <1>;
147 #address-cells = <1>;
168 timer5: timer@40000c00 {
175 timers5: timers@40000c00 {
176 #address-cells = <1>;
206 #address-cells = <1>;
230 #address-cells = <1>;
246 #address-cells = <1>;
267 timers13: timers@40001c00 {
298 clocks = <&rcc 1 CLK_RTC>;
299 assigned-clocks = <&rcc 1 CLK_RTC>;
300 assigned-clock-parents = <&rcc 1 CLK_LSE>;
302 interrupts = <17 1>;
311 clocks = <&rcc 1 CLK_USART2>;
319 clocks = <&rcc 1 CLK_USART3>;
323 usart4: serial@40004c00 {
327 clocks = <&rcc 1 CLK_UART4>;
335 clocks = <&rcc 1 CLK_UART5>;
345 clocks = <&rcc 1 CLK_I2C1>;
346 #address-cells = <1>;
357 clocks = <&rcc 1 CLK_I2C2>;
358 #address-cells = <1>;
363 i2c3: i2c@40005c00 {
369 clocks = <&rcc 1 CLK_I2C3>;
370 #address-cells = <1>;
381 clocks = <&rcc 1 CLK_I2C4>;
382 #address-cells = <1>;
387 cec: cec@40006c00 {
391 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
400 clocks = <&rcc 1 CLK_UART7>;
404 usart8: serial@40007c00 {
408 clocks = <&rcc 1 CLK_UART8>;
413 #address-cells = <1>;
435 #address-cells = <1>;
460 clocks = <&rcc 1 CLK_USART1>;
468 clocks = <&rcc 1 CLK_USART6>;
472 sdio2: sdio2@40011c00 {
483 sdio1: sdio1@40012c00 {
499 exti: interrupt-controller@40013c00 {
504 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
508 #address-cells = <1>;
570 #reset-cells = <1>;
576 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
637 clocks = <&rcc 1 0>;