Lines Matching refs:x3
41 uaccess_ttbr0_enable x2, x3, x4
46 dcache_line_size x2, x3
47 sub x3, x2, #1
48 bic x4, x0, x3
61 invalidate_icache_by_line x0, x1, x2, x3, 9f
87 uaccess_ttbr0_enable x2, x3, x4
89 invalidate_icache_by_line x0, x1, x2, x3, 2f
109 dcache_by_line_op civac, sy, x0, x1, x2, x3
127 dcache_by_line_op cvau, ish, x0, x1, x2, x3
151 dcache_line_size x2, x3
152 sub x3, x2, #1
153 tst x1, x3 // end cache line aligned?
154 bic x1, x1, x3
157 1: tst x0, x3 // start cache line aligned?
158 bic x0, x0, x3
189 dcache_by_line_op cvac, sy, x0, x1, x2, x3
207 dcache_by_line_op cvap, sy, x0, x1, x2, x3
220 dcache_by_line_op civac, sy, x0, x1, x2, x3