Lines Matching +full:64 +full:bit

40  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
41  * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
46  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
131 GCR_ACCESSOR_RO(64, 0x000, config)
139 GCR_ACCESSOR_RW(64, 0x008, base)
167 #define CM_GCR_ERR_CONTROL_L2_ECC_EN		BIT(1)
168 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT	BIT(0)
171 GCR_ACCESSOR_RW(64, 0x040, error_mask)
174 GCR_ACCESSOR_RW(64, 0x048, error_cause)
180 GCR_ACCESSOR_RW(64, 0x050, error_addr)
183 GCR_ACCESSOR_RW(64, 0x058, error_mult)
187 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
189 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN		BIT(0)
192 GCR_ACCESSOR_RW(64, 0x080, gic_base)
194 #define CM_GCR_GIC_BASE_GICEN			BIT(0)
197 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
199 #define CM_GCR_CPC_BASE_CPCEN			BIT(0)
202 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
203 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
204 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
205 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
209 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
210 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
211 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
212 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
215 #define CM_GCR_REGn_MASK_CCAOVREN		BIT(4)
216 #define CM_GCR_REGn_MASK_DROPL2			BIT(2)
225 #define CM_GCR_GIC_STATUS_EX			BIT(0)
229 #define CM_GCR_CPC_STATUS_EX			BIT(0)
233 #define CM_GCR_L2_CONFIG_BYPASS			BIT(20)
245 #define CM_GCR_L2_PFT_CONTROL_PFTEN		BIT(8)
250 #define CM_GCR_L2_PFT_CONTROL_B_CEN		BIT(8)
255 #define CM_GCR_L2SM_COP_PRESENT			BIT(31)
262 #define CM_GCR_L2SM_COP_RUNNING			BIT(5)
276 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
281 GCR_ACCESSOR_RW(64, 0x680, bev_base)
289 #define CM3_GCR_Cx_COHERENCE_COHEN		BIT(0)
299 #define CM_GCR_Cx_OTHER_CLUSTER_EN		BIT(31)		/* CM >= 3.5 */
300 #define CM_GCR_Cx_OTHER_GIC_EN			BIT(30)		/* CM >= 3.5 */
322 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET	BIT(31)
323 #define CM_GCR_Cx_RESET_EXT_BASE_UEB		BIT(30)
326 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT	BIT(0)