54 #define SATA_CTL		0x0
55 #define SATA_STATUS		0x1 /* Status Reg */
56 #define SATA_INT		0x2 /* Interrupt Reg */
57 #define SATA_INT_MASK		0x3 /* Interrupt Mask Reg */
58 #define SATA_BIU_TIMEOUT	0x4
59 #define AXIWRSPERRLOG		0x5
60 #define AXIRDSPERRLOG		0x6
61 #define BiuTimeoutLow		0x7
62 #define BiuTimeoutHi		0x8
63 #define BiuSlvErLow		0x9
64 #define BiuSlvErHi		0xa
65 #define IO_CONFIG_SWAP_DIS	0xb
66 #define CR_REG_TIMER		0xc
67 #define CORE_ID			0xd
68 #define AXI_SLAVE_OPT1		0xe
69 #define PHY_MEM_ACCESS		0xf
70 #define PHY0_CNTRL		0x10
71 #define PHY0_STAT		0x11
72 #define PHY0_RX_ALIGN		0x12
73 #define PHY0_RX_EQ_LO		0x13
74 #define PHY0_RX_EQ_HI		0x14
75 #define PHY0_BIST_LOOP		0x15
76 #define PHY1_CNTRL		0x16
77 #define PHY1_STAT		0x17
78 #define PHY1_RX_ALIGN		0x18
79 #define PHY1_RX_EQ_LO		0x19
80 #define PHY1_RX_EQ_HI		0x1a
81 #define PHY1_BIST_LOOP		0x1b
82 #define RdExBase		0x1c
83 #define RdExLimit		0x1d
84 #define CacheAllocBase		0x1e
85 #define CacheAllocLimit		0x1f
86 #define BiuSlaveCmdGstNum	0x20
89 #define SATA_RST_N		BIT(0)  /* Active low reset sata_core phy */
119 #define M_CACTIVE		BIT(0)  /* m_cactive, not used */
135 #define CR_TIME_SCALE		(0x1000 << 0)
138 #define RXCDRCALFOSC0		0x0065
139 #define CALDUTY			0x006e
140 #define RXDPIF			0x8065
141 #define PPMDRIFTMAX_HI		0x80A4
148 		(nlm_get_sata_pcibase(node) + 0x100)
150 /* SATA PHY config for register block 1 0x0065 .. 0x006e */
152 	0xC9, 0xC9, 0x07, 0x07, 0x18, 0x18, 0x01, 0x01, 0x22, 0x00
155 /* SATA PHY config for register block 2 0x8065 .. 0x80A4 */
157 	0xAA, 0x00, 0x4C, 0xC9, 0xC9, 0x07, 0x07, 0x18,
158 	0x18, 0x05, 0x0C, 0x10, 0x00, 0x10, 0x00, 0xFF,
159 	0xCF, 0xF7, 0xE1, 0xF5, 0xFD, 0xFD, 0xFF, 0xFF,
160 	0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5, 0xFD, 0xFD,
161 	0xF5, 0xF5, 0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5,
162 	0xFD, 0xFD, 0xF5, 0xF5, 0xFF, 0xFF, 0xFF, 0xF5,
163 	0x3F, 0x00, 0x32, 0x00, 0x03, 0x01, 0x05, 0x05,
164 	0x04, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x04,
167 const int sata_phy_debug = 0;	/* set to verify PHY writes */
197 		(0 << 31) | (physel << 24) | (0 << 16) | addr);  in read_phy_reg()
200 	return (val >> 16) & 0xff;  in read_phy_reg()
208 	for (port = 0; port < 2; port++) {  in config_sata_phy()
209 		for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++)  in config_sata_phy()
212 		for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++)  in config_sata_phy()
216 		write_phy_reg(regbase, 0x800F, port, 0x1f);  in config_sata_phy()
218 		val = read_phy_reg(regbase, 0x0029, port);  in config_sata_phy()
219 		write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1));  in config_sata_phy()
221 		val = read_phy_reg(regbase, 0x0056, port);  in config_sata_phy()
222 		write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3));  in config_sata_phy()
224 		val = read_phy_reg(regbase, 0x0018, port);  in config_sata_phy()
225 		write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0));  in config_sata_phy()
234 	pr_info("PHY read addr = 0x%x physel = %d data = 0x%x %s\n",  in check_phy_register()
242 	for (port = 0; port < 2; port++) {  in verify_sata_phy_config()
243 		for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++)  in verify_sata_phy_config()
247 		for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++)  in verify_sata_phy_config()
319 	} while (--n > 0);  in nlm_sata_firmware_init()
338 		return 0;  in nlm_ahci_init()
339 	for (node = 0; node < NLM_NR_NODES; node++)  in nlm_ahci_init()
342 	return 0;  in nlm_ahci_init()
359 	dev->resource[5] = dev->resource[0];  in nlm_sata_fixup_bar()
360 	memset(&dev->resource[0], 0, sizeof(dev->resource[0]));  in nlm_sata_fixup_bar()
378 	sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1);  in nlm_sata_fixup_final()