Lines Matching +full:0 +full:x11000
13 #define EP_OFFSET 0x10008
15 #define PARMAREA 0x10400
16 #define EARLY_SCCB_OFFSET 0x11000
17 #define HEAD_END 0x12000
25 #define MACHINE_FLAG_VM BIT(0)
44 #define LPP_PID_MASK _AC(0xffffffff, UL)
48 #define STARTUP_NORMAL_OFFSET 0x10000
49 #define STARTUP_KDUMP_OFFSET 0x10010
53 #define IPL_DEVICE_OFFSET 0x10400
54 #define INITRD_START_OFFSET 0x10408
55 #define INITRD_SIZE_OFFSET 0x10410
56 #define OLDMEM_BASE_OFFSET 0x10418
57 #define OLDMEM_SIZE_OFFSET 0x10420
58 #define KERNEL_VERSION_OFFSET 0x10428
59 #define COMMAND_LINE_OFFSET 0x10480
74 unsigned long ipl_device; /* 0x10400 */
75 unsigned long initrd_start; /* 0x10408 */
76 unsigned long initrd_size; /* 0x10410 */
77 unsigned long oldmem_base; /* 0x10418 */
78 unsigned long oldmem_size; /* 0x10420 */
79 unsigned long kernel_version; /* 0x10428 */
80 char pad1[0x10480 - 0x10430]; /* 0x10430 - 0x10480 */
81 char command_line[ARCH_COMMAND_LINE_SIZE]; /* 0x10480 */
85 #define ZLIB_DFLTCC_DISABLED 0
126 #define CONSOLE_IS_UNDEFINED (console_mode == 0)
132 #define SET_CONSOLE_SCLP do { console_mode = 1; } while (0)
133 #define SET_CONSOLE_3215 do { console_mode = 2; } while (0)
134 #define SET_CONSOLE_3270 do { console_mode = 3; } while (0)
135 #define SET_CONSOLE_VT220 do { console_mode = 4; } while (0)
136 #define SET_CONSOLE_HVC do { console_mode = 5; } while (0)
143 #define pfault_fini() do { } while (0)
169 BUILD_BUG_ON(addr > 0xfff); in gen_lpswe()
170 return 0xb2b20000 | addr; in gen_lpswe()