1 // SPDX-License-Identifier: GPL-2.0+
3  * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
19 #include "clk-mpll.h"
20 #include "clk-pll.h"
21 #include "clk-regmap.h"
22 #include "clk-cpu-dyndiv.h"
23 #include "vid-pll-div.h"
24 #include "meson-eeclk.h"
25 #include "g12a.h"
308 		 * b) CCF has a clock hand-off mechanism to make the sure the
344 		 * b) CCF has a clock hand-off mechanism to make the sure the
388 		/* This sub-tree is used a parking clock */
470 		/* This sub-tree is used a parking clock */
617 		/* This sub-tree is used a parking clock */
654 		/* This sub-tree is used a parking clock */
956 		 *    \- cpu_clk_dyn  in g12a_cpu_clk_postmux_notifier_cb()
957 		 *          \- cpu_clk_postmux0  in g12a_cpu_clk_postmux_notifier_cb()
958 		 *                \- cpu_clk_muxX_div  in g12a_cpu_clk_postmux_notifier_cb()
959 		 *                      \- cpu_clk_premux0  in g12a_cpu_clk_postmux_notifier_cb()
960 		 *				\- fclk_div3 or fclk_div2  in g12a_cpu_clk_postmux_notifier_cb()
962 		 *                \- cpu_clk_premux0  in g12a_cpu_clk_postmux_notifier_cb()
963 		 *			\- fclk_div3 or fclk_div2  in g12a_cpu_clk_postmux_notifier_cb()
967 		clk_hw_set_parent(nb_data->cpu_clk_premux1,  in g12a_cpu_clk_postmux_notifier_cb()
968 				  nb_data->xtal);  in g12a_cpu_clk_postmux_notifier_cb()
971 		clk_hw_set_parent(nb_data->cpu_clk_postmux1,  in g12a_cpu_clk_postmux_notifier_cb()
972 				  nb_data->cpu_clk_premux1);  in g12a_cpu_clk_postmux_notifier_cb()
975 		clk_hw_set_parent(nb_data->cpu_clk_dyn,  in g12a_cpu_clk_postmux_notifier_cb()
976 				  nb_data->cpu_clk_postmux1);  in g12a_cpu_clk_postmux_notifier_cb()
981 		 *    \- cpu_clk_dyn  in g12a_cpu_clk_postmux_notifier_cb()
982 		 *          \- cpu_clk_postmux1  in g12a_cpu_clk_postmux_notifier_cb()
983 		 *                \- cpu_clk_premux1  in g12a_cpu_clk_postmux_notifier_cb()
984 		 *                      \- xtal  in g12a_cpu_clk_postmux_notifier_cb()
999 		clk_hw_set_parent(nb_data->cpu_clk_dyn,  in g12a_cpu_clk_postmux_notifier_cb()
1000 				  nb_data->cpu_clk_postmux0);  in g12a_cpu_clk_postmux_notifier_cb()
1005 		 *    \- cpu_clk_dyn  in g12a_cpu_clk_postmux_notifier_cb()
1006 		 *          \- cpu_clk_postmux0  in g12a_cpu_clk_postmux_notifier_cb()
1007 		 *                \- cpu_clk_muxX_div  in g12a_cpu_clk_postmux_notifier_cb()
1008 		 *                      \- cpu_clk_premux0  in g12a_cpu_clk_postmux_notifier_cb()
1009 		 *				\- fclk_div3 or fclk_div2  in g12a_cpu_clk_postmux_notifier_cb()
1011 		 *                \- cpu_clk_premux0  in g12a_cpu_clk_postmux_notifier_cb()
1012 		 *			\- fclk_div3 or fclk_div2  in g12a_cpu_clk_postmux_notifier_cb()
1059 		 *    \- sys_pll  in g12a_sys_pll_notifier_cb()
1060 		 *          \- sys_pll_dco  in g12a_sys_pll_notifier_cb()
1064 		clk_hw_set_parent(nb_data->cpu_clk,  in g12a_sys_pll_notifier_cb()
1065 				  nb_data->cpu_clk_dyn);  in g12a_sys_pll_notifier_cb()
1070 		 *    \- cpu_clk_dyn  in g12a_sys_pll_notifier_cb()
1071 		 *          \- cpu_clk_dynX  in g12a_sys_pll_notifier_cb()
1072 		 *                \- cpu_clk_dynX_sel  in g12a_sys_pll_notifier_cb()
1073 		 *		     \- cpu_clk_dynX_div  in g12a_sys_pll_notifier_cb()
1074 		 *                      \- xtal/fclk_div2/fclk_div3  in g12a_sys_pll_notifier_cb()
1075 		 *                   \- xtal/fclk_div2/fclk_div3  in g12a_sys_pll_notifier_cb()
1089 		clk_hw_set_parent(nb_data->cpu_clk,  in g12a_sys_pll_notifier_cb()
1090 				  nb_data->sys_pll);  in g12a_sys_pll_notifier_cb()
1096 		 *    \- sys_pll  in g12a_sys_pll_notifier_cb()
1097 		 *          \- sys_pll_dco  in g12a_sys_pll_notifier_cb()
1309 			 * G12A and G12B have different cpu_clks (with
1315 			.index = -1,
1828  * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
3715  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
3716  * muxed by a glitch-free switch. The CCF can manage this glitch-free
3717  * mux because it does top-to-bottom updates the each clock tree and
3851 		.name = "mali",
5176 		dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n");  in meson_g12a_dvfs_setup_common()
5185 		dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n");  in meson_g12a_dvfs_setup_common()
5211 		dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");  in meson_g12b_dvfs_setup()
5221 		dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n");  in meson_g12b_dvfs_setup()
5234 		dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n");  in meson_g12b_dvfs_setup()
5243 		dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n");  in meson_g12b_dvfs_setup()
5252 		dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n");  in meson_g12b_dvfs_setup()
5262 		dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");  in meson_g12b_dvfs_setup()
5285 		dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");  in meson_g12a_dvfs_setup()
5294 		dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");  in meson_g12a_dvfs_setup()
5312 	eeclkc_data = of_device_get_match_data(&pdev->dev);  in meson_g12a_probe()
5314 		return -EINVAL;  in meson_g12a_probe()
5323 	if (g12a_data->dvfs_setup)  in meson_g12a_probe()
5324 		return g12a_data->dvfs_setup(pdev);  in meson_g12a_probe()
5360 		.compatible = "amlogic,g12a-clkc",
5364 		.compatible = "amlogic,g12b-clkc",
5368 		.compatible = "amlogic,sm1-clkc",
5377 		.name	= "g12a-clkc",