Lines Matching +full:aiu +full:- +full:gxl
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include "clk-regmap.h"
14 #include "clk-pll.h"
15 #include "clk-mpll.h"
16 #include "meson-eeclk.h"
17 #include "vid-pll-div.h"
228 * On gxl, there is a register shift due to
542 * GXL and GXBB have different gp0_pll_dco (with
548 .index = -1,
615 * b) CCF has a clock hand-off mechanism to make the sure the
783 * GXL and GXBB have different SDM_EN registers. We
788 .index = -1,
998 * muxed by a glitch-free switch. The CCF can manage this glitch-free
999 * mux because it does top-to-bottom updates the each clock tree and
1279 { .name = "cts_slow_oscin", .index = -1 },
1793 * GXL and GXBB have different hdmi_plls (with
1799 .index = -1,
1810 * GXL and GXBB have different hdmi_plls (with
1815 { .name = "hdmi_pll", .index = -1 },
2718 /* AIU gates */
3556 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3557 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3564 .name = "gxbb-clkc",