Lines Matching full:div6

20 #include "clk-div6.h"
68 	 * DIV6 clocks require the divisor field to be non-zero when stopping  in cpg_div6_clock_disable()
146 	pr_err("%s: %s DIV6 clock set to invalid parent %u\n",  in cpg_div6_clock_get_parent()
188 		 * TODO: This does not yet support DIV6 clocks with multiple  in cpg_div6_clock_notifier_call()
190 		 * Fortunately so far such DIV6 clocks are found only on  in cpg_div6_clock_notifier_call()
205  * cpg_div6_register - Register a DIV6 clock
206  * @name: Name of the DIV6 clock
207  * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
209  * @reg: Mapped register used to control the DIV6 clock
252 		pr_err("%s: invalid number of parents for DIV6 clock %s\n",  in cpg_div6_register()
303 		pr_err("%s: no parent found for %pOFn DIV6 clock\n",  in cpg_div6_clock_init()
315 		pr_err("%s: failed to map %pOFn DIV6 clock register\n",  in cpg_div6_clock_init()
328 		pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",  in cpg_div6_clock_init()
343 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);