39 #define WARN_DEBUG(x)	do { } while (0)
56 	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
57 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
61 	0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62 	0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
70 	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
71 	0x990, 0x994, 0x998, 0x99C,
75 	0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
76 	0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
85 	0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
86 	0x424, 0x428, 0x42C,
94 	0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
95 	0x920, 0x924, 0x928, 0x92C,
99 	0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
100 	0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
104 #define RMSTPCR(i)	(smstpcr[i] - 0x20)
107 #define MMSTPCR(i)	(smstpcr[i] + 0x20)
112 	0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
113 	0x960, 0x964, 0x968, 0x96C,
117 	0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
118 	0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
224 		return 0;  in cpg_mstp_clock_endisable()
226 	for (i = 1000; i > 0; --i) {  in cpg_mstp_clock_endisable()
238 	return 0;  in cpg_mstp_clock_endisable()
283 	switch (clkspec->args[0]) {  in cpg_mssr_clk_src_twocell_get()
303 		if (range_check < 0 || idx >= priv->num_mod_clks) {  in cpg_mssr_clk_src_twocell_get()
312 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);  in cpg_mssr_clk_src_twocell_get()
321 			clkspec->args[0], clkspec->args[1], clk,  in cpg_mssr_clk_src_twocell_get()
362 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;  in cpg_mssr_register_core_clk()
370 							parent_name, 0,  in cpg_mssr_register_core_clk()
376 		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,  in cpg_mssr_register_core_clk()
448 	for (i = 0; i < info->num_crit_mod_clks; i++)  in cpg_mssr_register_mod_clk()
488 	switch (clkspec->args[0]) {  in cpg_mssr_is_pm_clk()
490 		for (i = 0; i < pd->num_core_pm_clks; i++)  in cpg_mssr_is_pm_clk()
509 	int i = 0;  in cpg_mssr_attach_dev()
526 	return 0;  in cpg_mssr_attach_dev()
543 	return 0;  in cpg_mssr_attach_dev()
565 	size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);  in cpg_mssr_add_clk_domain()
584 	return 0;  in cpg_mssr_add_clk_domain()
610 	return 0;  in cpg_mssr_reset()
623 	return 0;  in cpg_mssr_assert()
637 	return 0;  in cpg_mssr_deassert()
662 	unsigned int unpacked = reset_spec->args[0];  in cpg_mssr_reset_xlate()
686 	return 0;  in cpg_mssr_reset_controller_register()
850 		return 0;  in cpg_mssr_suspend_noirq()
853 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_suspend_noirq()
864 	return 0;  in cpg_mssr_suspend_noirq()
875 		return 0;  in cpg_mssr_resume_noirq()
881 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_resume_noirq()
909 		for (i = 1000; i > 0; --i) {  in cpg_mssr_resume_noirq()
917 			dev_warn(dev, "Failed to enable %s%u[0x%x]\n",  in cpg_mssr_resume_noirq()
922 	return 0;  in cpg_mssr_resume_noirq()
957 	priv->base = of_iomap(np, 0);  in cpg_mssr_common_init()
986 	for (i = 0; i < nclks; i++)  in cpg_mssr_common_init()
993 	return 0;  in cpg_mssr_common_init()
1013 	for (i = 0; i < info->num_early_core_clks; i++)  in cpg_mssr_early_init()
1017 	for (i = 0; i < info->num_early_mod_clks; i++)  in cpg_mssr_early_init()
1044 	for (i = 0; i < info->num_core_clks; i++)  in cpg_mssr_probe()
1047 	for (i = 0; i < info->num_mod_clks; i++)  in cpg_mssr_probe()
1063 		return 0;  in cpg_mssr_probe()
1069 	return 0;  in cpg_mssr_probe()
1094 	for (i = 0; i < num_core_clks; i++)  in cpg_core_nullify_range()
1106 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)  in mssr_mod_nullify()
1120 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)  in mssr_mod_reparent()