Lines Matching full:cmt
3 * SuperH Timer Support - CMT
35 * The CMT comes in 5 different identified flavours, depending not only on the
52 * registers block address. Some CMT instances have a subset of channels
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
91 struct sh_cmt_device *cmt; member
241 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
243 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
249 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
251 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
256 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); in sh_cmt_read_cmcsr()
261 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); in sh_cmt_write_cmcsr()
266 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); in sh_cmt_read_cmcnt()
271 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); in sh_cmt_write_cmcnt()
276 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); in sh_cmt_write_cmcor()
284 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
292 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
306 raw_spin_lock_irqsave(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
315 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
322 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_enable()
323 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); in sh_cmt_enable()
326 ret = clk_enable(ch->cmt->clk); in sh_cmt_enable()
328 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", in sh_cmt_enable()
337 if (ch->cmt->info->width == 16) { in sh_cmt_enable()
368 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", in sh_cmt_enable()
379 clk_disable(ch->cmt->clk); in sh_cmt_enable()
390 /* disable interrupts in CMT block */ in sh_cmt_disable()
394 clk_disable(ch->cmt->clk); in sh_cmt_disable()
396 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); in sh_cmt_disable()
397 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_disable()
487 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", in sh_cmt_clock_event_program_verify()
496 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", in __sh_cmt_set_next()
518 ch->cmt->info->clear_bits); in sh_cmt_interrupt()
575 if (ch->cmt->num_channels == 1 && in sh_cmt_start()
614 if (ch->cmt->num_channels == 1) { in sh_cmt_clocksource_read()
667 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); in sh_cmt_clocksource_suspend()
677 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); in sh_cmt_clocksource_resume()
693 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); in sh_cmt_register_clocksource()
696 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", in sh_cmt_register_clocksource()
699 clocksource_register_hz(cs, ch->cmt->rate); in sh_cmt_register_clocksource()
713 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); in sh_cmt_clock_event_start()
735 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", in sh_cmt_clock_event_set_state()
769 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); in sh_cmt_clock_event_suspend()
770 clk_unprepare(ch->cmt->clk); in sh_cmt_clock_event_suspend()
777 clk_prepare(ch->cmt->clk); in sh_cmt_clock_event_resume()
778 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); in sh_cmt_clock_event_resume()
788 irq = platform_get_irq(ch->cmt->pdev, ch->index); in sh_cmt_register_clockevent()
794 dev_name(&ch->cmt->pdev->dev), ch); in sh_cmt_register_clockevent()
796 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", in sh_cmt_register_clockevent()
815 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); in sh_cmt_register_clockevent()
821 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", in sh_cmt_register_clockevent()
834 ch->cmt->has_clockevent = true; in sh_cmt_register()
841 ch->cmt->has_clocksource = true; in sh_cmt_register()
850 bool clocksource, struct sh_cmt_device *cmt) in sh_cmt_setup_channel() argument
858 ch->cmt = cmt; in sh_cmt_setup_channel()
868 switch (cmt->info->model) { in sh_cmt_setup_channel()
870 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; in sh_cmt_setup_channel()
874 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; in sh_cmt_setup_channel()
878 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; in sh_cmt_setup_channel()
884 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) in sh_cmt_setup_channel()
887 ch->max_match_value = (1 << cmt->info->width) - 1; in sh_cmt_setup_channel()
892 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), in sh_cmt_setup_channel()
895 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", in sh_cmt_setup_channel()
904 static int sh_cmt_map_memory(struct sh_cmt_device *cmt) in sh_cmt_map_memory() argument
908 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); in sh_cmt_map_memory()
910 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); in sh_cmt_map_memory()
914 cmt->mapbase = ioremap(mem->start, resource_size(mem)); in sh_cmt_map_memory()
915 if (cmt->mapbase == NULL) { in sh_cmt_map_memory()
916 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); in sh_cmt_map_memory()
924 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
925 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
933 .compatible = "renesas,cmt-48",
938 .compatible = "renesas,cmt-48-gen2",
969 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) in sh_cmt_setup() argument
975 cmt->pdev = pdev; in sh_cmt_setup()
976 raw_spin_lock_init(&cmt->lock); in sh_cmt_setup()
979 cmt->info = of_device_get_match_data(&pdev->dev); in sh_cmt_setup()
980 cmt->hw_channels = cmt->info->channels_mask; in sh_cmt_setup()
985 cmt->info = (const struct sh_cmt_info *)id->driver_data; in sh_cmt_setup()
986 cmt->hw_channels = cfg->channels_mask; in sh_cmt_setup()
988 dev_err(&cmt->pdev->dev, "missing platform data\n"); in sh_cmt_setup()
993 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); in sh_cmt_setup()
994 if (IS_ERR(cmt->clk)) { in sh_cmt_setup()
995 dev_err(&cmt->pdev->dev, "cannot get clock\n"); in sh_cmt_setup()
996 return PTR_ERR(cmt->clk); in sh_cmt_setup()
999 ret = clk_prepare(cmt->clk); in sh_cmt_setup()
1004 ret = clk_enable(cmt->clk); in sh_cmt_setup()
1008 if (cmt->info->width == 16) in sh_cmt_setup()
1009 cmt->rate = clk_get_rate(cmt->clk) / 512; in sh_cmt_setup()
1011 cmt->rate = clk_get_rate(cmt->clk) / 8; in sh_cmt_setup()
1013 clk_disable(cmt->clk); in sh_cmt_setup()
1016 ret = sh_cmt_map_memory(cmt); in sh_cmt_setup()
1021 cmt->num_channels = hweight8(cmt->hw_channels); in sh_cmt_setup()
1022 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), in sh_cmt_setup()
1024 if (cmt->channels == NULL) { in sh_cmt_setup()
1033 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { in sh_cmt_setup()
1035 bool clocksource = i == 1 || cmt->num_channels == 1; in sh_cmt_setup()
1038 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, in sh_cmt_setup()
1039 clockevent, clocksource, cmt); in sh_cmt_setup()
1046 platform_set_drvdata(pdev, cmt); in sh_cmt_setup()
1051 kfree(cmt->channels); in sh_cmt_setup()
1052 iounmap(cmt->mapbase); in sh_cmt_setup()
1054 clk_unprepare(cmt->clk); in sh_cmt_setup()
1056 clk_put(cmt->clk); in sh_cmt_setup()
1062 struct sh_cmt_device *cmt = platform_get_drvdata(pdev); in sh_cmt_probe() local
1070 if (cmt) { in sh_cmt_probe()
1075 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); in sh_cmt_probe()
1076 if (cmt == NULL) in sh_cmt_probe()
1079 ret = sh_cmt_setup(cmt, pdev); in sh_cmt_probe()
1081 kfree(cmt); in sh_cmt_probe()
1089 if (cmt->has_clockevent || cmt->has_clocksource) in sh_cmt_probe()
1130 MODULE_DESCRIPTION("SuperH CMT Timer Driver");