Lines Matching +full:tegra210 +full:- +full:ahub
1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADMA driver for Nvidia's Tegra210 ADMA controller.
17 #include "virt-dma.h"
75 * struct tegra_adma_chip_data - Tegra chip specific data
78 * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
79 * @ch_req_rx_shift: Register offset for AHUB receive channel select.
104 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
117 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
128 * struct tegra_adma_chan - Tegra ADMA channel information
150 * struct tegra_adma - Tegra ADMA controller information
172 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_write()
177 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_read()
182 writel(val, tdc->chan_addr + reg); in tdma_ch_write()
187 return readl(tdc->chan_addr + reg); in tdma_ch_read()
203 return tdc->tdma->dev; in tdc2dev()
216 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig)); in tegra_adma_slave_config()
227 tdma_write(tdma, tdma->cdata->global_int_clear, 0x1); in tegra_adma_init()
234 tdma->base_addr + in tegra_adma_init()
235 tdma->cdata->global_reg_offset + in tegra_adma_init()
250 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_alloc()
251 unsigned int sreq_index = tdc->sreq_index; in tegra_adma_request_alloc()
253 if (tdc->sreq_reserved) in tegra_adma_request_alloc()
254 return tdc->sreq_dir == direction ? 0 : -EINVAL; in tegra_adma_request_alloc()
256 if (sreq_index > tdma->cdata->ch_req_max) { in tegra_adma_request_alloc()
257 dev_err(tdma->dev, "invalid DMA request\n"); in tegra_adma_request_alloc()
258 return -EINVAL; in tegra_adma_request_alloc()
263 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) { in tegra_adma_request_alloc()
264 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
265 return -EINVAL; in tegra_adma_request_alloc()
270 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) { in tegra_adma_request_alloc()
271 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
272 return -EINVAL; in tegra_adma_request_alloc()
277 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_alloc()
278 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_alloc()
279 return -EINVAL; in tegra_adma_request_alloc()
282 tdc->sreq_dir = direction; in tegra_adma_request_alloc()
283 tdc->sreq_reserved = true; in tegra_adma_request_alloc()
290 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_free()
292 if (!tdc->sreq_reserved) in tegra_adma_request_free()
295 switch (tdc->sreq_dir) { in tegra_adma_request_free()
297 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved); in tegra_adma_request_free()
301 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved); in tegra_adma_request_free()
305 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_free()
306 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_free()
310 tdc->sreq_reserved = false; in tegra_adma_request_free()
340 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS, in tegra_adma_stop()
347 kfree(tdc->desc); in tegra_adma_stop()
348 tdc->desc = NULL; in tegra_adma_stop()
353 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); in tegra_adma_start()
360 list_del(&vd->node); in tegra_adma_start()
362 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_start()
369 ch_regs = &desc->ch_regs; in tegra_adma_start()
371 tdc->tx_buf_pos = 0; in tegra_adma_start()
372 tdc->tx_buf_count = 0; in tegra_adma_start()
373 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc); in tegra_adma_start()
374 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_start()
375 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr); in tegra_adma_start()
376 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr); in tegra_adma_start()
377 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); in tegra_adma_start()
378 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); in tegra_adma_start()
383 tdc->desc = desc; in tegra_adma_start()
388 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_get_residue()
396 if (pos < tdc->tx_buf_pos) in tegra_adma_get_residue()
397 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos); in tegra_adma_get_residue()
399 tdc->tx_buf_count += pos - tdc->tx_buf_pos; in tegra_adma_get_residue()
401 periods_remaining = tdc->tx_buf_count % desc->num_periods; in tegra_adma_get_residue()
402 tdc->tx_buf_pos = pos; in tegra_adma_get_residue()
404 return desc->buf_len - (periods_remaining * desc->period_len); in tegra_adma_get_residue()
413 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_isr()
416 if (status == 0 || !tdc->desc) { in tegra_adma_isr()
417 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_isr()
421 vchan_cyclic_callback(&tdc->desc->vd); in tegra_adma_isr()
423 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_isr()
433 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
435 if (vchan_issue_pending(&tdc->vc)) { in tegra_adma_issue_pending()
436 if (!tdc->desc) in tegra_adma_issue_pending()
440 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
456 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_pause()
457 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_pause()
460 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_pause()
461 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); in tegra_adma_pause()
462 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_pause()
464 while (dcnt-- && !tegra_adma_is_paused(tdc)) in tegra_adma_pause()
469 return -EBUSY; in tegra_adma_pause()
478 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_resume()
479 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_resume()
481 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_resume()
482 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); in tegra_adma_resume()
483 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_resume()
494 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
496 if (tdc->desc) in tegra_adma_terminate_all()
500 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_adma_terminate_all()
501 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
502 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_adma_terminate_all()
522 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_tx_status()
524 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_adma_tx_status()
526 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_tx_status()
527 residual = desc->ch_regs.tc; in tegra_adma_tx_status()
528 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) { in tegra_adma_tx_status()
534 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_tx_status()
554 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; in tegra186_adma_get_burst_config()
562 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_set_xfer_params()
563 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata; in tegra_adma_set_xfer_params()
566 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS) in tegra_adma_set_xfer_params()
567 return -EINVAL; in tegra_adma_set_xfer_params()
572 burst_size = tdc->sconfig.dst_maxburst; in tegra_adma_set_xfer_params()
573 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
574 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, in tegra_adma_set_xfer_params()
575 cdata->ch_req_mask, in tegra_adma_set_xfer_params()
576 cdata->ch_req_tx_shift); in tegra_adma_set_xfer_params()
577 ch_regs->src_addr = buf_addr; in tegra_adma_set_xfer_params()
582 burst_size = tdc->sconfig.src_maxburst; in tegra_adma_set_xfer_params()
583 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
584 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, in tegra_adma_set_xfer_params()
585 cdata->ch_req_mask, in tegra_adma_set_xfer_params()
586 cdata->ch_req_rx_shift); in tegra_adma_set_xfer_params()
587 ch_regs->trg_addr = buf_addr; in tegra_adma_set_xfer_params()
592 return -EINVAL; in tegra_adma_set_xfer_params()
595 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) | in tegra_adma_set_xfer_params()
598 ch_regs->config |= cdata->adma_get_burst_config(burst_size); in tegra_adma_set_xfer_params()
599 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1); in tegra_adma_set_xfer_params()
600 if (cdata->has_outstanding_reqs) in tegra_adma_set_xfer_params()
601 ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8); in tegra_adma_set_xfer_params()
602 ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl; in tegra_adma_set_xfer_params()
603 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; in tegra_adma_set_xfer_params()
635 desc->buf_len = buf_len; in tegra_adma_prep_dma_cyclic()
636 desc->period_len = period_len; in tegra_adma_prep_dma_cyclic()
637 desc->num_periods = buf_len / period_len; in tegra_adma_prep_dma_cyclic()
644 return vchan_tx_prep(&tdc->vc, &desc->vd, flags); in tegra_adma_prep_dma_cyclic()
652 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc); in tegra_adma_alloc_chan_resources()
662 free_irq(tdc->irq, tdc); in tegra_adma_alloc_chan_resources()
666 dma_cookie_init(&tdc->vc.chan); in tegra_adma_alloc_chan_resources()
676 vchan_free_chan_resources(&tdc->vc); in tegra_adma_free_chan_resources()
677 tasklet_kill(&tdc->vc.task); in tegra_adma_free_chan_resources()
678 free_irq(tdc->irq, tdc); in tegra_adma_free_chan_resources()
681 tdc->sreq_index = 0; in tegra_adma_free_chan_resources()
682 tdc->sreq_dir = DMA_TRANS_NONE; in tegra_adma_free_chan_resources()
688 struct tegra_adma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
693 if (dma_spec->args_count != 1) in tegra_dma_of_xlate()
696 sreq_index = dma_spec->args[0]; in tegra_dma_of_xlate()
699 dev_err(tdma->dev, "DMA request must not be 0\n"); in tegra_dma_of_xlate()
703 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
708 tdc->sreq_index = sreq_index; in tegra_dma_of_xlate()
720 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); in tegra_adma_runtime_suspend()
721 if (!tdma->global_cmd) in tegra_adma_runtime_suspend()
724 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_suspend()
725 tdc = &tdma->channels[i]; in tegra_adma_runtime_suspend()
726 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_suspend()
727 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); in tegra_adma_runtime_suspend()
729 if (!ch_reg->cmd) in tegra_adma_runtime_suspend()
731 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC); in tegra_adma_runtime_suspend()
732 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR); in tegra_adma_runtime_suspend()
733 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR); in tegra_adma_runtime_suspend()
734 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_runtime_suspend()
735 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); in tegra_adma_runtime_suspend()
736 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG); in tegra_adma_runtime_suspend()
740 clk_disable_unprepare(tdma->ahub_clk); in tegra_adma_runtime_suspend()
752 ret = clk_prepare_enable(tdma->ahub_clk); in tegra_adma_runtime_resume()
754 dev_err(dev, "ahub clk_enable failed: %d\n", ret); in tegra_adma_runtime_resume()
757 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); in tegra_adma_runtime_resume()
759 if (!tdma->global_cmd) in tegra_adma_runtime_resume()
762 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_resume()
763 tdc = &tdma->channels[i]; in tegra_adma_runtime_resume()
764 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_resume()
766 if (!ch_reg->cmd) in tegra_adma_runtime_resume()
768 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc); in tegra_adma_runtime_resume()
769 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr); in tegra_adma_runtime_resume()
770 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr); in tegra_adma_runtime_resume()
771 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); in tegra_adma_runtime_resume()
772 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); in tegra_adma_runtime_resume()
773 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); in tegra_adma_runtime_resume()
774 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); in tegra_adma_runtime_resume()
811 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
812 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
824 cdata = of_device_get_match_data(&pdev->dev); in tegra_adma_probe()
826 dev_err(&pdev->dev, "device match data not found\n"); in tegra_adma_probe()
827 return -ENODEV; in tegra_adma_probe()
830 tdma = devm_kzalloc(&pdev->dev, in tegra_adma_probe()
831 struct_size(tdma, channels, cdata->nr_channels), in tegra_adma_probe()
834 return -ENOMEM; in tegra_adma_probe()
836 tdma->dev = &pdev->dev; in tegra_adma_probe()
837 tdma->cdata = cdata; in tegra_adma_probe()
838 tdma->nr_channels = cdata->nr_channels; in tegra_adma_probe()
842 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res); in tegra_adma_probe()
843 if (IS_ERR(tdma->base_addr)) in tegra_adma_probe()
844 return PTR_ERR(tdma->base_addr); in tegra_adma_probe()
846 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); in tegra_adma_probe()
847 if (IS_ERR(tdma->ahub_clk)) { in tegra_adma_probe()
848 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); in tegra_adma_probe()
849 return PTR_ERR(tdma->ahub_clk); in tegra_adma_probe()
852 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_adma_probe()
853 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_probe()
854 struct tegra_adma_chan *tdc = &tdma->channels[i]; in tegra_adma_probe()
856 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset in tegra_adma_probe()
857 + (cdata->ch_reg_size * i); in tegra_adma_probe()
859 tdc->irq = of_irq_get(pdev->dev.of_node, i); in tegra_adma_probe()
860 if (tdc->irq <= 0) { in tegra_adma_probe()
861 ret = tdc->irq ?: -ENXIO; in tegra_adma_probe()
865 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_adma_probe()
866 tdc->vc.desc_free = tegra_adma_desc_free; in tegra_adma_probe()
867 tdc->tdma = tdma; in tegra_adma_probe()
870 pm_runtime_enable(&pdev->dev); in tegra_adma_probe()
872 ret = pm_runtime_get_sync(&pdev->dev); in tegra_adma_probe()
874 pm_runtime_put_noidle(&pdev->dev); in tegra_adma_probe()
882 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
883 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
884 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_adma_probe()
886 tdma->dma_dev.dev = &pdev->dev; in tegra_adma_probe()
887 tdma->dma_dev.device_alloc_chan_resources = in tegra_adma_probe()
889 tdma->dma_dev.device_free_chan_resources = in tegra_adma_probe()
891 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending; in tegra_adma_probe()
892 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic; in tegra_adma_probe()
893 tdma->dma_dev.device_config = tegra_adma_slave_config; in tegra_adma_probe()
894 tdma->dma_dev.device_tx_status = tegra_adma_tx_status; in tegra_adma_probe()
895 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all; in tegra_adma_probe()
896 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
897 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
898 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in tegra_adma_probe()
899 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in tegra_adma_probe()
900 tdma->dma_dev.device_pause = tegra_adma_pause; in tegra_adma_probe()
901 tdma->dma_dev.device_resume = tegra_adma_resume; in tegra_adma_probe()
903 ret = dma_async_device_register(&tdma->dma_dev); in tegra_adma_probe()
905 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret); in tegra_adma_probe()
909 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_adma_probe()
912 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret); in tegra_adma_probe()
916 pm_runtime_put(&pdev->dev); in tegra_adma_probe()
918 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n", in tegra_adma_probe()
919 tdma->nr_channels); in tegra_adma_probe()
924 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_probe()
926 pm_runtime_put_sync(&pdev->dev); in tegra_adma_probe()
928 pm_runtime_disable(&pdev->dev); in tegra_adma_probe()
930 while (--i >= 0) in tegra_adma_probe()
931 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_probe()
941 of_dma_controller_free(pdev->dev.of_node); in tegra_adma_remove()
942 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_remove()
944 for (i = 0; i < tdma->nr_channels; ++i) in tegra_adma_remove()
945 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_remove()
947 pm_runtime_put_sync(&pdev->dev); in tegra_adma_remove()
948 pm_runtime_disable(&pdev->dev); in tegra_adma_remove()
962 .name = "tegra-adma",
972 MODULE_ALIAS("platform:tegra210-adma");