Lines Matching refs:adev
85 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
98 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
110 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
115 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_rreg()
122 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_smc_wreg() argument
126 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_wreg()
129 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_wreg()
136 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) in cz_smc_rreg() argument
141 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cz_smc_rreg()
144 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cz_smc_rreg()
148 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cz_smc_wreg() argument
152 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cz_smc_wreg()
155 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cz_smc_wreg()
158 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in vi_uvd_ctx_rreg() argument
163 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_rreg()
166 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_rreg()
170 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_uvd_ctx_wreg() argument
174 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_wreg()
177 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in vi_uvd_ctx_wreg()
180 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) in vi_didt_rreg() argument
185 spin_lock_irqsave(&adev->didt_idx_lock, flags); in vi_didt_rreg()
188 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in vi_didt_rreg()
192 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_didt_wreg() argument
196 spin_lock_irqsave(&adev->didt_idx_lock, flags); in vi_didt_wreg()
199 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in vi_didt_wreg()
202 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in vi_gc_cac_rreg() argument
207 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_rreg()
210 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_rreg()
214 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_gc_cac_wreg() argument
218 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_wreg()
221 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in vi_gc_cac_wreg()
272 static void vi_init_golden_registers(struct amdgpu_device *adev) in vi_init_golden_registers() argument
275 mutex_lock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
277 if (amdgpu_sriov_vf(adev)) { in vi_init_golden_registers()
278 xgpu_vi_init_golden_registers(adev); in vi_init_golden_registers()
279 mutex_unlock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
283 switch (adev->asic_type) { in vi_init_golden_registers()
285 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
290 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
295 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
300 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
305 amdgpu_device_program_register_sequence(adev, in vi_init_golden_registers()
316 mutex_unlock(&adev->grbm_idx_mutex); in vi_init_golden_registers()
327 static u32 vi_get_xclk(struct amdgpu_device *adev) in vi_get_xclk() argument
329 u32 reference_clock = adev->clock.spll.reference_freq; in vi_get_xclk()
332 if (adev->flags & AMD_IS_APU) in vi_get_xclk()
359 void vi_srbm_select(struct amdgpu_device *adev, in vi_srbm_select() argument
370 static void vi_vga_set_state(struct amdgpu_device *adev, bool state) in vi_vga_set_state() argument
375 static bool vi_read_disabled_bios(struct amdgpu_device *adev) in vi_read_disabled_bios() argument
385 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
394 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
407 r = amdgpu_read_bios(adev); in vi_read_disabled_bios()
411 if (adev->mode_info.num_crtc) { in vi_read_disabled_bios()
420 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, in vi_read_bios_from_rom() argument
432 if (adev->flags & AMD_IS_APU) in vi_read_bios_from_rom()
438 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_read_bios_from_rom()
446 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_read_bios_from_rom()
530 static uint32_t vi_get_register_value(struct amdgpu_device *adev, in vi_get_register_value() argument
541 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; in vi_get_register_value()
543 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; in vi_get_register_value()
545 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; in vi_get_register_value()
547 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; in vi_get_register_value()
550 mutex_lock(&adev->grbm_idx_mutex); in vi_get_register_value()
552 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
557 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); in vi_get_register_value()
558 mutex_unlock(&adev->grbm_idx_mutex); in vi_get_register_value()
565 return adev->gfx.config.gb_addr_config; in vi_get_register_value()
567 return adev->gfx.config.mc_arb_ramcfg; in vi_get_register_value()
601 return adev->gfx.config.tile_mode_array[idx]; in vi_get_register_value()
619 return adev->gfx.config.macrotile_mode_array[idx]; in vi_get_register_value()
626 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
638 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
645 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) in vi_gpu_pci_config_reset() argument
649 dev_info(adev->dev, "GPU pci config reset\n"); in vi_gpu_pci_config_reset()
652 pci_clear_master(adev->pdev); in vi_gpu_pci_config_reset()
654 amdgpu_device_pci_config_reset(adev); in vi_gpu_pci_config_reset()
659 for (i = 0; i < adev->usec_timeout; i++) { in vi_gpu_pci_config_reset()
662 pci_set_master(adev->pdev); in vi_gpu_pci_config_reset()
663 adev->has_hw_reset = true; in vi_gpu_pci_config_reset()
680 static int vi_asic_pci_config_reset(struct amdgpu_device *adev) in vi_asic_pci_config_reset() argument
684 amdgpu_atombios_scratch_regs_engine_hung(adev, true); in vi_asic_pci_config_reset()
686 r = vi_gpu_pci_config_reset(adev); in vi_asic_pci_config_reset()
688 amdgpu_atombios_scratch_regs_engine_hung(adev, false); in vi_asic_pci_config_reset()
693 static bool vi_asic_supports_baco(struct amdgpu_device *adev) in vi_asic_supports_baco() argument
695 switch (adev->asic_type) { in vi_asic_supports_baco()
702 return amdgpu_dpm_is_baco_supported(adev); in vi_asic_supports_baco()
709 vi_asic_reset_method(struct amdgpu_device *adev) in vi_asic_reset_method() argument
718 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in vi_asic_reset_method()
721 switch (adev->asic_type) { in vi_asic_reset_method()
728 baco_reset = amdgpu_dpm_is_baco_supported(adev); in vi_asic_reset_method()
750 static int vi_asic_reset(struct amdgpu_device *adev) in vi_asic_reset() argument
754 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { in vi_asic_reset()
755 dev_info(adev->dev, "BACO reset\n"); in vi_asic_reset()
756 r = amdgpu_dpm_baco_reset(adev); in vi_asic_reset()
758 dev_info(adev->dev, "PCI CONFIG reset\n"); in vi_asic_reset()
759 r = vi_asic_pci_config_reset(adev); in vi_asic_reset()
765 static u32 vi_get_config_memsize(struct amdgpu_device *adev) in vi_get_config_memsize() argument
770 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, in vi_set_uvd_clock() argument
777 r = amdgpu_atombios_get_clock_dividers(adev, in vi_set_uvd_clock()
785 if (adev->flags & AMD_IS_APU) in vi_set_uvd_clock()
795 if (adev->flags & AMD_IS_APU) { in vi_set_uvd_clock()
816 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument
820 if (adev->flags & AMD_IS_APU) { in vi_set_uvd_clocks()
821 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); in vi_set_uvd_clocks()
825 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); in vi_set_uvd_clocks()
829 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in vi_set_uvd_clocks()
833 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in vi_set_uvd_clocks()
841 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in vi_set_vce_clocks() argument
851 if (adev->flags & AMD_IS_APU) { in vi_set_vce_clocks()
863 r = amdgpu_atombios_get_clock_dividers(adev, in vi_set_vce_clocks()
895 static void vi_pcie_gen3_enable(struct amdgpu_device *adev) in vi_pcie_gen3_enable() argument
897 if (pci_is_root_bus(adev->pdev->bus)) in vi_pcie_gen3_enable()
903 if (adev->flags & AMD_IS_APU) in vi_pcie_gen3_enable()
906 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | in vi_pcie_gen3_enable()
913 static void vi_program_aspm(struct amdgpu_device *adev) in vi_program_aspm() argument
922 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, in vi_enable_doorbell_aperture() argument
928 if (adev->flags & AMD_IS_APU) in vi_enable_doorbell_aperture()
944 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) in vi_get_rev_id() argument
946 if (adev->flags & AMD_IS_APU) in vi_get_rev_id()
954 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) in vi_flush_hdp() argument
964 static void vi_invalidate_hdp(struct amdgpu_device *adev, in vi_invalidate_hdp() argument
975 static bool vi_need_full_reset(struct amdgpu_device *adev) in vi_need_full_reset() argument
977 switch (adev->asic_type) { in vi_need_full_reset()
996 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vi_get_pcie_usage() argument
1006 if (adev->flags & AMD_IS_APU) in vi_get_pcie_usage()
1042 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev) in vi_get_pcie_replay_count() argument
1054 static bool vi_need_reset_on_init(struct amdgpu_device *adev) in vi_need_reset_on_init() argument
1058 if (adev->flags & AMD_IS_APU) in vi_need_reset_on_init()
1071 static void vi_pre_asic_init(struct amdgpu_device *adev) in vi_pre_asic_init() argument
1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_early_init() local
1105 if (adev->flags & AMD_IS_APU) { in vi_common_early_init()
1106 adev->smc_rreg = &cz_smc_rreg; in vi_common_early_init()
1107 adev->smc_wreg = &cz_smc_wreg; in vi_common_early_init()
1109 adev->smc_rreg = &vi_smc_rreg; in vi_common_early_init()
1110 adev->smc_wreg = &vi_smc_wreg; in vi_common_early_init()
1112 adev->pcie_rreg = &vi_pcie_rreg; in vi_common_early_init()
1113 adev->pcie_wreg = &vi_pcie_wreg; in vi_common_early_init()
1114 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; in vi_common_early_init()
1115 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; in vi_common_early_init()
1116 adev->didt_rreg = &vi_didt_rreg; in vi_common_early_init()
1117 adev->didt_wreg = &vi_didt_wreg; in vi_common_early_init()
1118 adev->gc_cac_rreg = &vi_gc_cac_rreg; in vi_common_early_init()
1119 adev->gc_cac_wreg = &vi_gc_cac_wreg; in vi_common_early_init()
1121 adev->asic_funcs = &vi_asic_funcs; in vi_common_early_init()
1123 adev->rev_id = vi_get_rev_id(adev); in vi_common_early_init()
1124 adev->external_rev_id = 0xFF; in vi_common_early_init()
1125 switch (adev->asic_type) { in vi_common_early_init()
1127 adev->cg_flags = 0; in vi_common_early_init()
1128 adev->pg_flags = 0; in vi_common_early_init()
1129 adev->external_rev_id = 0x1; in vi_common_early_init()
1132 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1149 adev->pg_flags = 0; in vi_common_early_init()
1150 adev->external_rev_id = adev->rev_id + 0x3c; in vi_common_early_init()
1153 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1166 adev->pg_flags = 0; in vi_common_early_init()
1167 adev->external_rev_id = adev->rev_id + 0x14; in vi_common_early_init()
1170 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1189 adev->pg_flags = 0; in vi_common_early_init()
1190 adev->external_rev_id = adev->rev_id + 0x5A; in vi_common_early_init()
1193 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1212 adev->pg_flags = 0; in vi_common_early_init()
1213 adev->external_rev_id = adev->rev_id + 0x50; in vi_common_early_init()
1216 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in vi_common_early_init()
1235 adev->pg_flags = 0; in vi_common_early_init()
1236 adev->external_rev_id = adev->rev_id + 0x64; in vi_common_early_init()
1239 adev->cg_flags = 0; in vi_common_early_init()
1259 adev->pg_flags = 0; in vi_common_early_init()
1260 adev->external_rev_id = adev->rev_id + 0x6E; in vi_common_early_init()
1263 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | in vi_common_early_init()
1279 adev->pg_flags = 0; in vi_common_early_init()
1280 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { in vi_common_early_init()
1281 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | in vi_common_early_init()
1287 adev->external_rev_id = adev->rev_id + 0x1; in vi_common_early_init()
1290 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | in vi_common_early_init()
1304 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | in vi_common_early_init()
1310 adev->external_rev_id = adev->rev_id + 0x61; in vi_common_early_init()
1317 if (amdgpu_sriov_vf(adev)) { in vi_common_early_init()
1318 amdgpu_virt_init_setting(adev); in vi_common_early_init()
1319 xgpu_vi_mailbox_set_irq_funcs(adev); in vi_common_early_init()
1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_late_init() local
1329 if (amdgpu_sriov_vf(adev)) in vi_common_late_init()
1330 xgpu_vi_mailbox_get_irq(adev); in vi_common_late_init()
1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_sw_init() local
1339 if (amdgpu_sriov_vf(adev)) in vi_common_sw_init()
1340 xgpu_vi_mailbox_add_irq_id(adev); in vi_common_sw_init()
1352 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_hw_init() local
1355 vi_init_golden_registers(adev); in vi_common_hw_init()
1357 vi_pcie_gen3_enable(adev); in vi_common_hw_init()
1359 vi_program_aspm(adev); in vi_common_hw_init()
1361 vi_enable_doorbell_aperture(adev, true); in vi_common_hw_init()
1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_hw_fini() local
1371 vi_enable_doorbell_aperture(adev, false); in vi_common_hw_fini()
1373 if (amdgpu_sriov_vf(adev)) in vi_common_hw_fini()
1374 xgpu_vi_mailbox_put_irq(adev); in vi_common_hw_fini()
1381 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_suspend() local
1383 return vi_common_hw_fini(adev); in vi_common_suspend()
1388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_resume() local
1390 return vi_common_hw_init(adev); in vi_common_resume()
1408 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, in vi_update_bif_medium_grain_light_sleep() argument
1415 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) in vi_update_bif_medium_grain_light_sleep()
1428 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, in vi_update_hdp_medium_grain_clock_gating() argument
1435 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) in vi_update_hdp_medium_grain_clock_gating()
1444 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, in vi_update_hdp_light_sleep() argument
1451 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) in vi_update_hdp_light_sleep()
1460 static void vi_update_drm_light_sleep(struct amdgpu_device *adev, in vi_update_drm_light_sleep() argument
1467 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in vi_update_drm_light_sleep()
1477 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, in vi_update_rom_medium_grain_clock_gating() argument
1484 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) in vi_update_rom_medium_grain_clock_gating()
1500 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_set_clockgating_state_by_smu() local
1502 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1503 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { in vi_common_set_clockgating_state_by_smu()
1507 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { in vi_common_set_clockgating_state_by_smu()
1517 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1520 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1521 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { in vi_common_set_clockgating_state_by_smu()
1525 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { in vi_common_set_clockgating_state_by_smu()
1535 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1538 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { in vi_common_set_clockgating_state_by_smu()
1539 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { in vi_common_set_clockgating_state_by_smu()
1543 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { in vi_common_set_clockgating_state_by_smu()
1553 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1557 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { in vi_common_set_clockgating_state_by_smu()
1567 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1569 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { in vi_common_set_clockgating_state_by_smu()
1579 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1582 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { in vi_common_set_clockgating_state_by_smu()
1593 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1596 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { in vi_common_set_clockgating_state_by_smu()
1607 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); in vi_common_set_clockgating_state_by_smu()
1615 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_set_clockgating_state() local
1617 if (amdgpu_sriov_vf(adev)) in vi_common_set_clockgating_state()
1620 switch (adev->asic_type) { in vi_common_set_clockgating_state()
1622 vi_update_bif_medium_grain_light_sleep(adev, in vi_common_set_clockgating_state()
1624 vi_update_hdp_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
1626 vi_update_hdp_light_sleep(adev, in vi_common_set_clockgating_state()
1628 vi_update_rom_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
1633 vi_update_bif_medium_grain_light_sleep(adev, in vi_common_set_clockgating_state()
1635 vi_update_hdp_medium_grain_clock_gating(adev, in vi_common_set_clockgating_state()
1637 vi_update_hdp_light_sleep(adev, in vi_common_set_clockgating_state()
1639 vi_update_drm_light_sleep(adev, in vi_common_set_clockgating_state()
1647 vi_common_set_clockgating_state_by_smu(adev, state); in vi_common_set_clockgating_state()
1662 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in vi_common_get_clockgating_state() local
1665 if (amdgpu_sriov_vf(adev)) in vi_common_get_clockgating_state()
1716 void vi_set_virt_ops(struct amdgpu_device *adev) in vi_set_virt_ops() argument
1718 adev->virt.ops = &xgpu_vi_virt_ops; in vi_set_virt_ops()
1721 int vi_set_ip_blocks(struct amdgpu_device *adev) in vi_set_ip_blocks() argument
1723 switch (adev->asic_type) { in vi_set_ip_blocks()
1726 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
1727 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); in vi_set_ip_blocks()
1728 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); in vi_set_ip_blocks()
1729 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
1730 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); in vi_set_ip_blocks()
1731 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
1732 if (adev->enable_virtual_display) in vi_set_ip_blocks()
1733 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in vi_set_ip_blocks()
1736 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
1737 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); in vi_set_ip_blocks()
1738 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
1739 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
1740 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
1741 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
1742 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
1743 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in vi_set_ip_blocks()
1745 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
1746 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
1749 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); in vi_set_ip_blocks()
1750 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
1751 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); in vi_set_ip_blocks()
1752 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); in vi_set_ip_blocks()
1756 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
1757 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
1758 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
1759 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
1760 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
1761 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
1762 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
1763 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in vi_set_ip_blocks()
1765 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
1766 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
1769 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); in vi_set_ip_blocks()
1770 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
1771 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); in vi_set_ip_blocks()
1772 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); in vi_set_ip_blocks()
1779 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
1780 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); in vi_set_ip_blocks()
1781 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); in vi_set_ip_blocks()
1782 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
1783 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); in vi_set_ip_blocks()
1784 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
1785 if (adev->enable_virtual_display) in vi_set_ip_blocks()
1786 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in vi_set_ip_blocks()
1788 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
1789 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
1792 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); in vi_set_ip_blocks()
1793 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); in vi_set_ip_blocks()
1794 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); in vi_set_ip_blocks()
1797 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
1798 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
1799 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); in vi_set_ip_blocks()
1800 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); in vi_set_ip_blocks()
1801 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
1802 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
1803 if (adev->enable_virtual_display) in vi_set_ip_blocks()
1804 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in vi_set_ip_blocks()
1806 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
1807 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
1810 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); in vi_set_ip_blocks()
1811 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); in vi_set_ip_blocks()
1812 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); in vi_set_ip_blocks()
1814 amdgpu_device_ip_block_add(adev, &acp_ip_block); in vi_set_ip_blocks()
1818 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); in vi_set_ip_blocks()
1819 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); in vi_set_ip_blocks()
1820 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); in vi_set_ip_blocks()
1821 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); in vi_set_ip_blocks()
1822 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); in vi_set_ip_blocks()
1823 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); in vi_set_ip_blocks()
1824 if (adev->enable_virtual_display) in vi_set_ip_blocks()
1825 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); in vi_set_ip_blocks()
1827 else if (amdgpu_device_has_dc_support(adev)) in vi_set_ip_blocks()
1828 amdgpu_device_ip_block_add(adev, &dm_ip_block); in vi_set_ip_blocks()
1831 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); in vi_set_ip_blocks()
1832 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); in vi_set_ip_blocks()
1833 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); in vi_set_ip_blocks()
1835 amdgpu_device_ip_block_add(adev, &acp_ip_block); in vi_set_ip_blocks()
1846 void legacy_doorbell_index_init(struct amdgpu_device *adev) in legacy_doorbell_index_init() argument
1848 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; in legacy_doorbell_index_init()
1849 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0; in legacy_doorbell_index_init()
1850 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1; in legacy_doorbell_index_init()
1851 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2; in legacy_doorbell_index_init()
1852 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3; in legacy_doorbell_index_init()
1853 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4; in legacy_doorbell_index_init()
1854 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5; in legacy_doorbell_index_init()
1855 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6; in legacy_doorbell_index_init()
1856 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7; in legacy_doorbell_index_init()
1857 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0; in legacy_doorbell_index_init()
1858 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0; in legacy_doorbell_index_init()
1859 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1; in legacy_doorbell_index_init()
1860 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH; in legacy_doorbell_index_init()
1861 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT; in legacy_doorbell_index_init()