Lines Matching full:dispc
10 #define DSS_SUBSYS_NAME "DISPC"
37 #include "dispc.h"
41 /* DISPC */
50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
57 /* DISPC has feature id */
100 int (*calc_scaling)(struct dispc_device *dispc,
129 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
216 /* DISPC register field id */
342 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
343 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
344 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
346 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
349 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
351 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
354 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
356 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) in dispc_write_reg() argument
358 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
361 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx) in dispc_read_reg() argument
363 return __raw_readl(dispc->base + idx); in dispc_read_reg()
366 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_read() argument
371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
374 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_write() argument
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
382 static int dispc_get_num_ovls(struct dispc_device *dispc) in dispc_get_num_ovls() argument
384 return dispc->feat->num_ovls; in dispc_get_num_ovls()
387 static int dispc_get_num_mgrs(struct dispc_device *dispc) in dispc_get_num_mgrs() argument
389 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
392 static void dispc_get_reg_field(struct dispc_device *dispc, in dispc_get_reg_field() argument
396 BUG_ON(id >= dispc->feat->num_reg_fields); in dispc_get_reg_field()
398 *start = dispc->feat->reg_fields[id].start; in dispc_get_reg_field()
399 *end = dispc->feat->reg_fields[id].end; in dispc_get_reg_field()
402 static bool dispc_has_feature(struct dispc_device *dispc, in dispc_has_feature() argument
407 for (i = 0; i < dispc->feat->num_features; i++) { in dispc_has_feature()
408 if (dispc->feat->features[i] == id) in dispc_has_feature()
415 #define SR(dispc, reg) \ argument
416 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
417 #define RR(dispc, reg) \ argument
418 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
420 static void dispc_save_context(struct dispc_device *dispc) in dispc_save_context() argument
426 SR(dispc, IRQENABLE); in dispc_save_context()
427 SR(dispc, CONTROL); in dispc_save_context()
428 SR(dispc, CONFIG); in dispc_save_context()
429 SR(dispc, LINE_NUMBER); in dispc_save_context()
430 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_save_context()
431 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_save_context()
432 SR(dispc, GLOBAL_ALPHA); in dispc_save_context()
433 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_save_context()
434 SR(dispc, CONTROL2); in dispc_save_context()
435 SR(dispc, CONFIG2); in dispc_save_context()
437 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_save_context()
438 SR(dispc, CONTROL3); in dispc_save_context()
439 SR(dispc, CONFIG3); in dispc_save_context()
442 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_save_context()
443 SR(dispc, DEFAULT_COLOR(i)); in dispc_save_context()
444 SR(dispc, TRANS_COLOR(i)); in dispc_save_context()
445 SR(dispc, SIZE_MGR(i)); in dispc_save_context()
448 SR(dispc, TIMING_H(i)); in dispc_save_context()
449 SR(dispc, TIMING_V(i)); in dispc_save_context()
450 SR(dispc, POL_FREQ(i)); in dispc_save_context()
451 SR(dispc, DIVISORo(i)); in dispc_save_context()
453 SR(dispc, DATA_CYCLE1(i)); in dispc_save_context()
454 SR(dispc, DATA_CYCLE2(i)); in dispc_save_context()
455 SR(dispc, DATA_CYCLE3(i)); in dispc_save_context()
457 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_save_context()
458 SR(dispc, CPR_COEF_R(i)); in dispc_save_context()
459 SR(dispc, CPR_COEF_G(i)); in dispc_save_context()
460 SR(dispc, CPR_COEF_B(i)); in dispc_save_context()
464 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_save_context()
465 SR(dispc, OVL_BA0(i)); in dispc_save_context()
466 SR(dispc, OVL_BA1(i)); in dispc_save_context()
467 SR(dispc, OVL_POSITION(i)); in dispc_save_context()
468 SR(dispc, OVL_SIZE(i)); in dispc_save_context()
469 SR(dispc, OVL_ATTRIBUTES(i)); in dispc_save_context()
470 SR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_save_context()
471 SR(dispc, OVL_ROW_INC(i)); in dispc_save_context()
472 SR(dispc, OVL_PIXEL_INC(i)); in dispc_save_context()
473 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_save_context()
474 SR(dispc, OVL_PRELOAD(i)); in dispc_save_context()
476 SR(dispc, OVL_WINDOW_SKIP(i)); in dispc_save_context()
477 SR(dispc, OVL_TABLE_BA(i)); in dispc_save_context()
480 SR(dispc, OVL_FIR(i)); in dispc_save_context()
481 SR(dispc, OVL_PICTURE_SIZE(i)); in dispc_save_context()
482 SR(dispc, OVL_ACCU0(i)); in dispc_save_context()
483 SR(dispc, OVL_ACCU1(i)); in dispc_save_context()
486 SR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_save_context()
489 SR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_save_context()
492 SR(dispc, OVL_CONV_COEF(i, j)); in dispc_save_context()
494 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_save_context()
496 SR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_save_context()
499 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_save_context()
500 SR(dispc, OVL_BA0_UV(i)); in dispc_save_context()
501 SR(dispc, OVL_BA1_UV(i)); in dispc_save_context()
502 SR(dispc, OVL_FIR2(i)); in dispc_save_context()
503 SR(dispc, OVL_ACCU2_0(i)); in dispc_save_context()
504 SR(dispc, OVL_ACCU2_1(i)); in dispc_save_context()
507 SR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_save_context()
510 SR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_save_context()
513 SR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_save_context()
515 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_save_context()
516 SR(dispc, OVL_ATTRIBUTES2(i)); in dispc_save_context()
519 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_save_context()
520 SR(dispc, DIVISOR); in dispc_save_context()
522 dispc->ctx_valid = true; in dispc_save_context()
527 static void dispc_restore_context(struct dispc_device *dispc) in dispc_restore_context() argument
533 if (!dispc->ctx_valid) in dispc_restore_context()
536 /*RR(dispc, IRQENABLE);*/ in dispc_restore_context()
537 /*RR(dispc, CONTROL);*/ in dispc_restore_context()
538 RR(dispc, CONFIG); in dispc_restore_context()
539 RR(dispc, LINE_NUMBER); in dispc_restore_context()
540 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_restore_context()
541 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_restore_context()
542 RR(dispc, GLOBAL_ALPHA); in dispc_restore_context()
543 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
544 RR(dispc, CONFIG2); in dispc_restore_context()
545 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
546 RR(dispc, CONFIG3); in dispc_restore_context()
548 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_restore_context()
549 RR(dispc, DEFAULT_COLOR(i)); in dispc_restore_context()
550 RR(dispc, TRANS_COLOR(i)); in dispc_restore_context()
551 RR(dispc, SIZE_MGR(i)); in dispc_restore_context()
554 RR(dispc, TIMING_H(i)); in dispc_restore_context()
555 RR(dispc, TIMING_V(i)); in dispc_restore_context()
556 RR(dispc, POL_FREQ(i)); in dispc_restore_context()
557 RR(dispc, DIVISORo(i)); in dispc_restore_context()
559 RR(dispc, DATA_CYCLE1(i)); in dispc_restore_context()
560 RR(dispc, DATA_CYCLE2(i)); in dispc_restore_context()
561 RR(dispc, DATA_CYCLE3(i)); in dispc_restore_context()
563 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_restore_context()
564 RR(dispc, CPR_COEF_R(i)); in dispc_restore_context()
565 RR(dispc, CPR_COEF_G(i)); in dispc_restore_context()
566 RR(dispc, CPR_COEF_B(i)); in dispc_restore_context()
570 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_restore_context()
571 RR(dispc, OVL_BA0(i)); in dispc_restore_context()
572 RR(dispc, OVL_BA1(i)); in dispc_restore_context()
573 RR(dispc, OVL_POSITION(i)); in dispc_restore_context()
574 RR(dispc, OVL_SIZE(i)); in dispc_restore_context()
575 RR(dispc, OVL_ATTRIBUTES(i)); in dispc_restore_context()
576 RR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_restore_context()
577 RR(dispc, OVL_ROW_INC(i)); in dispc_restore_context()
578 RR(dispc, OVL_PIXEL_INC(i)); in dispc_restore_context()
579 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_restore_context()
580 RR(dispc, OVL_PRELOAD(i)); in dispc_restore_context()
582 RR(dispc, OVL_WINDOW_SKIP(i)); in dispc_restore_context()
583 RR(dispc, OVL_TABLE_BA(i)); in dispc_restore_context()
586 RR(dispc, OVL_FIR(i)); in dispc_restore_context()
587 RR(dispc, OVL_PICTURE_SIZE(i)); in dispc_restore_context()
588 RR(dispc, OVL_ACCU0(i)); in dispc_restore_context()
589 RR(dispc, OVL_ACCU1(i)); in dispc_restore_context()
592 RR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_restore_context()
595 RR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_restore_context()
598 RR(dispc, OVL_CONV_COEF(i, j)); in dispc_restore_context()
600 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_restore_context()
602 RR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_restore_context()
605 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_restore_context()
606 RR(dispc, OVL_BA0_UV(i)); in dispc_restore_context()
607 RR(dispc, OVL_BA1_UV(i)); in dispc_restore_context()
608 RR(dispc, OVL_FIR2(i)); in dispc_restore_context()
609 RR(dispc, OVL_ACCU2_0(i)); in dispc_restore_context()
610 RR(dispc, OVL_ACCU2_1(i)); in dispc_restore_context()
613 RR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_restore_context()
616 RR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_restore_context()
619 RR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_restore_context()
621 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_restore_context()
622 RR(dispc, OVL_ATTRIBUTES2(i)); in dispc_restore_context()
625 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_restore_context()
626 RR(dispc, DIVISOR); in dispc_restore_context()
629 RR(dispc, CONTROL); in dispc_restore_context()
630 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
631 RR(dispc, CONTROL2); in dispc_restore_context()
632 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
633 RR(dispc, CONTROL3); in dispc_restore_context()
635 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT); in dispc_restore_context()
641 RR(dispc, IRQENABLE); in dispc_restore_context()
649 int dispc_runtime_get(struct dispc_device *dispc) in dispc_runtime_get() argument
655 r = pm_runtime_get_sync(&dispc->pdev->dev); in dispc_runtime_get()
660 void dispc_runtime_put(struct dispc_device *dispc) in dispc_runtime_put() argument
666 r = pm_runtime_put_sync(&dispc->pdev->dev); in dispc_runtime_put()
670 static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, in dispc_mgr_get_vsync_irq() argument
676 static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, in dispc_mgr_get_framedone_irq() argument
679 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
685 static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, in dispc_mgr_get_sync_lost_irq() argument
691 static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) in dispc_wb_get_framedone_irq() argument
696 static void dispc_mgr_enable(struct dispc_device *dispc, in dispc_mgr_enable() argument
699 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable); in dispc_mgr_enable()
701 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_enable()
704 static bool dispc_mgr_is_enabled(struct dispc_device *dispc, in dispc_mgr_is_enabled() argument
707 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_is_enabled()
710 static bool dispc_mgr_go_busy(struct dispc_device *dispc, in dispc_mgr_go_busy() argument
713 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1; in dispc_mgr_go_busy()
716 static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) in dispc_mgr_go() argument
718 WARN_ON(!dispc_mgr_is_enabled(dispc, channel)); in dispc_mgr_go()
719 WARN_ON(dispc_mgr_go_busy(dispc, channel)); in dispc_mgr_go()
723 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); in dispc_mgr_go()
726 static bool dispc_wb_go_busy(struct dispc_device *dispc) in dispc_wb_go_busy() argument
728 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
731 static void dispc_wb_go(struct dispc_device *dispc) in dispc_wb_go() argument
736 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
741 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
747 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
750 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, in dispc_ovl_write_firh_reg() argument
754 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); in dispc_ovl_write_firh_reg()
757 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv_reg() argument
761 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); in dispc_ovl_write_firhv_reg()
764 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc, in dispc_ovl_write_firv_reg() argument
768 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); in dispc_ovl_write_firv_reg()
771 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc, in dispc_ovl_write_firh2_reg() argument
777 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); in dispc_ovl_write_firh2_reg()
780 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv2_reg() argument
786 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); in dispc_ovl_write_firhv2_reg()
789 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firv2_reg() argument
795 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); in dispc_ovl_write_firv2_reg()
798 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc, in dispc_ovl_set_scale_coef() argument
810 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", in dispc_ovl_set_scale_coef()
828 dispc_ovl_write_firh_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
829 dispc_ovl_write_firhv_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
831 dispc_ovl_write_firh2_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
832 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
843 dispc_ovl_write_firv_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
845 dispc_ovl_write_firv2_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
860 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc, in dispc_ovl_write_color_conv_coef() argument
866 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
869 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
870 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
872 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
877 static void dispc_wb_write_color_conv_coef(struct dispc_device *dispc, in dispc_wb_write_color_conv_coef() argument
884 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr)); in dispc_wb_write_color_conv_coef()
885 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb)); in dispc_wb_write_color_conv_coef()
886 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg)); in dispc_wb_write_color_conv_coef()
887 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr)); in dispc_wb_write_color_conv_coef()
888 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb)); in dispc_wb_write_color_conv_coef()
890 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_wb_write_color_conv_coef()
895 static void dispc_setup_color_conv_coef(struct dispc_device *dispc) in dispc_setup_color_conv_coef() argument
898 int num_ovl = dispc_get_num_ovls(dispc); in dispc_setup_color_conv_coef()
917 dispc_ovl_write_color_conv_coef(dispc, i, &coefs_yuv2rgb_bt601_lim); in dispc_setup_color_conv_coef()
919 if (dispc->feat->has_writeback) in dispc_setup_color_conv_coef()
920 dispc_wb_write_color_conv_coef(dispc, &coefs_rgb2yuv_bt601_lim); in dispc_setup_color_conv_coef()
923 static void dispc_ovl_set_ba0(struct dispc_device *dispc, in dispc_ovl_set_ba0() argument
926 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr); in dispc_ovl_set_ba0()
929 static void dispc_ovl_set_ba1(struct dispc_device *dispc, in dispc_ovl_set_ba1() argument
932 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr); in dispc_ovl_set_ba1()
935 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc, in dispc_ovl_set_ba0_uv() argument
938 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr); in dispc_ovl_set_ba0_uv()
941 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc, in dispc_ovl_set_ba1_uv() argument
944 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr); in dispc_ovl_set_ba1_uv()
947 static void dispc_ovl_set_pos(struct dispc_device *dispc, in dispc_ovl_set_pos() argument
958 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); in dispc_ovl_set_pos()
961 static void dispc_ovl_set_input_size(struct dispc_device *dispc, in dispc_ovl_set_input_size() argument
968 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_input_size()
970 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_input_size()
973 static void dispc_ovl_set_output_size(struct dispc_device *dispc, in dispc_ovl_set_output_size() argument
984 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_output_size()
986 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_output_size()
989 static void dispc_ovl_set_zorder(struct dispc_device *dispc, in dispc_ovl_set_zorder() argument
996 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
999 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc) in dispc_ovl_enable_zorder_planes() argument
1003 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_ovl_enable_zorder_planes()
1006 for (i = 0; i < dispc_get_num_ovls(dispc); i++) in dispc_ovl_enable_zorder_planes()
1007 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
1010 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc, in dispc_ovl_set_pre_mult_alpha() argument
1018 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
1021 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc, in dispc_ovl_setup_global_alpha() argument
1033 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
1036 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc, in dispc_ovl_set_pix_inc() argument
1039 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc); in dispc_ovl_set_pix_inc()
1042 static void dispc_ovl_set_row_inc(struct dispc_device *dispc, in dispc_ovl_set_row_inc() argument
1045 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc); in dispc_ovl_set_row_inc()
1048 static void dispc_ovl_set_color_mode(struct dispc_device *dispc, in dispc_ovl_set_color_mode() argument
1118 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode()
1121 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, in dispc_ovl_configure_burst_type() argument
1125 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0) in dispc_ovl_configure_burst_type()
1129 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type()
1131 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); in dispc_ovl_configure_burst_type()
1134 static void dispc_ovl_set_channel_out(struct dispc_device *dispc, in dispc_ovl_set_channel_out() argument
1156 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_channel_out()
1157 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_ovl_set_channel_out()
1172 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_ovl_set_channel_out()
1194 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_channel_out()
1197 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc, in dispc_ovl_get_channel_out() argument
1217 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_get_channel_out()
1222 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_ovl_get_channel_out()
1238 static void dispc_ovl_set_burst_size(struct dispc_device *dispc, in dispc_ovl_set_burst_size() argument
1246 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, in dispc_ovl_set_burst_size()
1250 static void dispc_configure_burst_sizes(struct dispc_device *dispc) in dispc_configure_burst_sizes() argument
1256 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_configure_burst_sizes()
1257 dispc_ovl_set_burst_size(dispc, i, burst_size); in dispc_configure_burst_sizes()
1258 if (dispc->feat->has_writeback) in dispc_configure_burst_sizes()
1259 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size); in dispc_configure_burst_sizes()
1262 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc, in dispc_ovl_get_burst_size() argument
1266 return dispc->feat->burst_size_unit * 8; in dispc_ovl_get_burst_size()
1269 static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, in dispc_ovl_color_mode_supported() argument
1275 modes = dispc->feat->supported_color_modes[plane]; in dispc_ovl_color_mode_supported()
1285 static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, in dispc_ovl_get_color_modes() argument
1288 return dispc->feat->supported_color_modes[plane]; in dispc_ovl_get_color_modes()
1291 static void dispc_mgr_enable_cpr(struct dispc_device *dispc, in dispc_mgr_enable_cpr() argument
1297 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable); in dispc_mgr_enable_cpr()
1300 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc, in dispc_mgr_set_cpr_coef() argument
1316 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r); in dispc_mgr_set_cpr_coef()
1317 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g); in dispc_mgr_set_cpr_coef()
1318 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b); in dispc_mgr_set_cpr_coef()
1321 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc, in dispc_ovl_set_vid_color_conv() argument
1328 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_vid_color_conv()
1330 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_vid_color_conv()
1333 static void dispc_ovl_enable_replication(struct dispc_device *dispc, in dispc_ovl_enable_replication() argument
1345 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); in dispc_ovl_enable_replication()
1348 static void dispc_mgr_set_size(struct dispc_device *dispc, in dispc_mgr_set_size() argument
1353 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1354 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); in dispc_mgr_set_size()
1356 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); in dispc_mgr_set_size()
1359 static void dispc_init_fifos(struct dispc_device *dispc) in dispc_init_fifos() argument
1367 unit = dispc->feat->buffer_size_unit; in dispc_init_fifos()
1369 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end); in dispc_init_fifos()
1371 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_init_fifos()
1372 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1375 dispc->fifo_size[fifo] = size; in dispc_init_fifos()
1381 dispc->fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1391 if (dispc->feat->gfx_fifo_workaround) { in dispc_init_fifos()
1394 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER); in dispc_init_fifos()
1401 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v); in dispc_init_fifos()
1403 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1404 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1410 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_fifos()
1415 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high, in dispc_init_fifos()
1418 dispc_ovl_set_fifo_threshold(dispc, i, low, high); in dispc_init_fifos()
1421 if (dispc->feat->has_writeback) { in dispc_init_fifos()
1426 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB, in dispc_init_fifos()
1430 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_fifos()
1434 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc, in dispc_ovl_get_fifo_size() argument
1440 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1441 if (dispc->fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1442 size += dispc->fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1448 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, in dispc_ovl_set_fifo_threshold() argument
1455 unit = dispc->feat->buffer_size_unit; in dispc_ovl_set_fifo_threshold()
1463 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1465 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1470 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1472 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1476 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1485 if (dispc_has_feature(dispc, FEAT_PRELOAD) && in dispc_ovl_set_fifo_threshold()
1486 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) in dispc_ovl_set_fifo_threshold()
1487 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane), in dispc_ovl_set_fifo_threshold()
1491 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) in dispc_enable_fifomerge() argument
1493 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { in dispc_enable_fifomerge()
1499 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); in dispc_enable_fifomerge()
1502 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, in dispc_ovl_compute_fifo_thresholds() argument
1511 unsigned int buf_unit = dispc->feat->buffer_size_unit; in dispc_ovl_compute_fifo_thresholds()
1515 burst_size = dispc_ovl_get_burst_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1516 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1520 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_ovl_compute_fifo_thresholds()
1521 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i); in dispc_ovl_compute_fifo_thresholds()
1532 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) { in dispc_ovl_compute_fifo_thresholds()
1549 static void dispc_ovl_set_mflag(struct dispc_device *dispc, in dispc_ovl_set_mflag() argument
1559 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); in dispc_ovl_set_mflag()
1562 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc, in dispc_ovl_set_mflag_threshold() argument
1566 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane), in dispc_ovl_set_mflag_threshold()
1570 static void dispc_init_mflag(struct dispc_device *dispc) in dispc_init_mflag() argument
1584 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, in dispc_init_mflag()
1588 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_mflag()
1589 u32 size = dispc_ovl_get_fifo_size(dispc, i); in dispc_init_mflag()
1590 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1593 dispc_ovl_set_mflag(dispc, i, true); in dispc_init_mflag()
1604 dispc_ovl_set_mflag_threshold(dispc, i, low, high); in dispc_init_mflag()
1607 if (dispc->feat->has_writeback) { in dispc_init_mflag()
1608 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB); in dispc_init_mflag()
1609 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1612 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true); in dispc_init_mflag()
1623 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_mflag()
1627 static void dispc_ovl_set_fir(struct dispc_device *dispc, in dispc_ovl_set_fir() argument
1637 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC, in dispc_ovl_set_fir()
1639 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC, in dispc_ovl_set_fir()
1644 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); in dispc_ovl_set_fir()
1647 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); in dispc_ovl_set_fir()
1651 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu0() argument
1658 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu0()
1660 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu0()
1666 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); in dispc_ovl_set_vid_accu0()
1669 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu1() argument
1676 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu1()
1678 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu1()
1684 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); in dispc_ovl_set_vid_accu1()
1687 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_0() argument
1694 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); in dispc_ovl_set_vid_accu2_0()
1697 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_1() argument
1704 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); in dispc_ovl_set_vid_accu2_1()
1707 static void dispc_ovl_set_scale_param(struct dispc_device *dispc, in dispc_ovl_set_scale_param() argument
1719 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps, in dispc_ovl_set_scale_param()
1721 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp); in dispc_ovl_set_scale_param()
1724 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc, in dispc_ovl_set_accu_uv() argument
1809 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0); in dispc_ovl_set_accu_uv()
1810 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1); in dispc_ovl_set_accu_uv()
1813 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc, in dispc_ovl_set_scaling_common() argument
1825 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_common()
1828 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_scaling_common()
1837 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) { in dispc_ovl_set_scaling_common()
1844 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) { in dispc_ovl_set_scaling_common()
1849 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_ovl_set_scaling_common()
1864 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0); in dispc_ovl_set_scaling_common()
1865 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1); in dispc_ovl_set_scaling_common()
1868 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, in dispc_ovl_set_scaling_uv() argument
1883 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) in dispc_ovl_set_scaling_uv()
1889 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1894 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width, in dispc_ovl_set_scaling_uv()
1937 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_uv()
1942 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1946 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); in dispc_ovl_set_scaling_uv()
1948 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); in dispc_ovl_set_scaling_uv()
1951 static void dispc_ovl_set_scaling(struct dispc_device *dispc, in dispc_ovl_set_scaling() argument
1961 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1965 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1970 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc, in dispc_ovl_set_rotation_attrs() argument
2027 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); in dispc_ovl_set_rotation_attrs()
2028 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE)) in dispc_ovl_set_rotation_attrs()
2029 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2032 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) { in dispc_ovl_set_rotation_attrs()
2039 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2161 * So, atleast DS-2 lines must have already been fetched by DISPC in check_horiz_timing_omap3()
2277 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_24xx() argument
2291 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_24xx()
2298 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2301 *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_24xx()
2326 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_34xx() argument
2339 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_34xx()
2356 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2370 !*core_clk || *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_34xx()
2414 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_44xx() argument
2428 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_44xx()
2429 const int maxdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling_44xx()
2434 in_width_max = dispc_core_clk_rate(dispc) in dispc_ovl_calc_scaling_44xx()
2473 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2481 static int dispc_ovl_calc_scaling(struct dispc_device *dispc, in dispc_ovl_calc_scaling() argument
2493 int maxhdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2494 int maxvdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2502 if (dispc->feat->supported_scaler_color_modes) { in dispc_ovl_calc_scaling()
2503 const u32 *modes = dispc->feat->supported_scaler_color_modes; in dispc_ovl_calc_scaling()
2542 dispc_has_feature(dispc, FEAT_BURST_2D)) ? in dispc_ovl_calc_scaling()
2555 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, in dispc_ovl_calc_scaling()
2575 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2577 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) { in dispc_ovl_calc_scaling()
2581 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2590 static int dispc_ovl_setup_common(struct dispc_device *dispc, in dispc_ovl_setup_common() argument
2615 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); in dispc_ovl_setup_common()
2616 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); in dispc_ovl_setup_common()
2651 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc)) in dispc_ovl_setup_common()
2654 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width, in dispc_ovl_setup_common()
2716 dispc_ovl_set_color_mode(dispc, plane, fourcc); in dispc_ovl_setup_common()
2718 dispc_ovl_configure_burst_type(dispc, plane, rotation_type); in dispc_ovl_setup_common()
2720 if (dispc->feat->reverse_ilace_field_order) in dispc_ovl_setup_common()
2723 dispc_ovl_set_ba0(dispc, plane, paddr + offset0); in dispc_ovl_setup_common()
2724 dispc_ovl_set_ba1(dispc, plane, paddr + offset1); in dispc_ovl_setup_common()
2727 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0); in dispc_ovl_setup_common()
2728 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1); in dispc_ovl_setup_common()
2731 if (dispc->feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2734 dispc_ovl_set_row_inc(dispc, plane, row_inc); in dispc_ovl_setup_common()
2735 dispc_ovl_set_pix_inc(dispc, plane, pix_inc); in dispc_ovl_setup_common()
2740 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y); in dispc_ovl_setup_common()
2742 dispc_ovl_set_input_size(dispc, plane, in_width, in_height); in dispc_ovl_setup_common()
2745 dispc_ovl_set_scaling(dispc, plane, in_width, in_height, in dispc_ovl_setup_common()
2748 dispc_ovl_set_output_size(dispc, plane, out_width, out_height); in dispc_ovl_setup_common()
2749 dispc_ovl_set_vid_color_conv(dispc, plane, cconv); in dispc_ovl_setup_common()
2752 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type, in dispc_ovl_setup_common()
2755 dispc_ovl_set_zorder(dispc, plane, caps, zorder); in dispc_ovl_setup_common()
2756 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha); in dispc_ovl_setup_common()
2757 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha); in dispc_ovl_setup_common()
2759 dispc_ovl_enable_replication(dispc, plane, caps, replication); in dispc_ovl_setup_common()
2764 static int dispc_ovl_setup(struct dispc_device *dispc, in dispc_ovl_setup() argument
2771 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; in dispc_ovl_setup()
2780 dispc_ovl_set_channel_out(dispc, plane, channel); in dispc_ovl_setup()
2782 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2791 static int dispc_wb_setup(struct dispc_device *dispc, in dispc_wb_setup() argument
2815 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, in dispc_wb_setup()
2840 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_wb_setup()
2848 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_wb_setup()
2852 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); in dispc_wb_setup()
2868 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); in dispc_wb_setup()
2874 static bool dispc_has_writeback(struct dispc_device *dispc) in dispc_has_writeback() argument
2876 return dispc->feat->has_writeback; in dispc_has_writeback()
2879 static int dispc_ovl_enable(struct dispc_device *dispc, in dispc_ovl_enable() argument
2884 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); in dispc_ovl_enable()
2889 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc, in dispc_lcd_enable_signal_polarity() argument
2892 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL)) in dispc_lcd_enable_signal_polarity()
2895 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); in dispc_lcd_enable_signal_polarity()
2898 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable) in dispc_lcd_enable_signal() argument
2900 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL)) in dispc_lcd_enable_signal()
2903 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); in dispc_lcd_enable_signal()
2906 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable) in dispc_pck_free_enable() argument
2908 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE)) in dispc_pck_free_enable()
2911 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); in dispc_pck_free_enable()
2914 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc, in dispc_mgr_enable_fifohandcheck() argument
2918 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); in dispc_mgr_enable_fifohandcheck()
2922 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc, in dispc_mgr_set_lcd_type_tft() argument
2925 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1); in dispc_mgr_set_lcd_type_tft()
2928 static void dispc_set_loadmode(struct dispc_device *dispc, in dispc_set_loadmode() argument
2931 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); in dispc_set_loadmode()
2935 static void dispc_mgr_set_default_color(struct dispc_device *dispc, in dispc_mgr_set_default_color() argument
2938 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color); in dispc_mgr_set_default_color()
2941 static void dispc_mgr_set_trans_key(struct dispc_device *dispc, in dispc_mgr_set_trans_key() argument
2946 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type); in dispc_mgr_set_trans_key()
2948 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key); in dispc_mgr_set_trans_key()
2951 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc, in dispc_mgr_enable_trans_key() argument
2954 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable); in dispc_mgr_enable_trans_key()
2957 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, in dispc_mgr_enable_alpha_fixed_zorder() argument
2961 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER)) in dispc_mgr_enable_alpha_fixed_zorder()
2965 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); in dispc_mgr_enable_alpha_fixed_zorder()
2967 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); in dispc_mgr_enable_alpha_fixed_zorder()
2970 static void dispc_mgr_setup(struct dispc_device *dispc, in dispc_mgr_setup() argument
2974 dispc_mgr_set_default_color(dispc, channel, info->default_color); in dispc_mgr_setup()
2975 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, in dispc_mgr_setup()
2977 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); in dispc_mgr_setup()
2978 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel, in dispc_mgr_setup()
2980 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_mgr_setup()
2981 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); in dispc_mgr_setup()
2982 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); in dispc_mgr_setup()
2986 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc, in dispc_mgr_set_tft_data_lines() argument
3010 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code); in dispc_mgr_set_tft_data_lines()
3013 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc, in dispc_mgr_set_io_pad_mode() argument
3037 l = dispc_read_reg(dispc, DISPC_CONTROL); in dispc_mgr_set_io_pad_mode()
3040 dispc_write_reg(dispc, DISPC_CONTROL, l); in dispc_mgr_set_io_pad_mode()
3043 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, in dispc_mgr_enable_stallmode() argument
3046 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable); in dispc_mgr_enable_stallmode()
3049 static void dispc_mgr_set_lcd_config(struct dispc_device *dispc, in dispc_mgr_set_lcd_config() argument
3053 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); in dispc_mgr_set_lcd_config()
3055 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); in dispc_mgr_set_lcd_config()
3056 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
3058 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); in dispc_mgr_set_lcd_config()
3060 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); in dispc_mgr_set_lcd_config()
3062 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
3064 dispc_mgr_set_lcd_type_tft(dispc, channel); in dispc_mgr_set_lcd_config()
3067 static bool _dispc_mgr_size_ok(struct dispc_device *dispc, in _dispc_mgr_size_ok() argument
3070 return width <= dispc->feat->mgr_width_max && in _dispc_mgr_size_ok()
3071 height <= dispc->feat->mgr_height_max; in _dispc_mgr_size_ok()
3074 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc, in _dispc_lcd_timings_ok() argument
3078 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3079 hfp < 1 || hfp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3080 hbp < 1 || hbp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3081 vsw < 1 || vsw > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3082 vfp < 0 || vfp > dispc->feat->vp_max || in _dispc_lcd_timings_ok()
3083 vbp < 0 || vbp > dispc->feat->vp_max) in _dispc_lcd_timings_ok()
3088 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, in _dispc_mgr_pclk_ok() argument
3093 return pclk <= dispc->feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
3095 return pclk <= dispc->feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
3098 static int dispc_mgr_check_timings(struct dispc_device *dispc, in dispc_mgr_check_timings() argument
3102 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) in dispc_mgr_check_timings()
3105 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) in dispc_mgr_check_timings()
3113 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, in dispc_mgr_check_timings()
3123 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc, in _dispc_mgr_set_lcd_timings() argument
3130 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3131 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3132 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3133 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3134 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3135 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3137 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h); in _dispc_mgr_set_lcd_timings()
3138 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v); in _dispc_mgr_set_lcd_timings()
3155 if (dispc->feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3158 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l); in _dispc_mgr_set_lcd_timings()
3160 if (dispc->syscon_pol) { in _dispc_mgr_set_lcd_timings()
3175 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3191 static void dispc_mgr_set_timings(struct dispc_device *dispc, in dispc_mgr_set_timings() argument
3201 if (dispc_mgr_check_timings(dispc, channel, &t)) { in dispc_mgr_set_timings()
3207 _dispc_mgr_set_lcd_timings(dispc, channel, &t); in dispc_mgr_set_timings()
3231 if (dispc->feat->supports_double_pixel) in dispc_mgr_set_timings()
3232 REG_FLD_MOD(dispc, DISPC_CONTROL, in dispc_mgr_set_timings()
3237 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive); in dispc_mgr_set_timings()
3240 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_set_lcd_divisor() argument
3247 dispc_write_reg(dispc, DISPC_DIVISORo(channel), in dispc_mgr_set_lcd_divisor()
3250 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) && in dispc_mgr_set_lcd_divisor()
3252 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor()
3255 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_get_lcd_divisor() argument
3260 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_get_lcd_divisor()
3265 static unsigned long dispc_fclk_rate(struct dispc_device *dispc) in dispc_fclk_rate() argument
3270 src = dss_get_dispc_clk_source(dispc->dss); in dispc_fclk_rate()
3273 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_fclk_rate()
3278 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_fclk_rate()
3287 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, in dispc_mgr_lclk_rate() argument
3296 return dispc_fclk_rate(dispc); in dispc_mgr_lclk_rate()
3298 src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_mgr_lclk_rate()
3301 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_mgr_lclk_rate()
3306 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_mgr_lclk_rate()
3312 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_lclk_rate()
3317 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, in dispc_mgr_pclk_rate() argument
3326 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_pclk_rate()
3330 r = dispc_mgr_lclk_rate(dispc, channel); in dispc_mgr_pclk_rate()
3334 return dispc->tv_pclk_rate; in dispc_mgr_pclk_rate()
3338 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk) in dispc_set_tv_pclk() argument
3340 dispc->tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3343 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc) in dispc_core_clk_rate() argument
3345 return dispc->core_clk_rate; in dispc_core_clk_rate()
3348 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, in dispc_plane_pclk_rate() argument
3356 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_pclk_rate()
3358 return dispc_mgr_pclk_rate(dispc, channel); in dispc_plane_pclk_rate()
3361 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, in dispc_plane_lclk_rate() argument
3369 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_lclk_rate()
3371 return dispc_mgr_lclk_rate(dispc, channel); in dispc_plane_lclk_rate()
3374 static void dispc_dump_clocks_channel(struct dispc_device *dispc, in dispc_dump_clocks_channel() argument
3383 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_dump_clocks_channel()
3388 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd); in dispc_dump_clocks_channel()
3391 dispc_mgr_lclk_rate(dispc, channel), lcd); in dispc_dump_clocks_channel()
3393 dispc_mgr_pclk_rate(dispc, channel), pcd); in dispc_dump_clocks_channel()
3396 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s) in dispc_dump_clocks() argument
3402 if (dispc_runtime_get(dispc)) in dispc_dump_clocks()
3405 seq_printf(s, "- DISPC -\n"); in dispc_dump_clocks()
3407 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); in dispc_dump_clocks()
3408 seq_printf(s, "dispc fclk source = %s\n", in dispc_dump_clocks()
3411 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); in dispc_dump_clocks()
3413 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in dispc_dump_clocks()
3414 seq_printf(s, "- DISPC-CORE-CLK -\n"); in dispc_dump_clocks()
3415 l = dispc_read_reg(dispc, DISPC_DIVISOR); in dispc_dump_clocks()
3419 (dispc_fclk_rate(dispc)/lcd), lcd); in dispc_dump_clocks()
3422 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD); in dispc_dump_clocks()
3424 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_dump_clocks()
3425 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2); in dispc_dump_clocks()
3426 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_dump_clocks()
3427 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3); in dispc_dump_clocks()
3429 dispc_runtime_put(dispc); in dispc_dump_clocks()
3434 struct dispc_device *dispc = s->private; in dispc_dump_regs() local
3451 #define DUMPREG(dispc, r) \ in dispc_dump_regs() argument
3452 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) in dispc_dump_regs()
3454 if (dispc_runtime_get(dispc)) in dispc_dump_regs()
3457 /* DISPC common registers */ in dispc_dump_regs()
3458 DUMPREG(dispc, DISPC_REVISION); in dispc_dump_regs()
3459 DUMPREG(dispc, DISPC_SYSCONFIG); in dispc_dump_regs()
3460 DUMPREG(dispc, DISPC_SYSSTATUS); in dispc_dump_regs()
3461 DUMPREG(dispc, DISPC_IRQSTATUS); in dispc_dump_regs()
3462 DUMPREG(dispc, DISPC_IRQENABLE); in dispc_dump_regs()
3463 DUMPREG(dispc, DISPC_CONTROL); in dispc_dump_regs()
3464 DUMPREG(dispc, DISPC_CONFIG); in dispc_dump_regs()
3465 DUMPREG(dispc, DISPC_CAPABLE); in dispc_dump_regs()
3466 DUMPREG(dispc, DISPC_LINE_STATUS); in dispc_dump_regs()
3467 DUMPREG(dispc, DISPC_LINE_NUMBER); in dispc_dump_regs()
3468 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_dump_regs()
3469 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_dump_regs()
3470 DUMPREG(dispc, DISPC_GLOBAL_ALPHA); in dispc_dump_regs()
3471 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_dump_regs()
3472 DUMPREG(dispc, DISPC_CONTROL2); in dispc_dump_regs()
3473 DUMPREG(dispc, DISPC_CONFIG2); in dispc_dump_regs()
3475 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_dump_regs()
3476 DUMPREG(dispc, DISPC_CONTROL3); in dispc_dump_regs()
3477 DUMPREG(dispc, DISPC_CONFIG3); in dispc_dump_regs()
3479 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3480 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE); in dispc_dump_regs()
3485 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ in dispc_dump_regs() argument
3487 dispc_read_reg(dispc, DISPC_REG(i, r))) in dispc_dump_regs()
3491 /* DISPC channel specific registers */ in dispc_dump_regs()
3492 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_dump_regs()
3493 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR); in dispc_dump_regs()
3494 DUMPREG(dispc, i, DISPC_TRANS_COLOR); in dispc_dump_regs()
3495 DUMPREG(dispc, i, DISPC_SIZE_MGR); in dispc_dump_regs()
3500 DUMPREG(dispc, i, DISPC_TIMING_H); in dispc_dump_regs()
3501 DUMPREG(dispc, i, DISPC_TIMING_V); in dispc_dump_regs()
3502 DUMPREG(dispc, i, DISPC_POL_FREQ); in dispc_dump_regs()
3503 DUMPREG(dispc, i, DISPC_DIVISORo); in dispc_dump_regs()
3505 DUMPREG(dispc, i, DISPC_DATA_CYCLE1); in dispc_dump_regs()
3506 DUMPREG(dispc, i, DISPC_DATA_CYCLE2); in dispc_dump_regs()
3507 DUMPREG(dispc, i, DISPC_DATA_CYCLE3); in dispc_dump_regs()
3509 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_dump_regs()
3510 DUMPREG(dispc, i, DISPC_CPR_COEF_R); in dispc_dump_regs()
3511 DUMPREG(dispc, i, DISPC_CPR_COEF_G); in dispc_dump_regs()
3512 DUMPREG(dispc, i, DISPC_CPR_COEF_B); in dispc_dump_regs()
3518 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3519 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3520 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3521 DUMPREG(dispc, i, DISPC_OVL_POSITION); in dispc_dump_regs()
3522 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3523 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3524 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3525 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3526 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3527 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3529 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_dump_regs()
3530 DUMPREG(dispc, i, DISPC_OVL_PRELOAD); in dispc_dump_regs()
3531 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3532 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3535 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP); in dispc_dump_regs()
3536 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA); in dispc_dump_regs()
3540 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3541 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3542 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3543 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3544 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3545 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3546 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3547 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3548 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3549 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3551 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3552 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3555 if (dispc->feat->has_writeback) { in dispc_dump_regs()
3557 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3558 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3559 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3560 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3561 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3562 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3563 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3564 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3566 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3567 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3569 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3570 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3571 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3572 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3573 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3574 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3575 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3576 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3577 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3578 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3580 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3581 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3588 #define DUMPREG(dispc, plane, name, i) \ in dispc_dump_regs() argument
3591 dispc_read_reg(dispc, DISPC_REG(plane, name, i))) in dispc_dump_regs()
3596 for (i = 1; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3598 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j); in dispc_dump_regs()
3601 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j); in dispc_dump_regs()
3604 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j); in dispc_dump_regs()
3606 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_dump_regs()
3608 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j); in dispc_dump_regs()
3611 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3613 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j); in dispc_dump_regs()
3616 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j); in dispc_dump_regs()
3619 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j); in dispc_dump_regs()
3623 dispc_runtime_put(dispc); in dispc_dump_regs()
3632 int dispc_calc_clock_rates(struct dispc_device *dispc, in dispc_calc_clock_rates() argument
3647 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, in dispc_div_calc() argument
3665 pckd_hw_min = dispc->feat->min_pcd; in dispc_div_calc()
3668 lck_max = dss_get_max_fck_rate(dispc->dss); in dispc_div_calc()
3686 * For OMAP2/3 the DISPC fclk is the same as LCD's logic in dispc_div_calc()
3687 * clock, which means we're configuring DISPC fclk here in dispc_div_calc()
3689 * OMAP4+ the DISPC fclk is a separate clock. in dispc_div_calc()
3691 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_div_calc()
3692 fck = dispc_core_clk_rate(dispc); in dispc_div_calc()
3707 void dispc_mgr_set_clock_div(struct dispc_device *dispc, in dispc_mgr_set_clock_div() argument
3714 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, in dispc_mgr_set_clock_div()
3718 int dispc_mgr_get_clock_div(struct dispc_device *dispc, in dispc_mgr_get_clock_div() argument
3724 fck = dispc_fclk_rate(dispc); in dispc_mgr_get_clock_div()
3726 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
3727 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); in dispc_mgr_get_clock_div()
3735 static u32 dispc_read_irqstatus(struct dispc_device *dispc) in dispc_read_irqstatus() argument
3737 return dispc_read_reg(dispc, DISPC_IRQSTATUS); in dispc_read_irqstatus()
3740 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) in dispc_clear_irqstatus() argument
3742 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); in dispc_clear_irqstatus()
3745 static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) in dispc_write_irqenable() argument
3747 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3750 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); in dispc_write_irqenable()
3752 dispc_write_reg(dispc, DISPC_IRQENABLE, mask); in dispc_write_irqenable()
3755 dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3758 void dispc_enable_sidle(struct dispc_device *dispc) in dispc_enable_sidle() argument
3761 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); in dispc_enable_sidle()
3764 void dispc_disable_sidle(struct dispc_device *dispc) in dispc_disable_sidle() argument
3766 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ in dispc_disable_sidle()
3769 static u32 dispc_mgr_gamma_size(struct dispc_device *dispc, in dispc_mgr_gamma_size() argument
3774 if (!dispc->feat->has_gamma_table) in dispc_mgr_gamma_size()
3780 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc, in dispc_mgr_write_gamma_table() argument
3784 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_write_gamma_table()
3797 dispc_write_reg(dispc, gdesc->reg, v); in dispc_mgr_write_gamma_table()
3801 static void dispc_restore_gamma_tables(struct dispc_device *dispc) in dispc_restore_gamma_tables() argument
3805 if (!dispc->feat->has_gamma_table) in dispc_restore_gamma_tables()
3808 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD); in dispc_restore_gamma_tables()
3810 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT); in dispc_restore_gamma_tables()
3812 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_gamma_tables()
3813 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2); in dispc_restore_gamma_tables()
3815 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_gamma_tables()
3816 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3); in dispc_restore_gamma_tables()
3824 static void dispc_mgr_set_gamma(struct dispc_device *dispc, in dispc_mgr_set_gamma() argument
3830 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_set_gamma()
3836 if (!dispc->feat->has_gamma_table) in dispc_mgr_set_gamma()
3868 if (dispc->is_enabled) in dispc_mgr_set_gamma()
3869 dispc_mgr_write_gamma_table(dispc, channel); in dispc_mgr_set_gamma()
3872 static int dispc_init_gamma_tables(struct dispc_device *dispc) in dispc_init_gamma_tables() argument
3876 if (!dispc->feat->has_gamma_table) in dispc_init_gamma_tables()
3879 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { in dispc_init_gamma_tables()
3884 !dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_init_gamma_tables()
3888 !dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_init_gamma_tables()
3891 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, in dispc_init_gamma_tables()
3896 dispc->gamma_table[channel] = gt; in dispc_init_gamma_tables()
3898 dispc_mgr_set_gamma(dispc, channel, NULL, 0); in dispc_init_gamma_tables()
3903 static void _omap_dispc_initial_config(struct dispc_device *dispc) in _omap_dispc_initial_config() argument
3908 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in _omap_dispc_initial_config()
3909 l = dispc_read_reg(dispc, DISPC_DIVISOR); in _omap_dispc_initial_config()
3913 dispc_write_reg(dispc, DISPC_DIVISOR, l); in _omap_dispc_initial_config()
3915 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config()
3919 if (dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3920 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); in _omap_dispc_initial_config()
3924 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables. in _omap_dispc_initial_config()
3926 if (dispc_has_feature(dispc, FEAT_FUNCGATED) || in _omap_dispc_initial_config()
3927 dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3928 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); in _omap_dispc_initial_config()
3930 dispc_setup_color_conv_coef(dispc); in _omap_dispc_initial_config()
3932 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY); in _omap_dispc_initial_config()
3934 dispc_init_fifos(dispc); in _omap_dispc_initial_config()
3936 dispc_configure_burst_sizes(dispc); in _omap_dispc_initial_config()
3938 dispc_ovl_enable_zorder_planes(dispc); in _omap_dispc_initial_config()
3940 if (dispc->feat->mstandby_workaround) in _omap_dispc_initial_config()
3941 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); in _omap_dispc_initial_config()
3943 if (dispc_has_feature(dispc, FEAT_MFLAG)) in _omap_dispc_initial_config()
3944 dispc_init_mflag(dispc); in _omap_dispc_initial_config()
4229 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler
4474 struct dispc_device *dispc = arg; in dispc_irq_handler() local
4476 if (!dispc->is_enabled) in dispc_irq_handler()
4479 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler()
4482 static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, in dispc_request_irq() argument
4487 if (dispc->user_handler != NULL) in dispc_request_irq()
4490 dispc->user_handler = handler; in dispc_request_irq()
4491 dispc->user_data = dev_id; in dispc_request_irq()
4496 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, in dispc_request_irq()
4497 IRQF_SHARED, "OMAP DISPC", dispc); in dispc_request_irq()
4499 dispc->user_handler = NULL; in dispc_request_irq()
4500 dispc->user_data = NULL; in dispc_request_irq()
4506 static void dispc_free_irq(struct dispc_device *dispc, void *dev_id) in dispc_free_irq() argument
4508 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq()
4510 dispc->user_handler = NULL; in dispc_free_irq()
4511 dispc->user_data = NULL; in dispc_free_irq()
4514 static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc) in dispc_get_memory_bandwidth_limit() argument
4519 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", in dispc_get_memory_bandwidth_limit()
4526 * Workaround for errata i734 in DSS dispc
4596 static int dispc_errata_i734_wa_init(struct dispc_device *dispc) in dispc_errata_i734_wa_init() argument
4598 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_init()
4604 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, in dispc_errata_i734_wa_init()
4607 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", in dispc_errata_i734_wa_init()
4615 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc) in dispc_errata_i734_wa_fini() argument
4617 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_fini()
4620 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, in dispc_errata_i734_wa_fini()
4624 static void dispc_errata_i734_wa(struct dispc_device *dispc) in dispc_errata_i734_wa() argument
4626 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc, in dispc_errata_i734_wa()
4633 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa()
4636 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); in dispc_errata_i734_wa()
4643 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); in dispc_errata_i734_wa()
4646 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false, in dispc_errata_i734_wa()
4648 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true); in dispc_errata_i734_wa()
4651 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri); in dispc_errata_i734_wa()
4652 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), in dispc_errata_i734_wa()
4654 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf); in dispc_errata_i734_wa()
4655 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm); in dispc_errata_i734_wa()
4657 dispc_clear_irqstatus(dispc, framedone_irq); in dispc_errata_i734_wa()
4660 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true); in dispc_errata_i734_wa()
4661 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false); in dispc_errata_i734_wa()
4668 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) { in dispc_errata_i734_wa()
4670 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", in dispc_errata_i734_wa()
4675 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false); in dispc_errata_i734_wa()
4678 dispc_clear_irqstatus(dispc, 0xffffffff); in dispc_errata_i734_wa()
4681 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); in dispc_errata_i734_wa()
4725 /* DISPC HW IP initialisation */
4727 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
4728 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats },
4729 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats },
4730 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats },
4731 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats },
4749 struct dispc_device *dispc; in dispc_bind() local
4755 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); in dispc_bind()
4756 if (!dispc) in dispc_bind()
4759 dispc->pdev = pdev; in dispc_bind()
4760 platform_set_drvdata(pdev, dispc); in dispc_bind()
4761 dispc->dss = dss; in dispc_bind()
4769 dispc->feat = soc->data; in dispc_bind()
4771 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data; in dispc_bind()
4773 r = dispc_errata_i734_wa_init(dispc); in dispc_bind()
4777 dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0); in dispc_bind()
4778 dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem); in dispc_bind()
4779 if (IS_ERR(dispc->base)) { in dispc_bind()
4780 r = PTR_ERR(dispc->base); in dispc_bind()
4784 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind()
4785 if (dispc->irq < 0) { in dispc_bind()
4792 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4793 if (IS_ERR(dispc->syscon_pol)) { in dispc_bind()
4795 r = PTR_ERR(dispc->syscon_pol); in dispc_bind()
4800 &dispc->syscon_pol_offset)) { in dispc_bind()
4807 r = dispc_init_gamma_tables(dispc); in dispc_bind()
4813 r = dispc_runtime_get(dispc); in dispc_bind()
4817 _omap_dispc_initial_config(dispc); in dispc_bind()
4819 rev = dispc_read_reg(dispc, DISPC_REVISION); in dispc_bind()
4820 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", in dispc_bind()
4823 dispc_runtime_put(dispc); in dispc_bind()
4825 dss->dispc = dispc; in dispc_bind()
4828 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, in dispc_bind()
4829 dispc); in dispc_bind()
4836 kfree(dispc); in dispc_bind()
4842 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_unbind() local
4843 struct dss_device *dss = dispc->dss; in dispc_unbind()
4845 dss_debugfs_remove_file(dispc->debugfs); in dispc_unbind()
4847 dss->dispc = NULL; in dispc_unbind()
4852 dispc_errata_i734_wa_fini(dispc); in dispc_unbind()
4854 kfree(dispc); in dispc_unbind()
4875 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_suspend() local
4877 dispc->is_enabled = false; in dispc_runtime_suspend()
4880 /* wait for current handler to finish before turning the DISPC off */ in dispc_runtime_suspend()
4881 synchronize_irq(dispc->irq); in dispc_runtime_suspend()
4883 dispc_save_context(dispc); in dispc_runtime_suspend()
4890 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_resume() local
4898 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { in dispc_runtime_resume()
4899 _omap_dispc_initial_config(dispc); in dispc_runtime_resume()
4901 dispc_errata_i734_wa(dispc); in dispc_runtime_resume()
4903 dispc_restore_context(dispc); in dispc_runtime_resume()
4905 dispc_restore_gamma_tables(dispc); in dispc_runtime_resume()
4908 dispc->is_enabled = true; in dispc_runtime_resume()