106 	priv->dispc_ops->mgr_enable(priv->dispc, channel, true);  in omap_crtc_dss_start_update()
131 		priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);  in omap_crtc_set_enabled()
144 	framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,  in omap_crtc_set_enabled()
146 	vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);  in omap_crtc_set_enabled()
153 		 * FRAMEDONE to know that DISPC has finished with the output.  in omap_crtc_set_enabled()
166 	priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);  in omap_crtc_set_enabled()
189 	priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,  in omap_crtc_dss_enable()
224 	priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,  in omap_crtc_dss_set_lcd_config()
300 	 * If the dispc is busy we're racing the flush operation. Try again on  in omap_crtc_vblank_irq()
303 	if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {  in omap_crtc_vblank_irq()
407 	priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);  in omap_crtc_write_crtc_properties()
448 	priv->dispc_ops->runtime_get(priv->dispc);  in omap_crtc_atomic_enable()
487 	priv->dispc_ops->runtime_put(priv->dispc);  in omap_crtc_atomic_disable()
502 	 * valid DISPC mode. DSI will calculate and configure the  in omap_crtc_mode_valid()
503 	 * proper DISPC mode later.  in omap_crtc_mode_valid()
507 		r = priv->dispc_ops->mgr_check_timings(priv->dispc,  in omap_crtc_mode_valid()
623 		priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,  in omap_crtc_atomic_flush()
648 	priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);  in omap_crtc_atomic_flush()
832 	/* The dispc API adapts to what ever size, but the HW supports  in omap_crtc_init()
839 	if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {  in omap_crtc_init()