Lines Matching +full:0 +full:x55c
24 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
25 * 0x8860 0xa1
26 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
27 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
28 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
29 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
30 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
65 module_param(force_id, ushort, 0);
74 #define W83627EHF_LD_HWM 0x0b
75 #define W83667HG_LD_VID 0x0d
77 #define SIO_REG_LDSEL 0x07 /* Logical device select */
78 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
79 #define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
80 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
81 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
82 #define SIO_REG_VID_CTRL 0xF0 /* VID control */
83 #define SIO_REG_VID_DATA 0xF1 /* VID data */
85 #define SIO_W83627EHF_ID 0x8850
86 #define SIO_W83627EHG_ID 0x8860
87 #define SIO_W83627DHG_ID 0xa020
88 #define SIO_W83627DHG_P_ID 0xb070
89 #define SIO_W83627UHG_ID 0xa230
90 #define SIO_W83667HG_ID 0xa510
91 #define SIO_W83667HG_B_ID 0xb350
92 #define SIO_ID_MASK 0xFFF0
121 outb(0x87, ioreg); in superio_enter()
122 outb(0x87, ioreg); in superio_enter()
124 return 0; in superio_enter()
130 outb(0xaa, ioreg); in superio_exit()
131 outb(0x02, ioreg); in superio_exit()
132 outb(0x02, ioreg + 1); in superio_exit()
143 #define ADDR_REG_OFFSET 0
146 #define W83627EHF_REG_BANK 0x4E
147 #define W83627EHF_REG_CONFIG 0x40
151 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
152 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
153 * REG_MAN_ID is at port 0x4f
154 * REG_CHIP_ID is at port 0x58
157 static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
158 static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
161 #define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
162 (0x554 + (((nr) - 7) * 2)))
163 #define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
164 (0x555 + (((nr) - 7) * 2)))
165 #define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
166 (0x550 + (nr) - 7))
168 static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
169 static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
170 static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
171 static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
174 #define W83627EHF_REG_FANDIV1 0x47
175 #define W83627EHF_REG_FANDIV2 0x4B
176 #define W83627EHF_REG_VBAT 0x5D
177 #define W83627EHF_REG_DIODE 0x59
178 #define W83627EHF_REG_SMI_OVT 0x4C
180 #define W83627EHF_REG_ALARM1 0x459
181 #define W83627EHF_REG_ALARM2 0x45A
182 #define W83627EHF_REG_ALARM3 0x45B
184 #define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
185 #define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
188 #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
189 #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
193 0x04, /* SYS FAN0 output mode and PWM mode */
194 0x04, /* CPU FAN0 output mode and PWM mode */
195 0x12, /* AUX FAN mode */
196 0x62, /* CPU FAN1 mode */
199 static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
203 static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
204 static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
205 static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
208 static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
209 static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
210 static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
213 = { 0xff, 0x67, 0xff, 0x69 };
215 = { 0xff, 0x68, 0xff, 0x6a };
217 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
219 = { 0x68, 0x6a, 0x6c };
221 static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
238 return ((((reg & 0xff00) == 0x100 in is_word_sized()
239 || (reg & 0xff00) == 0x200) in is_word_sized()
240 && ((reg & 0x00ff) == 0x50 in is_word_sized()
241 || (reg & 0x00ff) == 0x53 in is_word_sized()
242 || (reg & 0x00ff) == 0x55)) in is_word_sized()
243 || (reg & 0xfff0) == 0x630 in is_word_sized()
244 || reg == 0x640 || reg == 0x642 in is_word_sized()
245 || ((reg & 0xfff0) == 0x650 in is_word_sized()
246 && (reg & 0x000f) >= 0x06) in is_word_sized()
247 || reg == 0x73 || reg == 0x75 || reg == 0x77 in is_word_sized()
269 if (reg == 0 || reg == 255) in fan_from_reg8()
270 return 0; in fan_from_reg8()
288 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
298 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255); in in_to_reg()
323 char valid; /* !=0 if following fields are valid */
345 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
389 * On older chips, only registers 0x50-0x5f are banked.
411 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); in w83627ehf_read_value()
414 outb_p((reg & 0xff) + 1, in w83627ehf_read_value()
431 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); in w83627ehf_write_value()
434 outb_p((reg & 0xff) + 1, in w83627ehf_write_value()
437 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET); in w83627ehf_write_value()
440 return 0; in w83627ehf_write_value()
469 case 0: in w83627ehf_write_fan_div()
470 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf) in w83627ehf_write_fan_div()
471 | ((data->fan_div[0] & 0x03) << 4); in w83627ehf_write_fan_div()
473 reg |= (data->has_fan & (1 << 4)) ? 1 : 0; in w83627ehf_write_fan_div()
475 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf) in w83627ehf_write_fan_div()
476 | ((data->fan_div[0] & 0x04) << 3); in w83627ehf_write_fan_div()
480 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f) in w83627ehf_write_fan_div()
481 | ((data->fan_div[1] & 0x03) << 6); in w83627ehf_write_fan_div()
483 reg |= (data->has_fan & (1 << 4)) ? 1 : 0; in w83627ehf_write_fan_div()
485 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf) in w83627ehf_write_fan_div()
486 | ((data->fan_div[1] & 0x04) << 4); in w83627ehf_write_fan_div()
490 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f) in w83627ehf_write_fan_div()
491 | ((data->fan_div[2] & 0x03) << 6); in w83627ehf_write_fan_div()
493 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f) in w83627ehf_write_fan_div()
494 | ((data->fan_div[2] & 0x04) << 5); in w83627ehf_write_fan_div()
498 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc) in w83627ehf_write_fan_div()
499 | (data->fan_div[3] & 0x03); in w83627ehf_write_fan_div()
501 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f) in w83627ehf_write_fan_div()
502 | ((data->fan_div[3] & 0x04) << 5); in w83627ehf_write_fan_div()
506 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73) in w83627ehf_write_fan_div()
507 | ((data->fan_div[4] & 0x03) << 2) in w83627ehf_write_fan_div()
508 | ((data->fan_div[4] & 0x04) << 5); in w83627ehf_write_fan_div()
519 data->fan_div[0] = (i >> 4) & 0x03; in w83627ehf_update_fan_div()
520 data->fan_div[1] = (i >> 6) & 0x03; in w83627ehf_update_fan_div()
522 data->fan_div[2] = (i >> 6) & 0x03; in w83627ehf_update_fan_div()
524 data->fan_div[0] |= (i >> 3) & 0x04; in w83627ehf_update_fan_div()
525 data->fan_div[1] |= (i >> 4) & 0x04; in w83627ehf_update_fan_div()
526 data->fan_div[2] |= (i >> 5) & 0x04; in w83627ehf_update_fan_div()
529 data->fan_div[3] = i & 0x03; in w83627ehf_update_fan_div()
530 data->fan_div[4] = ((i >> 2) & 0x03) in w83627ehf_update_fan_div()
531 | ((i >> 5) & 0x04); in w83627ehf_update_fan_div()
535 data->fan_div[3] |= (i >> 5) & 0x04; in w83627ehf_update_fan_div()
542 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */ in w83627ehf_update_pwm()
544 for (i = 0; i < data->pwm_num; i++) { in w83627ehf_update_pwm()
548 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */ in w83627ehf_update_pwm()
556 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1; in w83627ehf_update_pwm()
561 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f; in w83627ehf_update_pwm()
578 for (i = 0; i < data->in_num; i++) { in w83627ehf_update_device()
591 for (i = 0; i < 5; i++) { in w83627ehf_update_device()
609 if (reg >= 0xff && data->fan_div[i] < 0x07) { in w83627ehf_update_device()
628 for (i = 0; i < data->pwm_num; i++) { in w83627ehf_update_device()
643 data->REG_FAN_MAX_OUTPUT[i] != 0xff) in w83627ehf_update_device()
649 data->REG_FAN_STEP_OUTPUT[i] != 0xff) in w83627ehf_update_device()
657 (data->pwm_mode[i] == 1 ? 0x7f : 0xff); in w83627ehf_update_device()
661 for (i = 0; i < NUM_REG_TEMP; i++) { in w83627ehf_update_device()
705 if (val < 0) \
712 return 0; \
725 if (val < 0) in store_in_reg()
751 new_div = 0; /* 1 == (1 << 0) */ in store_in_reg()
754 channel + 1, val, fan_from_reg8(1, 0)); in store_in_reg()
761 new_div = 0; in store_in_reg()
787 return 0; in store_in_reg()
799 return 0; \
814 return 0; in store_temp_offset()
823 if (val < 0 || val > 1) in store_pwm_mode()
834 return 0; in store_pwm_mode()
841 val = clamp_val(val, 0, 255); in store_pwm()
847 return 0; in store_pwm()
856 if (!val || val < 0 || in store_pwm_enable()
864 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[channel]); in store_pwm_enable()
869 return 0; in store_pwm_enable()
897 if (err < 0) in show_tol_temp()
900 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 127); in show_tol_temp()
921 if (err < 0) in store_tolerance()
924 /* Limit the temp to 0C - 15C */ in store_tolerance()
925 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 15); in store_tolerance()
930 reg = (reg & 0x0f) | (val << 4); in store_tolerance()
932 reg = (reg & 0xf0) | val; in store_tolerance()
940 store_target_temp, 0);
949 store_tolerance, 0);
980 if (err < 0) \
1019 if (err < 0) \
1050 store_fan_stop_time, 0);
1054 store_fan_start_output, 0);
1058 store_fan_stop_output, 0);
1068 store_fan_max_output, 0);
1070 store_fan_step_output, 0);
1094 const u16 mask = 0x80; in clear_caseopen()
1097 if (val != 0 || channel != 0) in clear_caseopen()
1104 data->valid = 0; /* Force cache refresh */ in clear_caseopen()
1107 return 0; in clear_caseopen()
1136 data->REG_FAN_STEP_OUTPUT[sda->index] != 0xff) in w83627ehf_attrs_visible()
1162 return 0; in w83627ehf_attrs_visible()
1227 if (!(tmp & 0x01)) in w83627ehf_init_device()
1229 tmp | 0x01); in w83627ehf_init_device()
1232 for (i = 0; i < NUM_REG_TEMP; i++) { in w83627ehf_init_device()
1239 if (tmp & 0x01) in w83627ehf_init_device()
1242 tmp & 0xfe); in w83627ehf_init_device()
1247 if (!(tmp & 0x01)) in w83627ehf_init_device()
1248 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01); in w83627ehf_init_device()
1256 diode = 0x00; in w83627ehf_init_device()
1259 diode = 0x70; in w83627ehf_init_device()
1261 for (i = 0; i < 3; i++) { in w83627ehf_init_device()
1268 if (label && strncmp(label, "PECI", 4) == 0) in w83627ehf_init_device()
1270 else if (label && strncmp(label, "AMD", 3) == 0) in w83627ehf_init_device()
1272 else if ((tmp & (0x02 << i))) in w83627ehf_init_device()
1273 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3; in w83627ehf_init_device()
1284 for (i = 0; i < n_temp; i++) { in w83627ehf_set_temp_reg_ehf()
1300 data->has_fan = 0x03; /* fan1 and fan2 */ in w83627ehf_check_fan_inputs()
1301 data->has_fan_min = 0x03; in w83627ehf_check_fan_inputs()
1308 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40; in w83627ehf_check_fan_inputs()
1309 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20; in w83627ehf_check_fan_inputs()
1312 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06); in w83627ehf_check_fan_inputs()
1313 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02); in w83627ehf_check_fan_inputs()
1316 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */ in w83627ehf_check_fan_inputs()
1346 /* channel 0.., name 1.. */ in w83627ehf_is_visible()
1348 return 0; in w83627ehf_is_visible()
1354 return 0; in w83627ehf_is_visible()
1357 return 0; in w83627ehf_is_visible()
1362 return 0; in w83627ehf_is_visible()
1368 return 0; in w83627ehf_is_visible()
1371 return 0; in w83627ehf_is_visible()
1378 return 0; in w83627ehf_is_visible()
1383 /* channel 0.., name 1.. */ in w83627ehf_is_visible()
1385 return 0; in w83627ehf_is_visible()
1395 return 0; in w83627ehf_is_visible()
1400 /* channel 0.., name 0.. */ in w83627ehf_is_visible()
1402 return 0; in w83627ehf_is_visible()
1404 return 0; in w83627ehf_is_visible()
1412 /* channel 0.., name 1.. */ in w83627ehf_is_visible()
1415 return 0; in w83627ehf_is_visible()
1425 return 0; in w83627ehf_is_visible()
1428 return 0; /* Shouldn't happen */ in w83627ehf_is_visible()
1438 return 0; in w83627ehf_do_read_temp()
1441 return 0; in w83627ehf_do_read_temp()
1444 return 0; in w83627ehf_do_read_temp()
1447 return 0; in w83627ehf_do_read_temp()
1450 return 0; in w83627ehf_do_read_temp()
1455 return 0; in w83627ehf_do_read_temp()
1473 return 0; in w83627ehf_do_read_in()
1477 return 0; in w83627ehf_do_read_in()
1481 return 0; in w83627ehf_do_read_in()
1484 int bit[] = { 0, 1, 2, 3, 8, 21, 20, 16, 17, 19 }; in w83627ehf_do_read_in()
1486 return 0; in w83627ehf_do_read_in()
1502 return 0; in w83627ehf_do_read_fan()
1506 return 0; in w83627ehf_do_read_fan()
1509 return 0; in w83627ehf_do_read_fan()
1514 return 0; in w83627ehf_do_read_fan()
1530 return 0; in w83627ehf_do_read_pwm()
1533 return 0; in w83627ehf_do_read_pwm()
1536 return 0; in w83627ehf_do_read_pwm()
1547 if (attr != hwmon_intrusion_alarm || channel != 0) in w83627ehf_do_read_intrusion()
1550 *val = !!(data->caseopen & 0x10); in w83627ehf_do_read_intrusion()
1551 return 0; in w83627ehf_do_read_intrusion()
1593 return 0; in w83627ehf_read_string()
1704 int i, err = 0; in w83627ehf_probe()
1707 res = platform_get_resource(pdev, IORESOURCE_IO, 0); in w83627ehf_probe()
1710 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", in w83627ehf_probe()
1727 data->bank = 0xff; /* Force initial bank selection */ in w83627ehf_probe()
1747 data->have_temp = 0x07; in w83627ehf_probe()
1756 * Temperature sources are selected with bank 0, registers 0x49 in w83627ehf_probe()
1757 * and 0x4a. in w83627ehf_probe()
1759 reg = w83627ehf_read_value(data, 0x4a); in w83627ehf_probe()
1760 data->temp_src[0] = reg >> 5; in w83627ehf_probe()
1761 reg = w83627ehf_read_value(data, 0x49); in w83627ehf_probe()
1762 data->temp_src[1] = reg & 0x07; in w83627ehf_probe()
1763 data->temp_src[2] = (reg >> 4) & 0x07; in w83627ehf_probe()
1766 * W83667HG-B has another temperature register at 0x7e. in w83627ehf_probe()
1767 * The temperature source is selected with register 0x7d. in w83627ehf_probe()
1771 reg = w83627ehf_read_value(data, 0x7d); in w83627ehf_probe()
1772 reg &= 0x07; in w83627ehf_probe()
1773 if (reg != data->temp_src[0] && reg != data->temp_src[1] in w83627ehf_probe()
1784 if (data->temp_src[2] == 2 && (reg & 0x01)) in w83627ehf_probe()
1792 data->have_temp_offset = data->have_temp & 0x07; in w83627ehf_probe()
1793 for (i = 0; i < 3; i++) { in w83627ehf_probe()
1804 * bank 0, registers 0x49 and 0x4a. in w83627ehf_probe()
1806 data->temp_src[0] = 0; /* SYSTIN */ in w83627ehf_probe()
1807 reg = w83627ehf_read_value(data, 0x49) & 0x07; in w83627ehf_probe()
1809 if (reg == 0) in w83627ehf_probe()
1815 reg = w83627ehf_read_value(data, 0x4a); in w83627ehf_probe()
1823 data->temp_src[2] == data->temp_src[0] || in w83627ehf_probe()
1833 data->have_temp_offset = data->have_temp & 0x03; in w83627ehf_probe()
1834 for (i = 0; i < 3; i++) { in w83627ehf_probe()
1852 if (reg & 0x01) in w83627ehf_probe()
1857 data->have_temp_offset = data->have_temp & 0x07; in w83627ehf_probe()
1892 * 0xe3. in w83627ehf_probe()
1895 data->vid = superio_inb(sio_data->sioreg, 0xe3); in w83627ehf_probe()
1899 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) { in w83627ehf_probe()
1910 if ((en_vrm10 & 0x08) && data->vrm == 90) { in w83627ehf_probe()
1915 en_vrm10 & ~0x08); in w83627ehf_probe()
1916 } else if (!(en_vrm10 & 0x08) in w83627ehf_probe()
1922 en_vrm10 | 0x08); in w83627ehf_probe()
1929 data->vid &= 0x3f; in w83627ehf_probe()
1946 for (i = 0; i < data->pwm_num; i++) in w83627ehf_probe()
1959 return 0; in w83627ehf_probe()
1973 return 0; in w83627ehf_remove()
1985 return 0; in w83627ehf_suspend()
1994 data->bank = 0xff; /* Force initial bank selection */ in w83627ehf_resume()
1997 for (i = 0; i < data->in_num; i++) { in w83627ehf_resume()
2007 for (i = 0; i < 5; i++) { in w83627ehf_resume()
2015 for (i = 0; i < NUM_REG_TEMP; i++) { in w83627ehf_resume()
2037 data->valid = 0; in w83627ehf_resume()
2040 return 0; in w83627ehf_resume()
2119 if (val != 0xffff) in w83627ehf_find()
2120 pr_debug("unsupported chip ID: 0x%04x\n", val); in w83627ehf_find()
2130 if (*addr == 0) { in w83627ehf_find()
2131 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n"); in w83627ehf_find()
2138 if (!(val & 0x01)) { in w83627ehf_find()
2140 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01); in w83627ehf_find()
2147 return 0; in w83627ehf_find()
2169 * driver will probe 0x2e and 0x4e and auto-detect the presence of a in sensors_w83627ehf_init()
2172 if (w83627ehf_find(0x2e, &address, &sio_data) && in sensors_w83627ehf_init()
2173 w83627ehf_find(0x4e, &address, &sio_data)) in sensors_w83627ehf_init()
2194 memset(&res, 0, sizeof(res)); in sensors_w83627ehf_init()
2217 return 0; in sensors_w83627ehf_init()