28 			return 0;  in config_drive_for_dma()
33 	 * UltraDMA (mode 0/1/2/3/4/5/6) enabled  in config_drive_for_dma()
36 	    ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))  in config_drive_for_dma()
43 	if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 ||  in config_drive_for_dma()
44 	    (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)  in config_drive_for_dma()
51 	return 0;  in config_drive_for_dma()
105  *	Most chipsets correctly interpret a length of 0x0000 as 64KB,
110  *	returns 0 otherwise.
119 	unsigned int count = 0;  in ide_build_dmatable()
140 			bcount = 0x10000 - (cur_addr & 0xffff);  in ide_build_dmatable()
144 			xcount = bcount & 0xffff;  in ide_build_dmatable()
147 			else if (xcount == 0x0000) {  in ide_build_dmatable()
150 				*table++ = cpu_to_le32(0x8000);  in ide_build_dmatable()
151 				*table++ = cpu_to_le32(cur_addr + 0x8000);  in ide_build_dmatable()
152 				xcount = 0x8000;  in ide_build_dmatable()
162 			*--table |= cpu_to_le32(0x80000000);  in ide_build_dmatable()
170 	return 0; /* revert to PIO for this request */  in ide_build_dmatable()
184  *	Returns 0 on success. If a PIO fallback is required then 1
191 	u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;  in ide_dma_setup()
192 	u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;  in ide_dma_setup()
196 	if (ide_build_dmatable(drive, cmd) == 0) {  in ide_dma_setup()
220 	return 0;  in ide_dma_setup()
243 	printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",  in ide_dma_sff_timer_expiry()
246 	if ((dma_stat & 0x18) == 0x18)	/* BUSY Stupid Early Timer !! */  in ide_dma_sff_timer_expiry()
260 	return 0;	/* Status is unknown -- reset the bus */  in ide_dma_sff_timer_expiry()
285 /* returns 1 on error, 0 otherwise */
289 	u8 dma_stat = 0, dma_cmd = 0;  in ide_dma_end()
311 		return 0x10 | dma_stat;  in ide_dma_end()
312 	return 0;  in ide_dma_end()
316 /* returns 1 if dma irq issued, 0 otherwise */
322 	return (dma_stat & ATA_DMA_INTR) ? 1 : 0;  in ide_dma_test_irq()