Lines Matching +full:0 +full:x170
24 #define READ_REG 0 /* index of Read cycle timing register */
35 * is at reg_base (0x1f0 primary, 0x170 secondary,
45 outb(0x83, reg_base + 2); in write_reg()
49 * is at reg_base (0x1f0 primary, 0x170 secondary,
55 u8 ret = 0; in read_reg()
61 outb(0x83, reg_base + 2); in read_reg()
76 { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */ in opti621_set_pio_mode()
77 { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */ in opti621_set_pio_mode()
80 { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */ in opti621_set_pio_mode()
81 { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */ in opti621_set_pio_mode()
97 outb(0xc0, reg_base + CNTRL_REG); in opti621_set_pio_mode()
99 outb(0xff, reg_base + 5); in opti621_set_pio_mode()
100 /* if reads 0xff, adapter not exist? */ in opti621_set_pio_mode()
102 /* if reads 0xc0, no interface exist? */ in opti621_set_pio_mode()
113 /* select Index-0/1 for Register-A/B */ in opti621_set_pio_mode()
120 /* use Register-A for drive 0 */ in opti621_set_pio_mode()
122 write_reg(0x85, CNTRL_REG); in opti621_set_pio_mode()
137 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
149 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
150 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
151 { 0, },