Lines Matching full:iommu
19 #include <linux/amd-iommu.h>
24 #include <asm/iommu.h>
97 * structure describing one IOMMU in the ACPI table. Typically followed by one
117 * A device entry describing which devices a specific IOMMU translates and
133 * An AMD IOMMU memory definition structure. It defines things like exclusion
198 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
204 * The rlookup table is used to find the IOMMU which is responsible
217 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
262 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
264 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
268 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
270 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
273 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
277 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
279 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
305 struct amd_iommu *iommu; in check_feature_on_all_iommus() local
307 for_each_iommu(iommu) { in check_feature_on_all_iommus()
308 ret = iommu_feature(iommu, mask); in check_feature_on_all_iommus()
322 static void __init early_iommu_features_init(struct amd_iommu *iommu, in early_iommu_features_init() argument
326 iommu->features = h->efr_reg; in early_iommu_features_init()
331 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
335 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
336 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
340 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
342 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
343 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
344 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
347 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
351 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
352 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
356 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
358 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
359 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
364 * AMD IOMMU MMIO register space handling functions
366 * These functions are used to program the IOMMU device registers in
372 * This function set the exclusion range in the IOMMU. DMA accesses to the
375 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
377 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
378 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
381 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
385 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
393 static void iommu_set_cwwb_range(struct amd_iommu *iommu) in iommu_set_cwwb_range() argument
395 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
398 if (!iommu_feature(iommu, FEATURE_SNP)) in iommu_set_cwwb_range()
405 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
412 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
416 /* Programs the physical address of the device table into the IOMMU hardware */
417 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
421 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
425 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
429 /* Generic functions to enable/disable certain features of the IOMMU. */
430 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
434 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
436 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
439 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
443 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
445 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
448 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
452 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
455 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
459 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
461 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
464 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
466 if (!iommu->mmio_base) in iommu_disable()
470 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
473 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
474 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
476 /* Disable IOMMU GA_LOG */ in iommu_disable()
477 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in iommu_disable()
478 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in iommu_disable()
480 /* Disable IOMMU hardware itself */ in iommu_disable()
481 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
485 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
500 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
502 if (iommu->mmio_base) in iommu_unmap_mmio_space()
503 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
504 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
525 * The functions below belong to the first pass of AMD IOMMU ACPI table
549 * After reading the highest device id from the IOMMU PCI capability header
639 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
646 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
647 * write commands to that buffer later and the IOMMU will execute them
650 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
652 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_command_buffer()
655 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
659 * This function resets the command buffer if the IOMMU stopped fetching
662 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
664 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
666 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
667 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
668 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
669 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
671 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
678 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
682 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
684 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
687 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
690 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
696 static void iommu_disable_command_buffer(struct amd_iommu *iommu) in iommu_disable_command_buffer() argument
698 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable_command_buffer()
701 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
703 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
706 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, in iommu_alloc_4k_pages() argument
713 iommu_feature(iommu, FEATURE_SNP) && in iommu_alloc_4k_pages()
722 /* allocates the memory where the IOMMU will log its events to */
723 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
725 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_event_buffer()
728 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
731 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
735 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
737 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
739 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
743 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
744 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
746 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
752 static void iommu_disable_event_buffer(struct amd_iommu *iommu) in iommu_disable_event_buffer() argument
754 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable_event_buffer()
757 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
759 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
762 /* allocates the memory where the IOMMU will log its events to */
763 static int __init alloc_ppr_log(struct amd_iommu *iommu) in alloc_ppr_log() argument
765 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_ppr_log()
768 return iommu->ppr_log ? 0 : -ENOMEM; in alloc_ppr_log()
771 static void iommu_enable_ppr_log(struct amd_iommu *iommu) in iommu_enable_ppr_log() argument
775 if (iommu->ppr_log == NULL) in iommu_enable_ppr_log()
778 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()
780 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in iommu_enable_ppr_log()
784 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_enable_ppr_log()
785 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_enable_ppr_log()
787 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); in iommu_enable_ppr_log()
788 iommu_feature_enable(iommu, CONTROL_PPR_EN); in iommu_enable_ppr_log()
791 static void __init free_ppr_log(struct amd_iommu *iommu) in free_ppr_log() argument
793 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); in free_ppr_log()
796 static void free_ga_log(struct amd_iommu *iommu) in free_ga_log() argument
799 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
800 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); in free_ga_log()
804 static int iommu_ga_log_enable(struct amd_iommu *iommu) in iommu_ga_log_enable() argument
810 if (!iommu->ga_log) in iommu_ga_log_enable()
814 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
818 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_ga_log_enable()
819 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_ga_log_enable()
821 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_ga_log_enable()
823 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_ga_log_enable()
825 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_ga_log_enable()
826 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_ga_log_enable()
829 iommu_feature_enable(iommu, CONTROL_GAINT_EN); in iommu_ga_log_enable()
830 iommu_feature_enable(iommu, CONTROL_GALOG_EN); in iommu_ga_log_enable()
833 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
844 static int iommu_init_ga_log(struct amd_iommu *iommu) in iommu_init_ga_log() argument
850 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
852 if (!iommu->ga_log) in iommu_init_ga_log()
855 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
857 if (!iommu->ga_log_tail) in iommu_init_ga_log()
862 free_ga_log(iommu); in iommu_init_ga_log()
869 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) in alloc_cwwb_sem() argument
871 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); in alloc_cwwb_sem()
873 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
876 static void __init free_cwwb_sem(struct amd_iommu *iommu) in free_cwwb_sem() argument
878 if (iommu->cmd_sem) in free_cwwb_sem()
879 free_page((unsigned long)iommu->cmd_sem); in free_cwwb_sem()
882 static void iommu_enable_xt(struct amd_iommu *iommu) in iommu_enable_xt() argument
891 iommu_feature_enable(iommu, CONTROL_XT_EN); in iommu_enable_xt()
895 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
897 if (!iommu_feature(iommu, FEATURE_GT)) in iommu_enable_gt()
900 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
927 struct amd_iommu *iommu; in copy_device_table() local
936 for_each_iommu(iommu) { in copy_device_table()
938 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in copy_device_table()
939 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in copy_device_table()
942 pr_err("IOMMU:%d should use the same dev table as others!\n", in copy_device_table()
943 iommu->index); in copy_device_table()
950 pr_err("The device table size of IOMMU:%d is not expected!\n", in copy_device_table()
951 iommu->index); in copy_device_table()
1032 /* Writes the specific IOMMU for a device into the rlookup table */
1033 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) in set_iommu_for_device() argument
1035 amd_iommu_rlookup_table[devid] = iommu; in set_iommu_for_device()
1042 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
1062 set_iommu_for_device(iommu, devid); in set_dev_entry_from_acpi()
1173 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1176 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
1198 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1222 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); in init_iommu_from_acpi()
1234 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1264 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1265 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1297 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1325 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
1328 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
1364 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1429 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1443 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1445 free_cwwb_sem(iommu); in free_iommu_one()
1446 free_command_buffer(iommu); in free_iommu_one()
1447 free_event_buffer(iommu); in free_iommu_one()
1448 free_ppr_log(iommu); in free_iommu_one()
1449 free_ga_log(iommu); in free_iommu_one()
1450 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1455 struct amd_iommu *iommu, *next; in free_iommu_all() local
1457 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1458 list_del(&iommu->list); in free_iommu_all()
1459 free_iommu_one(iommu); in free_iommu_all()
1460 kfree(iommu); in free_iommu_all()
1465 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1470 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1479 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1480 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1486 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1488 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1489 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1492 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1496 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1501 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1511 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1517 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1519 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1523 * This function clues the initialization function for one IOMMU
1525 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1527 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) in init_iommu_one() argument
1531 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1532 iommu->cmd_sem_val = 0; in init_iommu_one()
1534 /* Add IOMMU to internal data structures */ in init_iommu_one()
1535 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1536 iommu->index = amd_iommus_present++; in init_iommu_one()
1538 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1543 /* Index is fine - add IOMMU to the array */ in init_iommu_one()
1544 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1547 * Copy data from ACPI table entry to the iommu struct in init_iommu_one()
1549 iommu->devid = h->devid; in init_iommu_one()
1550 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1551 iommu->pci_seg = h->pci_seg; in init_iommu_one()
1552 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1560 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1562 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1576 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1578 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1593 * the IOMMU MMIO access to MSI capability block registers in init_iommu_one()
1601 early_iommu_features_init(iommu, h); in init_iommu_one()
1608 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1609 iommu->mmio_phys_end); in init_iommu_one()
1610 if (!iommu->mmio_base) in init_iommu_one()
1613 if (alloc_cwwb_sem(iommu)) in init_iommu_one()
1616 if (alloc_command_buffer(iommu)) in init_iommu_one()
1619 if (alloc_event_buffer(iommu)) in init_iommu_one()
1622 iommu->int_enabled = false; in init_iommu_one()
1624 init_translation_status(iommu); in init_iommu_one()
1625 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_iommu_one()
1626 iommu_disable(iommu); in init_iommu_one()
1627 clear_translation_pre_enabled(iommu); in init_iommu_one()
1628 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", in init_iommu_one()
1629 iommu->index); in init_iommu_one()
1632 amd_iommu_pre_enabled = translation_pre_enabled(iommu); in init_iommu_one()
1634 ret = init_iommu_from_acpi(iommu, h); in init_iommu_one()
1638 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one()
1643 * Make sure IOMMU is not considered to translate itself. The IVRS in init_iommu_one()
1646 amd_iommu_rlookup_table[iommu->devid] = NULL; in init_iommu_one()
1678 * Iterates over all IOMMU entries in the ACPI table, allocates the
1679 * IOMMU structure and initializes it with init_iommu_one()
1685 struct amd_iommu *iommu; in init_iommu_all() local
1703 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1704 if (iommu == NULL) in init_iommu_all()
1707 ret = init_iommu_one(iommu, h); in init_iommu_all()
1719 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1722 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1724 if (!iommu_feature(iommu, FEATURE_PC)) in init_iommu_perf_ctr()
1729 pci_info(pdev, "IOMMU performance counters supported\n"); in init_iommu_perf_ctr()
1731 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1732 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1733 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1742 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_cap() local
1743 return sprintf(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
1751 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_features() local
1752 return sprintf(buf, "%llx\n", iommu->features); in amd_iommu_show_features()
1763 .name = "amd-iommu",
1774 * of the IOMMU Extended Feature Register [MMIO Offset 0030h].
1777 static void __init late_iommu_features_init(struct amd_iommu *iommu) in late_iommu_features_init() argument
1781 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) in late_iommu_features_init()
1785 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in late_iommu_features_init()
1787 if (!iommu->features) { in late_iommu_features_init()
1788 iommu->features = features; in late_iommu_features_init()
1796 if (features != iommu->features) in late_iommu_features_init()
1798 features, iommu->features); in late_iommu_features_init()
1801 static int __init iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
1803 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
1806 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
1807 iommu->devid & 0xff); in iommu_init_pci()
1808 if (!iommu->dev) in iommu_init_pci()
1811 /* Prevent binding other PCI device drivers to IOMMU devices */ in iommu_init_pci()
1812 iommu->dev->match_driver = false; in iommu_init_pci()
1814 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
1815 &iommu->cap); in iommu_init_pci()
1817 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
1820 late_iommu_features_init(iommu); in iommu_init_pci()
1822 if (iommu_feature(iommu, FEATURE_GT)) { in iommu_init_pci()
1827 pasmax = iommu->features & FEATURE_PASID_MASK; in iommu_init_pci()
1835 glxval = iommu->features & FEATURE_GLXVAL_MASK; in iommu_init_pci()
1844 if (iommu_feature(iommu, FEATURE_GT) && in iommu_init_pci()
1845 iommu_feature(iommu, FEATURE_PPR)) { in iommu_init_pci()
1846 iommu->is_iommu_v2 = true; in iommu_init_pci()
1850 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) in iommu_init_pci()
1853 ret = iommu_init_ga_log(iommu); in iommu_init_pci()
1857 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) in iommu_init_pci()
1860 init_iommu_perf_ctr(iommu); in iommu_init_pci()
1862 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
1865 iommu->root_pdev = in iommu_init_pci()
1866 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, in iommu_init_pci()
1874 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
1875 &iommu->stored_addr_lo); in iommu_init_pci()
1876 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
1877 &iommu->stored_addr_hi); in iommu_init_pci()
1880 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
1884 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
1887 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
1890 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
1891 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
1893 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
1894 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
1895 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops); in iommu_init_pci()
1896 iommu_device_register(&iommu->iommu); in iommu_init_pci()
1898 return pci_enable_device(iommu->dev); in iommu_init_pci()
1907 struct amd_iommu *iommu; in print_iommu_info() local
1909 for_each_iommu(iommu) { in print_iommu_info()
1910 struct pci_dev *pdev = iommu->dev; in print_iommu_info()
1913 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr); in print_iommu_info()
1915 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { in print_iommu_info()
1916 pr_info("Extended features (%#llx):", iommu->features); in print_iommu_info()
1919 if (iommu_feature(iommu, (1ULL << i))) in print_iommu_info()
1923 if (iommu->features & FEATURE_GAM_VAPIC) in print_iommu_info()
1940 struct amd_iommu *iommu; in amd_iommu_init_pci() local
1943 for_each_iommu(iommu) { in amd_iommu_init_pci()
1944 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
1949 iommu_set_cwwb_range(iommu); in amd_iommu_init_pci()
1966 for_each_iommu(iommu) in amd_iommu_init_pci()
1967 iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
1984 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
1988 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
1992 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
1996 iommu); in iommu_setup_msi()
1999 pci_disable_msi(iommu->dev); in iommu_setup_msi()
2003 iommu->int_enabled = true; in iommu_setup_msi()
2018 static void iommu_update_intcapxt(struct amd_iommu *iommu) in iommu_update_intcapxt() argument
2021 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET); in iommu_update_intcapxt()
2022 u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET); in iommu_update_intcapxt()
2023 u32 data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET); in iommu_update_intcapxt()
2036 * Current IOMMU implemtation uses the same IRQ for all in iommu_update_intcapxt()
2037 * 3 IOMMU interrupts. in iommu_update_intcapxt()
2039 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); in iommu_update_intcapxt()
2040 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); in iommu_update_intcapxt()
2041 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); in iommu_update_intcapxt()
2047 struct amd_iommu *iommu; in _irq_notifier_notify() local
2049 for_each_iommu(iommu) { in _irq_notifier_notify()
2050 if (iommu->dev->irq == notify->irq) { in _irq_notifier_notify()
2051 iommu_update_intcapxt(iommu); in _irq_notifier_notify()
2061 static int iommu_init_intcapxt(struct amd_iommu *iommu) in iommu_init_intcapxt() argument
2064 struct irq_affinity_notify *notify = &iommu->intcapxt_notify; in iommu_init_intcapxt()
2077 notify->irq = iommu->dev->irq; in iommu_init_intcapxt()
2080 ret = irq_set_affinity_notifier(iommu->dev->irq, notify); in iommu_init_intcapxt()
2083 iommu->devid, iommu->dev->irq); in iommu_init_intcapxt()
2087 iommu_update_intcapxt(iommu); in iommu_init_intcapxt()
2088 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); in iommu_init_intcapxt()
2092 static int iommu_init_msi(struct amd_iommu *iommu) in iommu_init_msi() argument
2096 if (iommu->int_enabled) in iommu_init_msi()
2099 if (iommu->dev->msi_cap) in iommu_init_msi()
2100 ret = iommu_setup_msi(iommu); in iommu_init_msi()
2108 ret = iommu_init_intcapxt(iommu); in iommu_init_msi()
2112 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_msi()
2114 if (iommu->ppr_log != NULL) in iommu_init_msi()
2115 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); in iommu_init_msi()
2117 iommu_ga_log_enable(iommu); in iommu_init_msi()
2249 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
2251 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2252 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
2253 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
2255 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2256 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
2257 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
2259 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2260 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
2261 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
2263 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2264 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
2265 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
2268 * make IOMMU memory accesses cache coherent in iommu_init_flags()
2270 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
2273 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
2276 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
2280 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2282 /* RD890 BIOSes may not have completely reconfigured the iommu */ in iommu_apply_resume_quirks()
2283 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2287 * First, we need to ensure that the iommu is enabled. This is in iommu_apply_resume_quirks()
2295 /* Enable the iommu */ in iommu_apply_resume_quirks()
2299 /* Restore the iommu BAR */ in iommu_apply_resume_quirks()
2300 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2301 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2302 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2303 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2308 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2312 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2315 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2316 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2319 static void iommu_enable_ga(struct amd_iommu *iommu) in iommu_enable_ga() argument
2324 iommu_feature_enable(iommu, CONTROL_GAM_EN); in iommu_enable_ga()
2327 iommu_feature_enable(iommu, CONTROL_GA_EN); in iommu_enable_ga()
2328 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2331 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2337 static void early_enable_iommu(struct amd_iommu *iommu) in early_enable_iommu() argument
2339 iommu_disable(iommu); in early_enable_iommu()
2340 iommu_init_flags(iommu); in early_enable_iommu()
2341 iommu_set_device_table(iommu); in early_enable_iommu()
2342 iommu_enable_command_buffer(iommu); in early_enable_iommu()
2343 iommu_enable_event_buffer(iommu); in early_enable_iommu()
2344 iommu_set_exclusion_range(iommu); in early_enable_iommu()
2345 iommu_enable_ga(iommu); in early_enable_iommu()
2346 iommu_enable_xt(iommu); in early_enable_iommu()
2347 iommu_enable(iommu); in early_enable_iommu()
2348 iommu_flush_all_caches(iommu); in early_enable_iommu()
2361 struct amd_iommu *iommu; in early_enable_iommus() local
2376 for_each_iommu(iommu) { in early_enable_iommus()
2377 clear_translation_pre_enabled(iommu); in early_enable_iommus()
2378 early_enable_iommu(iommu); in early_enable_iommus()
2385 for_each_iommu(iommu) { in early_enable_iommus()
2386 iommu_disable_command_buffer(iommu); in early_enable_iommus()
2387 iommu_disable_event_buffer(iommu); in early_enable_iommus()
2388 iommu_enable_command_buffer(iommu); in early_enable_iommus()
2389 iommu_enable_event_buffer(iommu); in early_enable_iommus()
2390 iommu_enable_ga(iommu); in early_enable_iommus()
2391 iommu_enable_xt(iommu); in early_enable_iommus()
2392 iommu_set_device_table(iommu); in early_enable_iommus()
2393 iommu_flush_all_caches(iommu); in early_enable_iommus()
2413 struct amd_iommu *iommu; in enable_iommus_v2() local
2415 for_each_iommu(iommu) { in enable_iommus_v2()
2416 iommu_enable_ppr_log(iommu); in enable_iommus_v2()
2417 iommu_enable_gt(iommu); in enable_iommus_v2()
2430 struct amd_iommu *iommu; in disable_iommus() local
2432 for_each_iommu(iommu) in disable_iommus()
2433 iommu_disable(iommu); in disable_iommus()
2448 struct amd_iommu *iommu; in amd_iommu_resume() local
2450 for_each_iommu(iommu) in amd_iommu_resume()
2451 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
2564 * This is the hardware init function for AMD IOMMU in the system.
2568 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2645 * IOMMU see for that device in early_amd_iommu_init()
2652 /* IOMMU rlookup table - find the IOMMU for a specific device */ in early_amd_iommu_init()
2685 /* Disable IOMMU if there's Stoney Ridge graphics */ in early_amd_iommu_init()
2689 pr_info("Disable IOMMU on Stoney Ridge\n"); in early_amd_iommu_init()
2745 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
2748 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
2749 ret = iommu_init_msi(iommu); in amd_iommu_enable_interrupts()
2782 * AMD IOMMU Initialization State Machine
2803 pr_info("AMD IOMMU disabled\n"); in state_next()
2850 struct amd_iommu *iommu; in state_next() local
2853 for_each_iommu(iommu) in state_next()
2854 iommu_flush_all_caches(iommu); in state_next()
2920 * This is the core init function for AMD IOMMU hardware in the system.
2926 struct amd_iommu *iommu; in amd_iommu_init() local
2933 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
2940 for_each_iommu(iommu) in amd_iommu_init()
2941 amd_iommu_debugfs_setup(iommu); in amd_iommu_init()
2959 pr_notice("IOMMU not currently supported when SME is active\n"); in amd_iommu_sme_check()
2966 * Early detect code. This code runs at IOMMU detection time in the DMA
2987 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
2994 * Parsing functions for the AMD IOMMU specific kernel command line
3148 struct amd_iommu *iommu; in get_amd_iommu() local
3150 for_each_iommu(iommu) in get_amd_iommu()
3152 return iommu; in get_amd_iommu()
3159 * IOMMU EFR Performance Counter support functionality. This code allows
3160 * access to the IOMMU PC functionality.
3166 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_banks() local
3168 if (iommu) in amd_iommu_pc_get_max_banks()
3169 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3183 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_counters() local
3185 if (iommu) in amd_iommu_pc_get_max_counters()
3186 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3192 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, in iommu_pc_get_set_reg() argument
3198 /* Make sure the IOMMU PC resource is available */ in iommu_pc_get_set_reg()
3202 /* Check for valid iommu and pc register indexing */ in iommu_pc_get_set_reg()
3203 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) in iommu_pc_get_set_reg()
3209 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3210 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3218 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3219 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3221 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3223 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3230 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_get_reg() argument
3232 if (!iommu) in amd_iommu_pc_get_reg()
3235 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); in amd_iommu_pc_get_reg()
3239 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_set_reg() argument
3241 if (!iommu) in amd_iommu_pc_set_reg()
3244 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); in amd_iommu_pc_set_reg()