Lines Matching full:iommu
33 #include <linux/iommu.h>
34 #include <linux/intel-iommu.h>
47 #include <asm/iommu.h>
90 * to the IOMMU core, which will then use this information to split
94 * Traditionally the IOMMU core just handed us the mappings directly,
101 * If at some point we'd like to utilize the IOMMU core's new behavior,
171 /* global iommu list, set NULL for ignored DMAR units */
293 * 2. It maps to each iommu if successful.
294 * 3. Each iommu mapps to this domain if successful.
414 static bool translation_pre_enabled(struct intel_iommu *iommu) in translation_pre_enabled() argument
416 return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
419 static void clear_translation_pre_enabled(struct intel_iommu *iommu) in clear_translation_pre_enabled() argument
421 iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
424 static void init_translation_status(struct intel_iommu *iommu) in init_translation_status() argument
428 gsts = readl(iommu->reg + DMAR_GSTS_REG); in init_translation_status()
430 iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
440 pr_info("IOMMU enabled\n"); in intel_iommu_setup()
444 pr_info("IOMMU disabled\n"); in intel_iommu_setup()
458 pr_info("Intel-IOMMU: scalable mode supported\n"); in intel_iommu_setup()
461 pr_info("Intel-IOMMU: not forcing on after tboot. This could expose security risk for tboot\n"); in intel_iommu_setup()
464 pr_info("Intel-IOMMU: No bounce buffer. This could expose security risks of DMA attacks\n"); in intel_iommu_setup()
479 static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did) in get_iommu_domain() argument
484 domains = iommu->domains[idx]; in get_iommu_domain()
491 static void set_iommu_domain(struct intel_iommu *iommu, u16 did, in set_iommu_domain() argument
497 if (!iommu->domains[idx]) { in set_iommu_domain()
499 iommu->domains[idx] = kzalloc(size, GFP_ATOMIC); in set_iommu_domain()
502 domains = iommu->domains[idx]; in set_iommu_domain()
563 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) in __iommu_calculate_agaw() argument
568 sagaw = cap_sagaw(iommu->cap); in __iommu_calculate_agaw()
579 * Calculate max SAGAW for each iommu.
581 int iommu_calculate_max_sagaw(struct intel_iommu *iommu) in iommu_calculate_max_sagaw() argument
583 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); in iommu_calculate_max_sagaw()
587 * calculate agaw for each iommu.
591 int iommu_calculate_agaw(struct intel_iommu *iommu) in iommu_calculate_agaw() argument
593 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); in iommu_calculate_agaw()
596 /* This functionin only returns single iommu in a domain */
614 static inline bool iommu_paging_structure_coherency(struct intel_iommu *iommu) in iommu_paging_structure_coherency() argument
616 return sm_supported(iommu) ? in iommu_paging_structure_coherency()
617 ecap_smpwc(iommu->ecap) : ecap_coherent(iommu->ecap); in iommu_paging_structure_coherency()
623 struct intel_iommu *iommu; in domain_update_iommu_coherency() local
641 for_each_active_iommu(iommu, drhd) { in domain_update_iommu_coherency()
642 if (!iommu_paging_structure_coherency(iommu)) { in domain_update_iommu_coherency()
653 struct intel_iommu *iommu; in domain_update_iommu_snooping() local
657 for_each_active_iommu(iommu, drhd) { in domain_update_iommu_snooping()
658 if (iommu != skip) { in domain_update_iommu_snooping()
665 if (!sm_supported(iommu) && in domain_update_iommu_snooping()
666 !ecap_sc_support(iommu->ecap)) { in domain_update_iommu_snooping()
681 struct intel_iommu *iommu; in domain_update_iommu_superpage() local
690 for_each_active_iommu(iommu, drhd) { in domain_update_iommu_superpage()
691 if (iommu != skip) { in domain_update_iommu_superpage()
693 if (!cap_fl1gp_support(iommu->cap)) in domain_update_iommu_superpage()
696 mask &= cap_super_page_val(iommu->cap); in domain_update_iommu_superpage()
763 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, in iommu_context_addr() argument
766 struct root_entry *root = &iommu->root_entry[bus]; in iommu_context_addr()
771 if (sm_supported(iommu)) { in iommu_context_addr()
785 context = alloc_pgtable_page(iommu->node); in iommu_context_addr()
789 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); in iommu_context_addr()
792 __iommu_flush_cache(iommu, entry, sizeof(*entry)); in iommu_context_addr()
835 /* We know that this device on this chipset has its own IOMMU. in quirk_ioat_snb_local_iommu()
836 * If we find it under a different IOMMU, then the BIOS is lying in quirk_ioat_snb_local_iommu()
837 * to us. Hope that the IOMMU for this device is actually in quirk_ioat_snb_local_iommu()
848 /* we know that the this iommu should be at offset 0xa000 from vtbar */ in quirk_ioat_snb_local_iommu()
859 static bool iommu_is_dummy(struct intel_iommu *iommu, struct device *dev) in iommu_is_dummy() argument
861 if (!iommu || iommu->drhd->ignored) in iommu_is_dummy()
880 struct intel_iommu *iommu; in device_to_iommu() local
894 * the PF instead to find the IOMMU. */ in device_to_iommu()
902 for_each_iommu(iommu, drhd) { in device_to_iommu()
910 * which we used for the IOMMU lookup. Strictly speaking in device_to_iommu()
936 iommu = NULL; in device_to_iommu()
938 if (iommu_is_dummy(iommu, dev)) in device_to_iommu()
939 iommu = NULL; in device_to_iommu()
943 return iommu; in device_to_iommu()
953 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) in device_context_mapped() argument
959 spin_lock_irqsave(&iommu->lock, flags); in device_context_mapped()
960 context = iommu_context_addr(iommu, bus, devfn, 0); in device_context_mapped()
963 spin_unlock_irqrestore(&iommu->lock, flags); in device_context_mapped()
967 static void free_context_table(struct intel_iommu *iommu) in free_context_table() argument
973 spin_lock_irqsave(&iommu->lock, flags); in free_context_table()
974 if (!iommu->root_entry) { in free_context_table()
978 context = iommu_context_addr(iommu, i, 0, 0); in free_context_table()
982 if (!sm_supported(iommu)) in free_context_table()
985 context = iommu_context_addr(iommu, i, 0x80, 0); in free_context_table()
990 free_pgtable_page(iommu->root_entry); in free_context_table()
991 iommu->root_entry = NULL; in free_context_table()
993 spin_unlock_irqrestore(&iommu->lock, flags); in free_context_table()
1006 /* Address beyond IOMMU's addressing capabilities. */ in pfn_to_dma_pte()
1263 /* We can't just free the pages because the IOMMU may still be walking
1309 /* iommu handling */
1310 static int iommu_alloc_root_entry(struct intel_iommu *iommu) in iommu_alloc_root_entry() argument
1315 root = (struct root_entry *)alloc_pgtable_page(iommu->node); in iommu_alloc_root_entry()
1318 iommu->name); in iommu_alloc_root_entry()
1322 __iommu_flush_cache(iommu, root, ROOT_SIZE); in iommu_alloc_root_entry()
1324 spin_lock_irqsave(&iommu->lock, flags); in iommu_alloc_root_entry()
1325 iommu->root_entry = root; in iommu_alloc_root_entry()
1326 spin_unlock_irqrestore(&iommu->lock, flags); in iommu_alloc_root_entry()
1331 static void iommu_set_root_entry(struct intel_iommu *iommu) in iommu_set_root_entry() argument
1337 addr = virt_to_phys(iommu->root_entry); in iommu_set_root_entry()
1338 if (sm_supported(iommu)) in iommu_set_root_entry()
1341 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_set_root_entry()
1342 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); in iommu_set_root_entry()
1344 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); in iommu_set_root_entry()
1347 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_set_root_entry()
1350 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_set_root_entry()
1352 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); in iommu_set_root_entry()
1353 if (sm_supported(iommu)) in iommu_set_root_entry()
1354 qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0); in iommu_set_root_entry()
1355 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); in iommu_set_root_entry()
1358 void iommu_flush_write_buffer(struct intel_iommu *iommu) in iommu_flush_write_buffer() argument
1363 if (!rwbf_quirk && !cap_rwbf(iommu->cap)) in iommu_flush_write_buffer()
1366 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_flush_write_buffer()
1367 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); in iommu_flush_write_buffer()
1370 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_flush_write_buffer()
1373 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_flush_write_buffer()
1377 static void __iommu_flush_context(struct intel_iommu *iommu, in __iommu_flush_context() argument
1400 raw_spin_lock_irqsave(&iommu->register_lock, flag); in __iommu_flush_context()
1401 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); in __iommu_flush_context()
1404 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, in __iommu_flush_context()
1407 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in __iommu_flush_context()
1411 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, in __iommu_flush_iotlb() argument
1414 int tlb_offset = ecap_iotlb_offset(iommu->ecap); in __iommu_flush_iotlb()
1440 if (cap_read_drain(iommu->cap)) in __iommu_flush_iotlb()
1443 if (cap_write_drain(iommu->cap)) in __iommu_flush_iotlb()
1446 raw_spin_lock_irqsave(&iommu->register_lock, flag); in __iommu_flush_iotlb()
1449 dmar_writeq(iommu->reg + tlb_offset, val_iva); in __iommu_flush_iotlb()
1450 dmar_writeq(iommu->reg + tlb_offset + 8, val); in __iommu_flush_iotlb()
1453 IOMMU_WAIT_OP(iommu, tlb_offset + 8, in __iommu_flush_iotlb()
1456 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in __iommu_flush_iotlb()
1468 iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu, in iommu_support_dev_iotlb() argument
1475 if (!iommu->qi) in iommu_support_dev_iotlb()
1479 if (info->iommu == iommu && info->bus == bus && in iommu_support_dev_iotlb()
1522 /* For IOMMU that supports device IOTLB throttling (DIT), we assign in iommu_enable_dev_iotlb()
1523 * PFSID to the invalidation desc of a VF such that IOMMU HW can gauge in iommu_enable_dev_iotlb()
1527 if (!ecap_dit(info->iommu->ecap)) in iommu_enable_dev_iotlb()
1604 qi_flush_dev_iotlb(info->iommu, sid, info->pfsid, in iommu_flush_dev_iotlb()
1610 static void domain_flush_piotlb(struct intel_iommu *iommu, in domain_flush_piotlb() argument
1614 u16 did = domain->iommu_did[iommu->seq_id]; in domain_flush_piotlb()
1617 qi_flush_piotlb(iommu, did, domain->default_pasid, in domain_flush_piotlb()
1621 qi_flush_piotlb(iommu, did, PASID_RID2PASID, addr, npages, ih); in domain_flush_piotlb()
1624 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, in iommu_flush_iotlb_psi() argument
1631 u16 did = domain->iommu_did[iommu->seq_id]; in iommu_flush_iotlb_psi()
1639 domain_flush_piotlb(iommu, domain, addr, pages, ih); in iommu_flush_iotlb_psi()
1646 if (!cap_pgsel_inv(iommu->cap) || in iommu_flush_iotlb_psi()
1647 mask > cap_max_amask_val(iommu->cap)) in iommu_flush_iotlb_psi()
1648 iommu->flush.flush_iotlb(iommu, did, 0, 0, in iommu_flush_iotlb_psi()
1651 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, in iommu_flush_iotlb_psi()
1659 if (!cap_caching_mode(iommu->cap) || !map) in iommu_flush_iotlb_psi()
1664 static inline void __mapping_notify_one(struct intel_iommu *iommu, in __mapping_notify_one() argument
1672 if (cap_caching_mode(iommu->cap) && !domain_use_first_level(domain)) in __mapping_notify_one()
1673 iommu_flush_iotlb_psi(iommu, domain, pfn, pages, 0, 1); in __mapping_notify_one()
1675 iommu_flush_write_buffer(iommu); in __mapping_notify_one()
1686 struct intel_iommu *iommu = g_iommus[idx]; in iommu_flush_iova() local
1687 u16 did = domain->iommu_did[iommu->seq_id]; in iommu_flush_iova()
1690 domain_flush_piotlb(iommu, domain, 0, -1, 0); in iommu_flush_iova()
1692 iommu->flush.flush_iotlb(iommu, did, 0, 0, in iommu_flush_iova()
1695 if (!cap_caching_mode(iommu->cap)) in iommu_flush_iova()
1696 iommu_flush_dev_iotlb(get_iommu_domain(iommu, did), in iommu_flush_iova()
1701 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) in iommu_disable_protect_mem_regions() argument
1706 if (!cap_plmr(iommu->cap) && !cap_phmr(iommu->cap)) in iommu_disable_protect_mem_regions()
1709 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_disable_protect_mem_regions()
1710 pmen = readl(iommu->reg + DMAR_PMEN_REG); in iommu_disable_protect_mem_regions()
1712 writel(pmen, iommu->reg + DMAR_PMEN_REG); in iommu_disable_protect_mem_regions()
1715 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, in iommu_disable_protect_mem_regions()
1718 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_disable_protect_mem_regions()
1721 static void iommu_enable_translation(struct intel_iommu *iommu) in iommu_enable_translation() argument
1726 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_enable_translation()
1727 iommu->gcmd |= DMA_GCMD_TE; in iommu_enable_translation()
1728 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_enable_translation()
1731 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_enable_translation()
1734 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_enable_translation()
1737 static void iommu_disable_translation(struct intel_iommu *iommu) in iommu_disable_translation() argument
1742 if (iommu_skip_te_disable && iommu->drhd->gfx_dedicated && in iommu_disable_translation()
1743 (cap_read_drain(iommu->cap) || cap_write_drain(iommu->cap))) in iommu_disable_translation()
1746 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_disable_translation()
1747 iommu->gcmd &= ~DMA_GCMD_TE; in iommu_disable_translation()
1748 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_disable_translation()
1751 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_disable_translation()
1754 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_disable_translation()
1757 static int iommu_init_domains(struct intel_iommu *iommu) in iommu_init_domains() argument
1762 ndomains = cap_ndoms(iommu->cap); in iommu_init_domains()
1764 iommu->name, ndomains); in iommu_init_domains()
1767 spin_lock_init(&iommu->lock); in iommu_init_domains()
1769 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); in iommu_init_domains()
1770 if (!iommu->domain_ids) { in iommu_init_domains()
1772 iommu->name); in iommu_init_domains()
1777 iommu->domains = kzalloc(size, GFP_KERNEL); in iommu_init_domains()
1779 if (iommu->domains) { in iommu_init_domains()
1781 iommu->domains[0] = kzalloc(size, GFP_KERNEL); in iommu_init_domains()
1784 if (!iommu->domains || !iommu->domains[0]) { in iommu_init_domains()
1786 iommu->name); in iommu_init_domains()
1787 kfree(iommu->domain_ids); in iommu_init_domains()
1788 kfree(iommu->domains); in iommu_init_domains()
1789 iommu->domain_ids = NULL; in iommu_init_domains()
1790 iommu->domains = NULL; in iommu_init_domains()
1800 set_bit(0, iommu->domain_ids); in iommu_init_domains()
1809 if (sm_supported(iommu)) in iommu_init_domains()
1810 set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); in iommu_init_domains()
1815 static void disable_dmar_iommu(struct intel_iommu *iommu) in disable_dmar_iommu() argument
1820 if (!iommu->domains || !iommu->domain_ids) in disable_dmar_iommu()
1825 if (info->iommu != iommu) in disable_dmar_iommu()
1835 if (iommu->gcmd & DMA_GCMD_TE) in disable_dmar_iommu()
1836 iommu_disable_translation(iommu); in disable_dmar_iommu()
1839 static void free_dmar_iommu(struct intel_iommu *iommu) in free_dmar_iommu() argument
1841 if ((iommu->domains) && (iommu->domain_ids)) { in free_dmar_iommu()
1842 int elems = ALIGN(cap_ndoms(iommu->cap), 256) >> 8; in free_dmar_iommu()
1846 kfree(iommu->domains[i]); in free_dmar_iommu()
1847 kfree(iommu->domains); in free_dmar_iommu()
1848 kfree(iommu->domain_ids); in free_dmar_iommu()
1849 iommu->domains = NULL; in free_dmar_iommu()
1850 iommu->domain_ids = NULL; in free_dmar_iommu()
1853 g_iommus[iommu->seq_id] = NULL; in free_dmar_iommu()
1856 free_context_table(iommu); in free_dmar_iommu()
1859 if (pasid_supported(iommu)) { in free_dmar_iommu()
1860 if (ecap_prs(iommu->ecap)) in free_dmar_iommu()
1861 intel_svm_finish_prq(iommu); in free_dmar_iommu()
1863 if (vccap_pasid(iommu->vccap)) in free_dmar_iommu()
1864 ioasid_unregister_allocator(&iommu->pasid_allocator); in free_dmar_iommu()
1876 struct intel_iommu *iommu; in first_level_by_default() local
1885 for_each_active_iommu(iommu, drhd) { in first_level_by_default()
1886 if (!sm_supported(iommu) || !ecap_flts(iommu->ecap)) { in first_level_by_default()
1915 /* Must be called with iommu->lock */
1917 struct intel_iommu *iommu) in domain_attach_iommu() argument
1923 assert_spin_locked(&iommu->lock); in domain_attach_iommu()
1925 domain->iommu_refcnt[iommu->seq_id] += 1; in domain_attach_iommu()
1927 if (domain->iommu_refcnt[iommu->seq_id] == 1) { in domain_attach_iommu()
1928 ndomains = cap_ndoms(iommu->cap); in domain_attach_iommu()
1929 num = find_first_zero_bit(iommu->domain_ids, ndomains); in domain_attach_iommu()
1932 pr_err("%s: No free domain ids\n", iommu->name); in domain_attach_iommu()
1933 domain->iommu_refcnt[iommu->seq_id] -= 1; in domain_attach_iommu()
1938 set_bit(num, iommu->domain_ids); in domain_attach_iommu()
1939 set_iommu_domain(iommu, num, domain); in domain_attach_iommu()
1941 domain->iommu_did[iommu->seq_id] = num; in domain_attach_iommu()
1942 domain->nid = iommu->node; in domain_attach_iommu()
1951 struct intel_iommu *iommu) in domain_detach_iommu() argument
1956 assert_spin_locked(&iommu->lock); in domain_detach_iommu()
1958 domain->iommu_refcnt[iommu->seq_id] -= 1; in domain_detach_iommu()
1960 if (domain->iommu_refcnt[iommu->seq_id] == 0) { in domain_detach_iommu()
1961 num = domain->iommu_did[iommu->seq_id]; in domain_detach_iommu()
1962 clear_bit(num, iommu->domain_ids); in domain_detach_iommu()
1963 set_iommu_domain(iommu, num, NULL); in domain_detach_iommu()
1966 domain->iommu_did[iommu->seq_id] = 0; in domain_detach_iommu()
2067 * IOMMU hardware will use the PASID value set in this field for
2098 struct intel_iommu *iommu, in domain_context_mapping_one() argument
2102 u16 did = domain->iommu_did[iommu->seq_id]; in domain_context_mapping_one()
2120 spin_lock(&iommu->lock); in domain_context_mapping_one()
2123 context = iommu_context_addr(iommu, bus, devfn, 1); in domain_context_mapping_one()
2143 if (did_old < cap_ndoms(iommu->cap)) { in domain_context_mapping_one()
2144 iommu->flush.flush_context(iommu, did_old, in domain_context_mapping_one()
2148 iommu->flush.flush_iotlb(iommu, did_old, 0, 0, in domain_context_mapping_one()
2155 if (sm_supported(iommu)) { in domain_context_mapping_one()
2172 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); in domain_context_mapping_one()
2185 * Skip top levels of page tables for iommu which has in domain_context_mapping_one()
2188 for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { in domain_context_mapping_one()
2195 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); in domain_context_mapping_one()
2209 context_set_address_width(context, iommu->msagaw); in domain_context_mapping_one()
2217 if (!ecap_coherent(iommu->ecap)) in domain_context_mapping_one()
2226 if (cap_caching_mode(iommu->cap)) { in domain_context_mapping_one()
2227 iommu->flush.flush_context(iommu, 0, in domain_context_mapping_one()
2231 iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); in domain_context_mapping_one()
2233 iommu_flush_write_buffer(iommu); in domain_context_mapping_one()
2240 spin_unlock(&iommu->lock); in domain_context_mapping_one()
2248 struct intel_iommu *iommu; member
2257 return domain_context_mapping_one(data->domain, data->iommu, in domain_context_mapping_cb()
2267 struct intel_iommu *iommu; in domain_context_mapping() local
2270 iommu = device_to_iommu(dev, &bus, &devfn); in domain_context_mapping()
2271 if (!iommu) in domain_context_mapping()
2277 return domain_context_mapping_one(domain, iommu, table, in domain_context_mapping()
2281 data.iommu = iommu; in domain_context_mapping()
2291 struct intel_iommu *iommu = opaque; in domain_context_mapped_cb() local
2293 return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff); in domain_context_mapped_cb()
2298 struct intel_iommu *iommu; in domain_context_mapped() local
2301 iommu = device_to_iommu(dev, &bus, &devfn); in domain_context_mapped()
2302 if (!iommu) in domain_context_mapped()
2306 return device_context_mapped(iommu, bus, devfn); in domain_context_mapped()
2309 domain_context_mapped_cb, iommu); in domain_context_mapped()
2479 struct intel_iommu *iommu; in domain_mapping() local
2487 iommu = g_iommus[iommu_id]; in domain_mapping()
2488 __mapping_notify_one(iommu, domain, iov_pfn, nr_pages); in domain_mapping()
2508 static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn) in domain_context_clear_one() argument
2514 if (!iommu) in domain_context_clear_one()
2517 spin_lock_irqsave(&iommu->lock, flags); in domain_context_clear_one()
2518 context = iommu_context_addr(iommu, bus, devfn, 0); in domain_context_clear_one()
2520 spin_unlock_irqrestore(&iommu->lock, flags); in domain_context_clear_one()
2525 __iommu_flush_cache(iommu, context, sizeof(*context)); in domain_context_clear_one()
2526 spin_unlock_irqrestore(&iommu->lock, flags); in domain_context_clear_one()
2527 iommu->flush.flush_context(iommu, in domain_context_clear_one()
2533 if (sm_supported(iommu)) in domain_context_clear_one()
2534 qi_flush_pasid_cache(iommu, did_old, QI_PC_ALL_PASIDS, 0); in domain_context_clear_one()
2536 iommu->flush.flush_iotlb(iommu, in domain_context_clear_one()
2567 if (unlikely(!dev || !dev->iommu)) in find_domain()
2604 static int domain_setup_first_level(struct intel_iommu *iommu, in domain_setup_first_level() argument
2614 * Skip top levels of page tables for iommu which has in domain_setup_first_level()
2617 for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { in domain_setup_first_level()
2635 return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid, in domain_setup_first_level()
2636 domain->iommu_did[iommu->seq_id], in domain_setup_first_level()
2646 static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, in dmar_insert_one_dev_info() argument
2663 info->segment = iommu->segment; in dmar_insert_one_dev_info()
2677 info->iommu = iommu; in dmar_insert_one_dev_info()
2685 if (ecap_dev_iotlb_support(iommu->ecap) && in dmar_insert_one_dev_info()
2690 if (sm_supported(iommu)) { in dmar_insert_one_dev_info()
2691 if (pasid_supported(iommu)) { in dmar_insert_one_dev_info()
2697 if (info->ats_supported && ecap_prs(iommu->ecap) && in dmar_insert_one_dev_info()
2724 spin_lock(&iommu->lock); in dmar_insert_one_dev_info()
2725 ret = domain_attach_iommu(domain, iommu); in dmar_insert_one_dev_info()
2726 spin_unlock(&iommu->lock); in dmar_insert_one_dev_info()
2741 if (dev && dev_is_pci(dev) && sm_supported(iommu)) { in dmar_insert_one_dev_info()
2750 spin_lock_irqsave(&iommu->lock, flags); in dmar_insert_one_dev_info()
2752 ret = intel_pasid_setup_pass_through(iommu, domain, in dmar_insert_one_dev_info()
2755 ret = domain_setup_first_level(iommu, domain, dev, in dmar_insert_one_dev_info()
2758 ret = intel_pasid_setup_second_level(iommu, domain, in dmar_insert_one_dev_info()
2760 spin_unlock_irqrestore(&iommu->lock, flags); in dmar_insert_one_dev_info()
2853 struct intel_iommu *iommu; in domain_add_dev_info() local
2856 iommu = device_to_iommu(dev, &bus, &devfn); in domain_add_dev_info()
2857 if (!iommu) in domain_add_dev_info()
2860 ndomain = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain); in domain_add_dev_info()
2926 * The second is use of the device through the IOMMU API. This interface
2930 * use of the RMRR space or even inform the IOMMU API user of the restriction.
2932 * the IOMMU API, which eliminates them from device assignment.
2981 static void intel_iommu_init_qi(struct intel_iommu *iommu) in intel_iommu_init_qi() argument
2984 * Start from the sane iommu hardware state. in intel_iommu_init_qi()
2989 if (!iommu->qi) { in intel_iommu_init_qi()
2993 dmar_fault(-1, iommu); in intel_iommu_init_qi()
2998 dmar_disable_qi(iommu); in intel_iommu_init_qi()
3001 if (dmar_enable_qi(iommu)) { in intel_iommu_init_qi()
3005 iommu->flush.flush_context = __iommu_flush_context; in intel_iommu_init_qi()
3006 iommu->flush.flush_iotlb = __iommu_flush_iotlb; in intel_iommu_init_qi()
3008 iommu->name); in intel_iommu_init_qi()
3010 iommu->flush.flush_context = qi_flush_context; in intel_iommu_init_qi()
3011 iommu->flush.flush_iotlb = qi_flush_iotlb; in intel_iommu_init_qi()
3012 pr_info("%s: Using Queued invalidation\n", iommu->name); in intel_iommu_init_qi()
3016 static int copy_context_table(struct intel_iommu *iommu, in copy_context_table() argument
3038 __iommu_flush_cache(iommu, new_ce, in copy_context_table()
3068 new_ce = alloc_pgtable_page(iommu->node); in copy_context_table()
3082 if (did >= 0 && did < cap_ndoms(iommu->cap)) in copy_context_table()
3083 set_bit(did, iommu->domain_ids); in copy_context_table()
3109 __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE); in copy_context_table()
3118 static int copy_translation_tables(struct intel_iommu *iommu) in copy_translation_tables() argument
3129 rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG); in copy_translation_tables()
3131 new_ext = !!ecap_ecs(iommu->ecap); in copy_translation_tables()
3158 ret = copy_context_table(iommu, &old_rt[bus], in copy_translation_tables()
3162 iommu->name, bus); in copy_translation_tables()
3167 spin_lock_irqsave(&iommu->lock, flags); in copy_translation_tables()
3176 iommu->root_entry[bus].lo = val; in copy_translation_tables()
3183 iommu->root_entry[bus].hi = val; in copy_translation_tables()
3186 spin_unlock_irqrestore(&iommu->lock, flags); in copy_translation_tables()
3190 __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE); in copy_translation_tables()
3203 struct intel_iommu *iommu = data; in intel_vcmd_ioasid_alloc() local
3206 if (!iommu) in intel_vcmd_ioasid_alloc()
3216 if (vcmd_alloc_pasid(iommu, &ioasid)) in intel_vcmd_ioasid_alloc()
3224 struct intel_iommu *iommu = data; in intel_vcmd_ioasid_free() local
3226 if (!iommu) in intel_vcmd_ioasid_free()
3236 vcmd_free_pasid(iommu, ioasid); in intel_vcmd_ioasid_free()
3239 static void register_pasid_allocator(struct intel_iommu *iommu) in register_pasid_allocator() argument
3245 if (!cap_caching_mode(iommu->cap)) in register_pasid_allocator()
3248 if (!sm_supported(iommu)) { in register_pasid_allocator()
3260 if (!vccap_pasid(iommu->vccap)) in register_pasid_allocator()
3264 iommu->pasid_allocator.alloc = intel_vcmd_ioasid_alloc; in register_pasid_allocator()
3265 iommu->pasid_allocator.free = intel_vcmd_ioasid_free; in register_pasid_allocator()
3266 iommu->pasid_allocator.pdata = (void *)iommu; in register_pasid_allocator()
3267 if (ioasid_register_allocator(&iommu->pasid_allocator)) { in register_pasid_allocator()
3270 * Disable scalable mode on this IOMMU if there in register_pasid_allocator()
3282 struct intel_iommu *iommu; in init_dmars() local
3304 /* Preallocate enough resources for IOMMU hot-addition */ in init_dmars()
3311 pr_err("Allocating global iommu array failed\n"); in init_dmars()
3316 for_each_iommu(iommu, drhd) { in init_dmars()
3318 iommu_disable_translation(iommu); in init_dmars()
3323 * Find the max pasid size of all IOMMU's in the system. in init_dmars()
3327 if (pasid_supported(iommu)) { in init_dmars()
3328 u32 temp = 2 << ecap_pss(iommu->ecap); in init_dmars()
3334 g_iommus[iommu->seq_id] = iommu; in init_dmars()
3336 intel_iommu_init_qi(iommu); in init_dmars()
3338 ret = iommu_init_domains(iommu); in init_dmars()
3342 init_translation_status(iommu); in init_dmars()
3344 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_dmars()
3345 iommu_disable_translation(iommu); in init_dmars()
3346 clear_translation_pre_enabled(iommu); in init_dmars()
3348 iommu->name); in init_dmars()
3354 * among all IOMMU's. Need to Split it later. in init_dmars()
3356 ret = iommu_alloc_root_entry(iommu); in init_dmars()
3360 if (translation_pre_enabled(iommu)) { in init_dmars()
3363 ret = copy_translation_tables(iommu); in init_dmars()
3366 * We found the IOMMU with translation in init_dmars()
3375 iommu->name); in init_dmars()
3376 iommu_disable_translation(iommu); in init_dmars()
3377 clear_translation_pre_enabled(iommu); in init_dmars()
3380 iommu->name); in init_dmars()
3384 if (!ecap_pass_through(iommu->ecap)) in init_dmars()
3387 if (!intel_iommu_strict && cap_caching_mode(iommu->cap)) { in init_dmars()
3391 intel_svm_check(iommu); in init_dmars()
3399 for_each_active_iommu(iommu, drhd) { in init_dmars()
3400 iommu_flush_write_buffer(iommu); in init_dmars()
3402 register_pasid_allocator(iommu); in init_dmars()
3404 iommu_set_root_entry(iommu); in init_dmars()
3427 for_each_iommu(iommu, drhd) { in init_dmars()
3434 iommu_disable_protect_mem_regions(iommu); in init_dmars()
3438 iommu_flush_write_buffer(iommu); in init_dmars()
3441 if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { in init_dmars()
3447 ret = intel_svm_enable_prq(iommu); in init_dmars()
3453 ret = dmar_set_interrupt(iommu); in init_dmars()
3461 for_each_active_iommu(iommu, drhd) { in init_dmars()
3462 disable_dmar_iommu(iommu); in init_dmars()
3463 free_dmar_iommu(iommu); in init_dmars()
3480 * Restrict dma_mask to the width that the iommu can handle. in intel_alloc_iova()
3527 struct intel_iommu *iommu; in __intel_map_single() local
3539 iommu = domain_get_iommu(domain); in __intel_map_single()
3551 !cap_zlr(iommu->cap)) in __intel_map_single()
3603 struct intel_iommu *iommu; in intel_unmap() local
3610 iommu = domain_get_iommu(domain); in intel_unmap()
3624 iommu_flush_iotlb_psi(iommu, domain, start_pfn, in intel_unmap()
3734 struct intel_iommu *iommu; in intel_map_sg() local
3745 iommu = domain_get_iommu(domain); in intel_map_sg()
3762 !cap_zlr(iommu->cap)) in intel_map_sg()
3829 struct intel_iommu *iommu; in bounce_map_single() local
3844 iommu = domain_get_iommu(domain); in bounce_map_single()
3845 if (WARN_ON(!iommu)) in bounce_map_single()
3859 !cap_zlr(iommu->cap)) in bounce_map_single()
4152 /* This IOMMU has *only* gfx devices. Either bypass it or in init_no_remapping_devices()
4164 struct intel_iommu *iommu = NULL; in init_iommu_hw() local
4166 for_each_active_iommu(iommu, drhd) in init_iommu_hw()
4167 if (iommu->qi) in init_iommu_hw()
4168 dmar_reenable_qi(iommu); in init_iommu_hw()
4170 for_each_iommu(iommu, drhd) { in init_iommu_hw()
4177 iommu_disable_protect_mem_regions(iommu); in init_iommu_hw()
4181 iommu_flush_write_buffer(iommu); in init_iommu_hw()
4182 iommu_set_root_entry(iommu); in init_iommu_hw()
4183 iommu_enable_translation(iommu); in init_iommu_hw()
4184 iommu_disable_protect_mem_regions(iommu); in init_iommu_hw()
4193 struct intel_iommu *iommu; in iommu_flush_all() local
4195 for_each_active_iommu(iommu, drhd) { in iommu_flush_all()
4196 iommu->flush.flush_context(iommu, 0, 0, 0, in iommu_flush_all()
4198 iommu->flush.flush_iotlb(iommu, 0, 0, 0, in iommu_flush_all()
4206 struct intel_iommu *iommu = NULL; in iommu_suspend() local
4209 for_each_active_iommu(iommu, drhd) { in iommu_suspend()
4210 iommu->iommu_state = kcalloc(MAX_SR_DMAR_REGS, sizeof(u32), in iommu_suspend()
4212 if (!iommu->iommu_state) in iommu_suspend()
4218 for_each_active_iommu(iommu, drhd) { in iommu_suspend()
4219 iommu_disable_translation(iommu); in iommu_suspend()
4221 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_suspend()
4223 iommu->iommu_state[SR_DMAR_FECTL_REG] = in iommu_suspend()
4224 readl(iommu->reg + DMAR_FECTL_REG); in iommu_suspend()
4225 iommu->iommu_state[SR_DMAR_FEDATA_REG] = in iommu_suspend()
4226 readl(iommu->reg + DMAR_FEDATA_REG); in iommu_suspend()
4227 iommu->iommu_state[SR_DMAR_FEADDR_REG] = in iommu_suspend()
4228 readl(iommu->reg + DMAR_FEADDR_REG); in iommu_suspend()
4229 iommu->iommu_state[SR_DMAR_FEUADDR_REG] = in iommu_suspend()
4230 readl(iommu->reg + DMAR_FEUADDR_REG); in iommu_suspend()
4232 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_suspend()
4237 for_each_active_iommu(iommu, drhd) in iommu_suspend()
4238 kfree(iommu->iommu_state); in iommu_suspend()
4246 struct intel_iommu *iommu = NULL; in iommu_resume() local
4251 panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); in iommu_resume()
4253 WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); in iommu_resume()
4257 for_each_active_iommu(iommu, drhd) { in iommu_resume()
4259 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_resume()
4261 writel(iommu->iommu_state[SR_DMAR_FECTL_REG], in iommu_resume()
4262 iommu->reg + DMAR_FECTL_REG); in iommu_resume()
4263 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], in iommu_resume()
4264 iommu->reg + DMAR_FEDATA_REG); in iommu_resume()
4265 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], in iommu_resume()
4266 iommu->reg + DMAR_FEADDR_REG); in iommu_resume()
4267 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], in iommu_resume()
4268 iommu->reg + DMAR_FEUADDR_REG); in iommu_resume()
4270 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_resume()
4273 for_each_active_iommu(iommu, drhd) in iommu_resume()
4274 kfree(iommu->iommu_state); in iommu_resume()
4448 struct intel_iommu *iommu = dmaru->iommu; in intel_iommu_add() local
4450 if (g_iommus[iommu->seq_id]) in intel_iommu_add()
4453 if (hw_pass_through && !ecap_pass_through(iommu->ecap)) { in intel_iommu_add()
4455 iommu->name); in intel_iommu_add()
4458 if (!ecap_sc_support(iommu->ecap) && in intel_iommu_add()
4459 domain_update_iommu_snooping(iommu)) { in intel_iommu_add()
4461 iommu->name); in intel_iommu_add()
4464 sp = domain_update_iommu_superpage(NULL, iommu) - 1; in intel_iommu_add()
4465 if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) { in intel_iommu_add()
4467 iommu->name); in intel_iommu_add()
4474 if (iommu->gcmd & DMA_GCMD_TE) in intel_iommu_add()
4475 iommu_disable_translation(iommu); in intel_iommu_add()
4477 g_iommus[iommu->seq_id] = iommu; in intel_iommu_add()
4478 ret = iommu_init_domains(iommu); in intel_iommu_add()
4480 ret = iommu_alloc_root_entry(iommu); in intel_iommu_add()
4484 intel_svm_check(iommu); in intel_iommu_add()
4491 iommu_disable_protect_mem_regions(iommu); in intel_iommu_add()
4495 intel_iommu_init_qi(iommu); in intel_iommu_add()
4496 iommu_flush_write_buffer(iommu); in intel_iommu_add()
4499 if (pasid_supported(iommu) && ecap_prs(iommu->ecap)) { in intel_iommu_add()
4500 ret = intel_svm_enable_prq(iommu); in intel_iommu_add()
4505 ret = dmar_set_interrupt(iommu); in intel_iommu_add()
4509 iommu_set_root_entry(iommu); in intel_iommu_add()
4510 iommu_enable_translation(iommu); in intel_iommu_add()
4512 iommu_disable_protect_mem_regions(iommu); in intel_iommu_add()
4516 disable_dmar_iommu(iommu); in intel_iommu_add()
4518 free_dmar_iommu(iommu); in intel_iommu_add()
4525 struct intel_iommu *iommu = dmaru->iommu; in dmar_iommu_hotplug() local
4529 if (iommu == NULL) in dmar_iommu_hotplug()
4535 disable_dmar_iommu(iommu); in dmar_iommu_hotplug()
4536 free_dmar_iommu(iommu); in dmar_iommu_hotplug()
4676 struct intel_iommu *iommu; in intel_iommu_memory_notifier() local
4683 for_each_active_iommu(iommu, drhd) in intel_iommu_memory_notifier()
4684 iommu_flush_iotlb_psi(iommu, si_domain, in intel_iommu_memory_notifier()
4706 struct intel_iommu *iommu = g_iommus[i]; in free_all_cpu_cached_iovas() local
4710 if (!iommu) in free_all_cpu_cached_iovas()
4713 for (did = 0; did < cap_ndoms(iommu->cap); did++) { in free_all_cpu_cached_iovas()
4714 domain = get_iommu_domain(iommu, (u16)did); in free_all_cpu_cached_iovas()
4732 struct intel_iommu *iommu = NULL; in intel_disable_iommus() local
4735 for_each_iommu(iommu, drhd) in intel_disable_iommus()
4736 iommu_disable_translation(iommu); in intel_disable_iommus()
4742 struct intel_iommu *iommu = NULL; in intel_iommu_shutdown() local
4750 for_each_iommu(iommu, drhd) in intel_iommu_shutdown()
4751 iommu_disable_protect_mem_regions(iommu); in intel_iommu_shutdown()
4763 return container_of(iommu_dev, struct intel_iommu, iommu); in dev_to_intel_iommu()
4770 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in intel_iommu_show_version() local
4771 u32 ver = readl(iommu->reg + DMAR_VER_REG); in intel_iommu_show_version()
4781 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in intel_iommu_show_address() local
4782 return sprintf(buf, "%llx\n", iommu->reg_phys); in intel_iommu_show_address()
4790 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in intel_iommu_show_cap() local
4791 return sprintf(buf, "%llx\n", iommu->cap); in intel_iommu_show_cap()
4799 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in intel_iommu_show_ecap() local
4800 return sprintf(buf, "%llx\n", iommu->ecap); in intel_iommu_show_ecap()
4808 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in intel_iommu_show_ndoms() local
4809 return sprintf(buf, "%ld\n", cap_ndoms(iommu->cap)); in intel_iommu_show_ndoms()
4817 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in intel_iommu_show_ndoms_used() local
4818 return sprintf(buf, "%d\n", bitmap_weight(iommu->domain_ids, in intel_iommu_show_ndoms_used()
4819 cap_ndoms(iommu->cap))); in intel_iommu_show_ndoms_used()
4834 .name = "intel-iommu",
4860 pr_info("Intel-IOMMU force enabled due to platform opt in\n"); in platform_optin_force_iommu()
4863 * If Intel-IOMMU is disabled by default, we will apply identity in platform_optin_force_iommu()
4879 struct intel_iommu *iommu __maybe_unused; in probe_acpi_namespace_devices()
4883 for_each_active_iommu(iommu, drhd) { in probe_acpi_namespace_devices()
4922 struct intel_iommu *iommu; in intel_iommu_init() local
4925 * Intel IOMMU is required for a TXT/tboot launch or platform in intel_iommu_init()
4933 panic("tboot: Failed to initialize iommu memory\n"); in intel_iommu_init()
4965 * We exit the function here to ensure IOMMU's remapping and in intel_iommu_init()
4966 * mempool aren't setup, which means that the IOMMU's PMRs in intel_iommu_init()
4973 for_each_iommu(iommu, drhd) in intel_iommu_init()
4974 iommu_disable_protect_mem_regions(iommu); in intel_iommu_init()
4994 panic("tboot: Failed to reserve iommu ranges\n"); in intel_iommu_init()
5015 for_each_active_iommu(iommu, drhd) { in intel_iommu_init()
5016 iommu_device_sysfs_add(&iommu->iommu, NULL, in intel_iommu_init()
5018 "%s", iommu->name); in intel_iommu_init()
5019 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops); in intel_iommu_init()
5020 iommu_device_register(&iommu->iommu); in intel_iommu_init()
5027 cpuhp_setup_state(CPUHP_IOMMU_INTEL_DEAD, "iommu/intel:dead", NULL, in intel_iommu_init()
5035 for_each_iommu(iommu, drhd) { in intel_iommu_init()
5036 if (!drhd->ignored && !translation_pre_enabled(iommu)) in intel_iommu_init()
5037 iommu_enable_translation(iommu); in intel_iommu_init()
5039 iommu_disable_protect_mem_regions(iommu); in intel_iommu_init()
5060 struct intel_iommu *iommu = opaque; in domain_context_clear_one_cb() local
5062 domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff); in domain_context_clear_one_cb()
5067 * NB - intel-iommu lacks any sort of reference counting for the users of
5072 static void domain_context_clear(struct intel_iommu *iommu, struct device *dev) in domain_context_clear() argument
5074 if (!iommu || !dev || !dev_is_pci(dev)) in domain_context_clear()
5077 pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu); in domain_context_clear()
5083 struct intel_iommu *iommu; in __dmar_remove_one_dev_info() local
5091 iommu = info->iommu; in __dmar_remove_one_dev_info()
5095 if (dev_is_pci(info->dev) && sm_supported(iommu)) in __dmar_remove_one_dev_info()
5096 intel_pasid_tear_down_entry(iommu, info->dev, in __dmar_remove_one_dev_info()
5101 domain_context_clear(iommu, info->dev); in __dmar_remove_one_dev_info()
5107 spin_lock_irqsave(&iommu->lock, flags); in __dmar_remove_one_dev_info()
5108 domain_detach_iommu(domain, iommu); in __dmar_remove_one_dev_info()
5109 spin_unlock_irqrestore(&iommu->lock, flags); in __dmar_remove_one_dev_info()
5250 struct intel_iommu *iommu; in aux_domain_add_dev() local
5252 iommu = device_to_iommu(dev, NULL, NULL); in aux_domain_add_dev()
5253 if (!iommu) in aux_domain_add_dev()
5272 * iommu->lock must be held to attach domain to iommu and setup the in aux_domain_add_dev()
5275 spin_lock(&iommu->lock); in aux_domain_add_dev()
5276 ret = domain_attach_iommu(domain, iommu); in aux_domain_add_dev()
5282 ret = domain_setup_first_level(iommu, domain, dev, in aux_domain_add_dev()
5285 ret = intel_pasid_setup_second_level(iommu, domain, dev, in aux_domain_add_dev()
5289 spin_unlock(&iommu->lock); in aux_domain_add_dev()
5298 domain_detach_iommu(domain, iommu); in aux_domain_add_dev()
5300 spin_unlock(&iommu->lock); in aux_domain_add_dev()
5312 struct intel_iommu *iommu; in aux_domain_remove_dev() local
5320 iommu = info->iommu; in aux_domain_remove_dev()
5324 spin_lock(&iommu->lock); in aux_domain_remove_dev()
5325 intel_pasid_tear_down_entry(iommu, dev, domain->default_pasid, false); in aux_domain_remove_dev()
5326 domain_detach_iommu(domain, iommu); in aux_domain_remove_dev()
5327 spin_unlock(&iommu->lock); in aux_domain_remove_dev()
5336 struct intel_iommu *iommu; in prepare_domain_attach_device() local
5339 iommu = device_to_iommu(dev, NULL, NULL); in prepare_domain_attach_device()
5340 if (!iommu) in prepare_domain_attach_device()
5343 /* check if this iommu agaw is sufficient for max mapped address */ in prepare_domain_attach_device()
5344 addr_width = agaw_to_width(iommu->agaw); in prepare_domain_attach_device()
5345 if (addr_width > cap_mgaw(iommu->cap)) in prepare_domain_attach_device()
5346 addr_width = cap_mgaw(iommu->cap); in prepare_domain_attach_device()
5349 dev_err(dev, "%s: iommu width (%d) is not " in prepare_domain_attach_device()
5359 while (iommu->agaw < dmar_domain->agaw) { in prepare_domain_attach_device()
5381 …dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Con… in intel_iommu_attach_device()
5433 * 2D array for converting and sanitizing IOMMU generic TLB granularity to
5444 * X: indexed by iommu cache type
5472 * IOMMU cache invalidate API passes granu_size in bytes, and number of in to_vtd_size()
5484 struct intel_iommu *iommu; in intel_iommu_sva_invalidate() local
5498 iommu = device_to_iommu(dev, &bus, &devfn); in intel_iommu_sva_invalidate()
5499 if (!iommu) in intel_iommu_sva_invalidate()
5506 spin_lock(&iommu->lock); in intel_iommu_sva_invalidate()
5512 did = dmar_domain->iommu_did[iommu->seq_id]; in intel_iommu_sva_invalidate()
5559 qi_flush_piotlb(iommu, did, pasid, in intel_iommu_sva_invalidate()
5589 qi_flush_dev_iotlb_pasid(iommu, sid, in intel_iommu_sva_invalidate()
5597 dev_err_ratelimited(dev, "Unsupported IOMMU invalidation type %d\n", in intel_iommu_sva_invalidate()
5603 spin_unlock(&iommu->lock); in intel_iommu_sva_invalidate()
5633 pr_err("%s: iommu width (%d) is not " in intel_iommu_map()
5704 struct intel_iommu *iommu; in scalable_mode_support() local
5708 for_each_active_iommu(iommu, drhd) { in scalable_mode_support()
5709 if (!sm_supported(iommu)) { in scalable_mode_support()
5722 struct intel_iommu *iommu; in iommu_pasid_support() local
5726 for_each_active_iommu(iommu, drhd) { in iommu_pasid_support()
5727 if (!pasid_supported(iommu)) { in iommu_pasid_support()
5740 struct intel_iommu *iommu; in nested_mode_support() local
5744 for_each_active_iommu(iommu, drhd) { in nested_mode_support()
5745 if (!sm_supported(iommu) || !ecap_nest(iommu->ecap)) { in nested_mode_support()
5767 struct intel_iommu *iommu; in intel_iommu_probe_device() local
5769 iommu = device_to_iommu(dev, NULL, NULL); in intel_iommu_probe_device()
5770 if (!iommu) in intel_iommu_probe_device()
5773 if (translation_pre_enabled(iommu)) in intel_iommu_probe_device()
5776 return &iommu->iommu; in intel_iommu_probe_device()
5781 struct intel_iommu *iommu; in intel_iommu_release_device() local
5783 iommu = device_to_iommu(dev, NULL, NULL); in intel_iommu_release_device()
5784 if (!iommu) in intel_iommu_release_device()
5862 int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev) in intel_iommu_enable_pasid() argument
5876 spin_lock(&iommu->lock); in intel_iommu_enable_pasid()
5883 context = iommu_context_addr(iommu, info->bus, info->devfn, 0); in intel_iommu_enable_pasid()
5893 iommu->flush.flush_context(iommu, in intel_iommu_enable_pasid()
5894 domain->iommu_did[iommu->seq_id], in intel_iommu_enable_pasid()
5907 spin_unlock(&iommu->lock); in intel_iommu_enable_pasid()
5936 struct intel_iommu *iommu; in intel_iommu_enable_auxd() local
5940 iommu = device_to_iommu(dev, NULL, NULL); in intel_iommu_enable_auxd()
5941 if (!iommu || dmar_disabled) in intel_iommu_enable_auxd()
5944 if (!sm_supported(iommu) || !pasid_supported(iommu)) in intel_iommu_enable_auxd()
5947 ret = intel_iommu_enable_pasid(iommu, dev); in intel_iommu_enable_auxd()
6021 return info && (info->iommu->flags & VTD_FLAG_SVM_CAPABLE) && in intel_iommu_dev_has_feat()
6041 if (info->iommu->flags & VTD_FLAG_SVM_CAPABLE) in intel_iommu_dev_enable_feat()
6117 * thus not be able to bypass the IOMMU restrictions.
6123 "Skipping IOMMU quirk for dev [%04X:%04X] on untrusted PCI link\n", in risky_device()
6174 pci_info(dev, "Disabling IOMMU for graphics on this chipset\n"); in quirk_iommu_igfx()
6255 pci_info(dev, "BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); in quirk_calpella_no_shadow_gtt()
6284 pci_info(dev, "Skip IOMMU disabling for graphics\n"); in quirk_igfx_skip_te_disable()