Lines Matching full:gic
5 * Interrupt architecture for the GIC:
40 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
113 * The GIC mapping of CPU interfaces does not necessarily match
115 * by the GIC itself.
311 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); in gic_set_type()
320 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
339 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
340 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
355 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
363 * The GIC encodes the source CPU in GICC_IAR, in gic_handle_irq()
372 handle_domain_irq(gic->domain, irqnr, regs); in gic_handle_irq()
423 static u8 gic_get_cpumask(struct gic_chip_data *gic) in gic_get_cpumask() argument
425 void __iomem *base = gic_data_dist_base(gic); in gic_get_cpumask()
437 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); in gic_get_cpumask()
448 static void gic_cpu_if_up(struct gic_chip_data *gic) in gic_cpu_if_up() argument
450 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_cpu_if_up()
455 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) in gic_cpu_if_up()
472 static void gic_dist_init(struct gic_chip_data *gic) in gic_dist_init() argument
476 unsigned int gic_irqs = gic->gic_irqs; in gic_dist_init()
477 void __iomem *base = gic_data_dist_base(gic); in gic_dist_init()
484 cpumask = gic_get_cpumask(gic); in gic_dist_init()
495 static int gic_cpu_init(struct gic_chip_data *gic) in gic_cpu_init() argument
497 void __iomem *dist_base = gic_data_dist_base(gic); in gic_cpu_init()
498 void __iomem *base = gic_data_cpu_base(gic); in gic_cpu_init()
503 * Setting up the CPU map is only relevant for the primary GIC in gic_cpu_init()
507 if (gic == &gic_data[0]) { in gic_cpu_init()
509 * Get what the GIC says our CPU mask is. in gic_cpu_init()
515 cpu_mask = gic_get_cpumask(gic); in gic_cpu_init()
530 gic_cpu_if_up(gic); in gic_cpu_init()
553 * Saves the GIC distributor registers during suspend or idle. Must be called
554 * with interrupts disabled but before powering down the GIC. After calling
555 * this function, no interrupts will be delivered by the GIC, and another
558 void gic_dist_save(struct gic_chip_data *gic) in gic_dist_save() argument
564 if (WARN_ON(!gic)) in gic_dist_save()
567 gic_irqs = gic->gic_irqs; in gic_dist_save()
568 dist_base = gic_data_dist_base(gic); in gic_dist_save()
574 gic->saved_spi_conf[i] = in gic_dist_save()
578 gic->saved_spi_target[i] = in gic_dist_save()
582 gic->saved_spi_enable[i] = in gic_dist_save()
586 gic->saved_spi_active[i] = in gic_dist_save()
591 * Restores the GIC distributor registers during resume or when coming out of
593 * that occurred while the GIC was suspended is still present, it will be
595 * the GIC and need to be handled by the platform-specific wakeup source.
597 void gic_dist_restore(struct gic_chip_data *gic) in gic_dist_restore() argument
603 if (WARN_ON(!gic)) in gic_dist_restore()
606 gic_irqs = gic->gic_irqs; in gic_dist_restore()
607 dist_base = gic_data_dist_base(gic); in gic_dist_restore()
615 writel_relaxed(gic->saved_spi_conf[i], in gic_dist_restore()
623 writel_relaxed(gic->saved_spi_target[i], in gic_dist_restore()
629 writel_relaxed(gic->saved_spi_enable[i], in gic_dist_restore()
636 writel_relaxed(gic->saved_spi_active[i], in gic_dist_restore()
643 void gic_cpu_save(struct gic_chip_data *gic) in gic_cpu_save() argument
650 if (WARN_ON(!gic)) in gic_cpu_save()
653 dist_base = gic_data_dist_base(gic); in gic_cpu_save()
654 cpu_base = gic_data_cpu_base(gic); in gic_cpu_save()
659 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_save()
663 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_save()
667 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_save()
673 void gic_cpu_restore(struct gic_chip_data *gic) in gic_cpu_restore() argument
680 if (WARN_ON(!gic)) in gic_cpu_restore()
683 dist_base = gic_data_dist_base(gic); in gic_cpu_restore()
684 cpu_base = gic_data_cpu_base(gic); in gic_cpu_restore()
689 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_restore()
696 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_restore()
703 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_restore()
712 gic_cpu_if_up(gic); in gic_cpu_restore()
745 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
747 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
749 if (WARN_ON(!gic->saved_ppi_enable)) in gic_pm_init()
752 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
754 if (WARN_ON(!gic->saved_ppi_active)) in gic_pm_init()
757 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, in gic_pm_init()
759 if (WARN_ON(!gic->saved_ppi_conf)) in gic_pm_init()
762 if (gic == &gic_data[0]) in gic_pm_init()
768 free_percpu(gic->saved_ppi_active); in gic_pm_init()
770 free_percpu(gic->saved_ppi_enable); in gic_pm_init()
775 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
869 "irqchip/arm/gic:starting", in gic_smp_init()
904 * @cpu: the logical CPU number to get the GIC ID for.
1017 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); in gic_init_physaddr()
1028 struct gic_chip_data *gic = d->host_data; in gic_irq_domain_map() local
1034 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, in gic_irq_domain_map()
1040 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, in gic_irq_domain_map()
1044 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, in gic_irq_domain_map()
1139 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, in gic_init_chip() argument
1143 gic->chip = gic_chip; in gic_init_chip()
1144 gic->chip.name = name; in gic_init_chip()
1145 gic->chip.parent_device = dev; in gic_init_chip()
1148 gic->chip.irq_mask = gic_eoimode1_mask_irq; in gic_init_chip()
1149 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; in gic_init_chip()
1150 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; in gic_init_chip()
1153 if (gic == &gic_data[0]) { in gic_init_chip()
1154 gic->chip.irq_set_affinity = gic_set_affinity; in gic_init_chip()
1155 gic->chip.ipi_send_mask = gic_ipi_send_mask; in gic_init_chip()
1159 static int gic_init_bases(struct gic_chip_data *gic, in gic_init_bases() argument
1164 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1165 /* Frankein-GIC without banked registers... */ in gic_init_bases()
1168 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1169 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1170 if (WARN_ON(!gic->dist_base.percpu_base || in gic_init_bases()
1171 !gic->cpu_base.percpu_base)) { in gic_init_bases()
1179 unsigned long offset = gic->percpu_offset * core_id; in gic_init_bases()
1180 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = in gic_init_bases()
1181 gic->raw_dist_base + offset; in gic_init_bases()
1182 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = in gic_init_bases()
1183 gic->raw_cpu_base + offset; in gic_init_bases()
1188 /* Normal, sane GIC... */ in gic_init_bases()
1189 WARN(gic->percpu_offset, in gic_init_bases()
1191 gic->percpu_offset); in gic_init_bases()
1192 gic->dist_base.common_base = gic->raw_dist_base; in gic_init_bases()
1193 gic->cpu_base.common_base = gic->raw_cpu_base; in gic_init_bases()
1198 * The GIC only supports up to 1020 interrupt sources. in gic_init_bases()
1200 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; in gic_init_bases()
1204 gic->gic_irqs = gic_irqs; in gic_init_bases()
1207 gic->domain = irq_domain_create_linear(handle, gic_irqs, in gic_init_bases()
1209 gic); in gic_init_bases()
1213 * No secondary GIC support whatsoever. in gic_init_bases()
1226 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, in gic_init_bases()
1227 16, &gic_irq_domain_ops, gic); in gic_init_bases()
1230 if (WARN_ON(!gic->domain)) { in gic_init_bases()
1235 gic_dist_init(gic); in gic_init_bases()
1236 ret = gic_cpu_init(gic); in gic_init_bases()
1240 ret = gic_pm_init(gic); in gic_init_bases()
1247 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1248 free_percpu(gic->dist_base.percpu_base); in gic_init_bases()
1249 free_percpu(gic->cpu_base.percpu_base); in gic_init_bases()
1255 static int __init __gic_init_bases(struct gic_chip_data *gic, in __gic_init_bases() argument
1261 if (WARN_ON(!gic || gic->domain)) in __gic_init_bases()
1264 if (gic == &gic_data[0]) { in __gic_init_bases()
1268 * This is only necessary for the primary GIC. in __gic_init_bases()
1275 pr_info("GIC: Using split EOI/Deactivate mode\n"); in __gic_init_bases()
1278 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { in __gic_init_bases()
1280 gic_init_chip(gic, NULL, name, true); in __gic_init_bases()
1282 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); in __gic_init_bases()
1283 gic_init_chip(gic, NULL, name, false); in __gic_init_bases()
1286 ret = gic_init_bases(gic, handle); in __gic_init_bases()
1289 else if (gic == &gic_data[0]) in __gic_init_bases()
1297 struct gic_chip_data *gic; in gic_init() local
1305 gic = &gic_data[0]; in gic_init()
1306 gic->raw_dist_base = dist_base; in gic_init()
1307 gic->raw_cpu_base = cpu_base; in gic_init()
1309 __gic_init_bases(gic, NULL); in gic_init()
1312 static void gic_teardown(struct gic_chip_data *gic) in gic_teardown() argument
1314 if (WARN_ON(!gic)) in gic_teardown()
1317 if (gic->raw_dist_base) in gic_teardown()
1318 iounmap(gic->raw_dist_base); in gic_teardown()
1319 if (gic->raw_cpu_base) in gic_teardown()
1320 iounmap(gic->raw_cpu_base); in gic_teardown()
1351 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode()
1364 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode()
1381 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode()
1404 pr_warn("GIC: Adjusting CPU interface base to %pa\n", in gic_check_eoimode()
1435 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) in gic_of_setup() argument
1437 if (!gic || !node) in gic_of_setup()
1440 gic->raw_dist_base = of_iomap(node, 0); in gic_of_setup()
1441 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) in gic_of_setup()
1444 gic->raw_cpu_base = of_iomap(node, 1); in gic_of_setup()
1445 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) in gic_of_setup()
1448 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) in gic_of_setup()
1449 gic->percpu_offset = 0; in gic_of_setup()
1451 gic_enable_of_quirks(node, gic_quirks, gic); in gic_of_setup()
1456 gic_teardown(gic); in gic_of_setup()
1461 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1465 if (!dev || !dev->of_node || !gic || !irq) in gic_of_init_child()
1468 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); in gic_of_init_child()
1469 if (!*gic) in gic_of_init_child()
1472 gic_init_chip(*gic, dev, dev->of_node->name, false); in gic_of_init_child()
1474 ret = gic_of_setup(*gic, dev->of_node); in gic_of_init_child()
1478 ret = gic_init_bases(*gic, &dev->of_node->fwnode); in gic_of_init_child()
1480 gic_teardown(*gic); in gic_of_init_child()
1484 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); in gic_of_init_child()
1516 struct gic_chip_data *gic; in gic_of_init() local
1525 gic = &gic_data[gic_cnt]; in gic_of_init()
1527 ret = gic_of_setup(gic, node); in gic_of_init()
1535 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) in gic_of_init()
1538 ret = __gic_init_bases(gic, &node->fwnode); in gic_of_init()
1540 gic_teardown(gic); in gic_of_init()
1560 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1561 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1562 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1563 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1564 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1565 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1570 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1685 struct gic_chip_data *gic = &gic_data[0]; in gic_v2_acpi_init() local
1696 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); in gic_v2_acpi_init()
1697 if (!gic->raw_cpu_base) { in gic_v2_acpi_init()
1703 gic->raw_dist_base = ioremap(dist->base_address, in gic_v2_acpi_init()
1705 if (!gic->raw_dist_base) { in gic_v2_acpi_init()
1707 gic_teardown(gic); in gic_v2_acpi_init()
1720 * Initialize GIC instance zero (no multi-GIC support). in gic_v2_acpi_init()
1725 gic_teardown(gic); in gic_v2_acpi_init()
1729 ret = __gic_init_bases(gic, domain_handle); in gic_v2_acpi_init()
1731 pr_err("Failed to initialise GIC\n"); in gic_v2_acpi_init()
1733 gic_teardown(gic); in gic_v2_acpi_init()