Lines Matching +full:0 +full:x028
18 #define IO_STATUS 0x000
19 #define IO_RAW_STATUS 0x004
20 #define IO_ENABLE 0x008
21 #define IO_DISABLE 0x00C
22 #define IO_CURRENT 0x020
23 #define IO_RESET 0x028
24 #define IO_MAX_PRIOTY 0x02C
26 #define IO_IRQ_BASE 0x000
27 #define IO_FIQ_BASE 0x100
29 #define IO_INVERT_SEL 0x200
30 #define IO_STICKY_SEL 0x204
31 #define IO_PRIORITY_SEL 0x300
60 writel(~0, base + IO_DISABLE); in zevio_init_irq_base()
63 writel(0xF, base + IO_MAX_PRIOTY); in zevio_init_irq_base()
79 zevio_irq_io = of_iomap(node, 0); in zevio_of_init()
83 writel(~0, zevio_irq_io + IO_INVERT_SEL); in zevio_of_init()
86 writel(0, zevio_irq_io + IO_STICKY_SEL); in zevio_of_init()
89 memset_io(zevio_irq_io + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32)); in zevio_of_init()
101 clr, 0, IRQ_GC_INIT_MASK_CACHE); in zevio_of_init()
104 gc = irq_get_domain_generic_chip(zevio_irq_domain, 0); in zevio_of_init()
106 gc->chip_types[0].chip.irq_ack = zevio_irq_ack; in zevio_of_init()
107 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in zevio_of_init()
108 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in zevio_of_init()
109 gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE; in zevio_of_init()
110 gc->chip_types[0].regs.enable = IO_IRQ_BASE + IO_ENABLE; in zevio_of_init()
111 gc->chip_types[0].regs.disable = IO_IRQ_BASE + IO_DISABLE; in zevio_of_init()
112 gc->chip_types[0].regs.ack = IO_IRQ_BASE + IO_RESET; in zevio_of_init()
117 return 0; in zevio_of_init()