Lines Matching full:esdhc

3  * Freescale eSDHC i.MX controller driver for the platform bus.
27 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include "sdhci-esdhc.h"
120  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
121  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
122  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
123  * Define this macro DMA error INT for fsl eSDHC
143  * The flag tells that the ESDHC controller is an USDHC block that is
299 		.name = "sdhci-esdhc-imx25",
302 		.name = "sdhci-esdhc-imx35",
305 		.name = "sdhci-esdhc-imx51",
314 	{ .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
315 	{ .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
316 	{ .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
317 	{ .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
359 #define DRIVER_NAME "sdhci-esdhc-imx"
375 	ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");  in esdhc_dump_debug_regs()
419 		/* In FSL esdhc IC module, only bit20 is used to indicate the  in esdhc_readl_le()
420 		 * ADMA2 capability of esdhc, but this bit is messed up on  in esdhc_readl_le()
498 			 * card interrupt. This is an eSDHC controller problem  in esdhc_writel_le()
500 			 * and set D3CD bit will make eSDHC re-sample the card  in esdhc_writel_le()
799 			 * The esdhc has a design violation to SDHC spec which  in esdhc_writeb_le()
801 			 * detection circuit. But esdhc clears its SYSCTL  in esdhc_writeb_le()
823 			 * The eSDHC DAT line software reset clears at least the  in esdhc_writeb_le()
1942 		.name	= "sdhci-esdhc-imx",
1954 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");