347 	u32 ssc;  in gl9750_set_ssc()  local
351 	ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
354 	ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;  in gl9750_set_ssc()
357 	ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);  in gl9750_set_ssc()
358 	sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
365 	/* set pll to 205MHz and enable ssc */  in gl9750_set_ssc_pll_205mhz()
474 	u32 ssc;  in gl9755_set_ssc()  local
478 	pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);  in gl9755_set_ssc()
481 	ssc &= ~PCI_GLI_9755_PLLSSC_PPM;  in gl9755_set_ssc()
484 	ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);  in gl9755_set_ssc()
485 	pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);  in gl9755_set_ssc()
492 	/* set pll to 205MHz and enable ssc */  in gl9755_set_ssc_pll_205mhz()